Abstract: An electrostatic discharge protection device includes a first well comprising a MOS transistor; a second well comprising a first impurity region to which a first voltage is applied, and a second impurity region connected to an input/output pad, the second well being disposed adjacent to the first well; and a third well comprising a third impurity region to which the first voltage is applied, the third well being disposed adjacent to the second well.

Abstract: A method is disclosed for fabricating a trench transistor, in which there are formed, within an epitaxial layer deposited above a substrate of a first conductivity type, a trench and, within the trench, a gate dielectric and a gate electrode and, in a body region of a second conductivity type adjoining the trench a source region of the first conductivity type, a drift region of the first conductivity type forming a drain zone being formed at the end of the junction between the substrate and the epitaxial layer by means of one or more high-energy implantations, the lower end of the trench projecting into said drift region, and to a trench transistor of this type formed as a low-voltage transistor.

Abstract: A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region.

Abstract: The present invention generally relates to the deposition of nanowires and other nanoparticles on surfaces. According to one aspect of the invention, a fluid containing nanoscale objects, such as nanowires, is deposited on a surface having one or more relatively hydrophilic regions and one or more relatively hydrophobic regions. If the fluid is hydrophilic, it will preferentially be located in the relatively hydrophilic regions (or vice versa if the fluid is relatively hydrophobic). The fluid is then allowed to evaporate to cause the nanoscale objects to deposit. For instance, the rate of evaporation may be controlled so as to allow the nanoscale objects to substantially deposit at the centers of the regions and/or at a rate that causes the nanoscale objects to become substantially aligned. In some cases, the regions may be relatively small, e.g., having a minimum surface dimension of less than about 3000 nm. In one set of embodiments, one or more cylindrical droplets may be formed on the surface.

Abstract: A production method with release of movable mechanical parts of an electro-mechanical microsystem is disclosed. The method is characterized in that porous zones are formed on the front face of a first water of a semiconductor material. Patterns of a material able to constitute the movable mechanical parts of the electro-mechanical microsystem are then formed on the front face of the first water at the level of the porous zones and encapsulated in a sacrificial layer. Then a layer of a material withstanding an attack by a solvent of the sacrificial layer is deposited. The release of the movable mechanical parts is then executed by the rear face of the first water, through the porous zones, using a solvent of the sacrificial layer.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.

Abstract: A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nano structures.

Abstract: Disclosed herein is a method for producing nanowires. The method comprises the steps of providing a porous template with a plurality of holes in the form of tubes, filling the tubes with nanoparticles or nanoparticle precursors, and forming the filled nanoparticles or nanoparticle precursors into nanowires. According to the method, highly rectilinear and well-ordered nanowires can be produced in a simple manner.

Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.

Abstract: Semiconductor nanocrystals known as quantum dots (QD) are caged by being associated with a molecule such as an orth-Nitrobenzyl (ONB) group. The luminescence of the QD is suppressed until activated by violet or ultra violet light.

Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.

Abstract: Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer.

Abstract: A method for preparing a semiconductor structure for use in the manufacture of three dimensional transistors, the structure comprising a silicon substrate and an epitaxial layer, the epitaxial layer comprising an endpoint detection epitaxial region comprising an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination.

Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A carbon nanobud molecule (3, 9, 18, 23, 29, 36) having at least one fullerene part covalently bonded to the side of a tubular carbon molecule is used to interact with electromagnetic radiation in a device, wherein the interaction with electromagnetic radiation occurs through relaxation and/or excitation of the carbon nanobud molecule.

Abstract: An atomic layer deposition-deposited silicon dioxide/metal oxide-nanolaminate, comprising at least one layer of silicon dioxide and at least one layer of a metal oxide, and having a wet etch rate in an etchant, said wet etch rate being either greater or smaller than both a wet etch rate of a film of silicon dioxide and a wet etch rate of a film of said metal oxide in said etchant. Also provided is a method for manufacturing the same.

Abstract: A nitride semiconductor free-standing substrate includes a diameter of not less than 40 mm, a thickness of not less than 100 ?m, a dislocation density of not more than 5×106/cm2, an impurity concentration of not more than 4×1019/cm3, and a nanoindentation hardness of not less than 19.0 GPa at a maximum load in a range of not less than 1 mN and not more than 50 mN.

Abstract: A high breakdown voltage GaN-based transistor is provided on a silicon substrate. A nitride semiconductor device including: a silicon substrate, a SiO2 layer stacked on the silicon substrate and having a film thickness 100 nm or more; a silicon layer stacked on the SiO2 layer; a buffer layer stacked on the silicon layer; a GaN layer stacked on the buffer layer; an AlGaN layer stacked on the GaN layer; and a source electrode, a drain electrode, and a gate electrode that are formed on the AlGaN layer, and edge sidewalls of the silicon layer, the buffer layer, the GaN layer, and the AlGaN layer contact an increased-resistivity region.

Abstract: An octagonal structure of photodiodes using standard CMOS technology has been developed to serve as a de-multiplexer for spatially multiplexed fiber optic communication systems.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.

Abstract: An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound 6 is formed directly on a channel 5 of a transistor 1 comprising a source electrode 2, a drain electrode 3, a gate electrode 4 and the n-type channel 5 having a nanotube-shaped structure and provided between the source electrode 2 and the drain electrode 3.

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract: Provided is a carbon nanotube field effect transistor manufacturing method wherein carbon nanotube field effect transistors having excellent stable electric conduction property are manufactured with excellent reproducibility. After arranging carbon nanotubes to be a channel on a substrate, the carbon nanotubes are covered with an insulating protection film. Then, a source electrode and a drain electrode are formed on the insulating protection film. At this time, a contact hole is formed on the protection film, and the carbon nanotubes are connected with the source electrode and the drain electrode. Then, a wiring protection film, a conductive film and a plasma CVD film are sequentially formed on the insulating protection film, the source electrode and the drain electrode. In the field effect transistor thus manufactured, since the carbon nanotubes to be the channel are not contaminated and not damaged, excellent stable electric conductive property is exhibited.

Abstract: An integrated circuit structure includes a semiconductor substrate formed of a first semiconductor material; two insulators in the semiconductor substrate; and a semiconductor region between and adjoining sidewalls of the two insulators. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material, and has a width less than about 50 nm.

Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Abstract: A multijunction solar cell comprising an upper first solar subcell having a first band gap; a middle second solar subcell adjacent to the first solar subcell and having a second band gap smaller than the first band gap, and having a base layer and an emitter layer; a graded interlayer adjacent to said second solar subcell, having a third band gap greater than the second band gap; a lower solar subcell adjacent to the grading interlayer, having a fourth band gap smaller than said second band gap such that the third subcell is lattice mismatched with respect to said second subcell; and a metal electrode layer deposited on said lower subcell and having a coefficient of thermal expansion substantially similar to that of the subcells.

Abstract: Compositions comprising a single-phase rare-earth dielectric disposed on a substrate. Embodiments of the present invention provide the basis for high-K gate dielectrics in conventional integrated circuits and high-K buried dielectrics as part of a semiconductor-on-insulator wafer structure.

Abstract: Substrate structures and methods of manufacturing the substrate structures. A substrate structure is manufactured by forming a protrusion area of a substrate under a buffer layer, and forming a semiconductor layer on the buffer layer, thereby separating the substrate from the buffer layer except in an area where the protrusion is formed. The semiconductor layer on the buffer layer not contacting the substrate has freestanding characteristics, and dislocation or cracks may be reduced and/or prevented.

Abstract: A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; a butler layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be shaped as an island having a size that does not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal defects when the Ge layer is annealed at a certain temperature.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract: A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.

Abstract: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid on top thereof. The nitride semiconductor layer has a depression immediately above the dislocation-concentrated region, and has, in a region thereof other than the depression, a high-quality quantum well active layer with good flatness and without cracks, a layer that, as is grown, readily exhibits p-type conductivity, and a stripe-shaped laser light waveguide region. The laser light waveguide region is formed above the low-dislocation region. This helps realize a nitride semiconductor laser device that offers a longer life.

Abstract: A semiconductor structure is formed of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase on a (0001) oriented semiconductor substrate. The structure comprises a bottom cladding layer, a top cladding layer, and a diffusion region positioned between the cladding layers for diffusing light propagating within the semiconductor structure. The diffuse region has refractive index different from those of the cladding layers and non-flat surfaces for providing light diffusing interfaces between the diffusion region and the cladding layers. According to the invention, the diffusion region comprises a plurality of diffusion layers, compositions and thicknesses of said diffusion layers having been chosen to avoid formation of strain-induced dislocations in the diffusion region, and adjacent diffusion layers having different refractive indices in order to further enhance the diffusion efficiency.

Abstract: This invention aims at providing an inexpensive semiconductor device having a parasitic diode and lowering an hfe of a parasitic PNP transistor and a manufacturing method thereof. Such semiconductor device includes a P-type silicon substrate and a gate electrode formed above the P-type silicon substrate. The P-type silicon substrate includes an N-type well layer, an N-type buried layer, a P-type body layer, an N-type source layer formed in the P-type body layer, and a drain contact layer formed in the N-type well layer. The P-type body layer and the N-type source layer are formed by self alignment that uses the gate electrode as a mask. The N-type drain contact layer is formed opposite the N-type source layer across the P-type body layer formed below the gate electrode. The N-type buried layer is formed below the P-type body layer.

Abstract: A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1.

Abstract: To provide a semiconductor device which includes a P-type Si substrate, an ESD protection element, and a protected element. The ESD protection element includes a source N-type diffusion region, and a high-concentration P-type diffusion region formed from under the source N-type diffusion region to at least under part of a gate electrode, covering the source N-type diffusion region within the P-type Si substrate, and having a higher P-type impurity concentration than the P-type Si substrate. The protected element includes a drain N-type diffusion region, and a low-concentration P-type diffusion region that is in contact with the drain N-type diffusion region within the P-type Si substrate. The drain electrode of the ESD protection element and the drain electrode of the protected element are connected, and the high-concentration P-type diffusion region 103 has a higher P-type impurity concentration than the low-concentration P-type diffusion region.

Abstract: A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region. A device comprises a semiconductor layer (6); a first doped region (5) within the semiconductor layer; a second doped region (7) within the first doped region (5); and a silicon layer (9) disposed over a part of the semiconductor layer; wherein the silicon layer is disposed over a part of the first doped region (5) but not over the second doped region (7).

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode 8 is provided on the bottom surface or the top surface of the field effect transistor. When the body electrode 8 is provided on the bottom surface, a p-type GaN layer 4 is provided on a p-type Si substrate 2 via a buffer layer 3 comprising a plurality of AlN layers 31 and GaN layers 32, with the top layer of that buffer layer 3 being a thin AlN layer 31, and the body electrode 8 being formed on the bottom surface of the p-type Si substrate. When the body electrode 8 is provided on the top surface, a p-type GaN layer 4 is provided on a sapphire substrate 21 and an AlGaN layer 13 is provided on the area under the source electrode 5 and drain electrode 6, with the body electrode 8 being provided on top of the AlGaN layer 13. Holes 20 that are generated by an avalanche phenomenon run through the body electrode 8.

Abstract: A semiconductor wafer includes a substrate, a buffer region formed on one main surface of the substrate and formed from a compound semiconductor, and a main semiconductor region formed in the buffer region and formed from a compound semiconductor, wherein the buffer region includes a first multi-layer structured buffer region and a second multi-layer structured buffer region stacked with a plurality of alternating first layers and second layers, and a single layer structured buffer region arranged between the first multi-layer structured buffer region and the second multi-layer structured buffer region, the first layer is formed from a compound semiconductor which has a lattice constant smaller than a lattice constant of a material which forms the substrate, the second layer is formed from a compound semiconductor which has a lattice constant between a lattice constant of a material which forms the substrate and a lattice constant of a material which forms the first layer, and wherein the single layer structu