Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer that comprises composite laminations of which a first semiconductor layer, that is formed of a compound semiconductor of a nitride system, that has a lattice constant to be as smaller than that of such the substrate, and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and a second semiconductor layer that is formed of a compound semiconductor of a nitride system are formed as alternately on to such the substrate; a semiconductor operation layer that is formed of a compound semiconductor of a nitride system and that is formed on to such the buffer layer; and a dislocation reduction layer, which comprises a lower layer region and an upper layer region that are formed at any location at an inner side of such the buffer layer and that comprise an interface of a concave and convex shape therebetween, at which a threading dislocation that draws from such the lower layer region toward such the upper l

Abstract: This invention relates to the fabrication of nanowires for electrical and electronic applications. A method of growing silicon nanowires using an alumina template is disclosed whereby the aluminum forming the alumina is also used as the catalyst for growing the silicon nanowires in a VLS (CVD) process and as the semiconductor dopant. In addition, various techniques for masking off parts of the aluminum and alumina in order to maintain electrical isolation between device layers is disclosed.

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract: A Semiconductor component that contains AlxGayIn1-x-yAszSb1-z, whereby the parameters x, y, and z are selected such that a bandgap of less than 350 meV is achieved, whereby it features a mesa-structuring and a passivation layer containing AlnGa1-nAsmSb1-m is applied at least partially on at least one lateral surface of the structuring, and the parameter n is selected in the range of 0.4 to 1 and the parameter m in the range of 0 to 1.

Abstract: A semiconductor nanowire is coated with a chemical coating layer that comprises a functional material which modulates the quantity of free charge carriers within the semiconductor nanowire. The outer surface of the chemical coating layer includes a chemical group that facilitates bonding with molecules to be detected through electrostatic forces. The bonding between the chemical coating layer and the molecules alters the electrical charge distribution in the chemical coating layer, which alters the amount of the free charge carriers and the conductivity in the semiconductor nanowire. The coated semiconductor nanowire may be employed as a chemical sensor for the type of chemicals that bonds with the functional material in the chemical coating layer. Detection of such chemicals may indicate pH of a solution, a vapor pressure of a reactive material in gas phase, and/or a concentration of a molecule in a solution.

Abstract: A semiconductor device is formed on a semiconductor substrate, which is comprised of: a base substrate; and a multilayer being formed on the base substrate and having a surface serving for an interface with the semiconductor device, the multilayer including alternating layers of a first compound semiconductor and a second compound semiconductor materially distinguishable from the first compound semiconductor, one selected from the group consisting of the first compound semiconductor and the second compound semiconductor being doped with one selected from the group consisting of carbon and transition elements.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.

Abstract: Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

Abstract: A semiconductor device including fin-FETs capable of suppressing both OFF-current resulting from the short channel effect and junction leakage, and a manufacturing method thereof are provided. A semiconductor device comprises: an active region defined to have a crank shape by an STI region formed on a semiconductor substrate, the active region having an upper surface higher than an upper surface of the STI region; a source region and a drain region formed on both ends of the active region, respectively; a channel region formed between the source region and the drain region in the active region; and a gate electrode covering an upper surface and side surfaces of a central portion of the active region including the channel region.

Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.

Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature, at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.

Abstract: Nanotube electronic devices exhibit selective affinity to disparate nanotube types. According to an example embodiment, a semiconductor device exhibits a treated substrate that selectively interacts (e.g., chemically) with nanotubes of a first type, relative to nanotubes of a second type, the respective types including semiconducting-type and metallic-type nanotubes. The selective interaction is used to set device configuration characteristics based upon the nanotube type. This selective-interaction approach can be used to set the type, and/or characteristics of nanotubes in the device.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.

Abstract: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid on top thereof. The nitride semiconductor layer has a depression immediately above the dislocation-concentrated region, and has, in a region thereof other than the depression, a high-quality quantum well active layer with good flatness and without cracks, a layer that, as is grown, readily exhibits p-type conductivity, and a stripe-shaped laser light waveguide region. The laser light waveguide region is formed above the low-dislocation region. This helps realize a nitride semiconductor laser device that offers a longer life.

Abstract: An ESD protection circuit using an N-type extended drain silicon controlled rectifier (N-EDSCR) and a method for fabricating the same are provided. An electro-static discharge (ESD) protection circuit includes a substrate, a well formed in the substrate, a drift region having a predetermined portion overlapped with the well, a plurality of first diffusion layers respectively formed in the well and the drift region, a plurality of second diffusion layers respectively formed in the well and the drift region, wherein corresponding first and second diffusion layers in the well are formed separately from each other and those in the drift region are formed adjacent to each other, a source region formed in a manner of surrounding a second conductive type diffusion layer inside the well, and a gate electrode formed on the well between the source and the drift region.

Abstract: A method of fabricating an organic electronic device is provided. The organic electronic device has a structure including an upper conductive layer and an underlying layer immediately beneath said upper conducting layer and having at least one solution process able semiconducting layer. The upper conducting layer preferably has a thickness of between 10 nm and 200 nm.

Abstract: A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment.

Abstract: A light receiving element 1 has a semiconductor substrate 101; a first mesa 11 provided over the semiconductor substrate 101, and having an active region and a first electrode (p-side electrode 111) provided over the active region; a second mesa 12 provided over the semiconductor substrate 101, and having a semiconductor layer and a second electrode (n-side electrode 121) provided over the semiconductor layer; and a third mesa 13 provided over the semiconductor substrate 101, and having a semiconductor layer, wherein the third mesa 13 is arranged so as to surround the first mesa 11.

Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Abstract: A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).

Abstract: A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract: An SOI substrate comprising a carrier substrate, a dielectric layer and a semiconductor layer. A continuous pn junction is realized in the semiconductor layer, which pn junction can be produced by applying differently doped partial layers on the SOI substrate. In this way, it is possible to use an SOI substrate for producing semiconductor components and, in particular, rear side diodes.

Abstract: An electronic device includes a primary nanowire of a first conductivity type, and a secondary nanowire of a second conductivity type extending outwardly from the primary nanowire. A doped region of the second conductivity type extends from the secondary nanowire into at least a portion of the primary nanowire.

Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

Abstract: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.

Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.

Abstract: A flat panel display is provided. The flat panel display includes a light emitting device and two or more thin film transistors (TFTs) having semiconductor active layers having channel regions, where the thickness of the channel regions of the TFTs are different from each other. Thus, higher switching properties of a switching TFT can be maintained, a more uniform brightness of a driving TFT can be satisfied, and a white balance can be satisfied without changing a size of the TFT active layer.

Abstract: A method for electrically connecting semiconductor layers using a layer less than 150 nm thick of a semiconductor material that exhibits strong piezoelectric and/or spontaneous electrical polarization to provide a tunnel junction that electrically connects the semiconductor layers. The semiconductor material that exhibits strong piezoelectric and/or spontaneous electrical polarization comprises an interface between differing (Al,In,Ga)N alloys. The tunnel junction may be between p-type and n-type semiconductor layers, or it may be between two n-type or p-type semiconductor layers. Stacked Schottky diodes or stacked photo-active junctions may be fabricated using this method.

Abstract: Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as transistors which turn on or turn off only when a gate voltage is applied. A number of these transistors are constructed in complementary fashion and/or have insulating regions built in and serve as a dummy.

Abstract: The invention concerns a semiconductor structure comprising at least one first material region and a second material region, whereby the second material region epitaxially surrounds the first material region and forms a boundary surface. The structure is characterized in that Fermi level pinning is present on the non-epitaxial boundary surface of the second material region located opposite the boundary surface of both material regions, and the first material region forms a quantum well for free charge carriers.