Abstract: Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT element including a collector region; a FWD element including a cathode region adjacent to the collector region; a base layer on the substrate; multiple trench gate structures including a gate electrode. The base layer is divided by the trench gate structures into multiple first and second regions. Each first region includes an emitter region contacting the gate electrode. Each first region together with the emitter region is electrically coupled with an emitter electrode. The first regions include collector side and cathode side first regions, and the second regions include collector side and cathode side second regions. At least a part of the cathode side second region is electrically coupled with the emitter electrode, and at least a part of the collector side second region has a floating potential.

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: Electrically isolated, deep trench isolation (DTI) structures, are formed in a wafer, and a portion of the DTI structures are converted to electrically connected structures to provide a shielding function, or to provide connection to deep buried layers. In one aspect, DTI structures include a polysilicon filling over a liner layer disposed on the inner surface of a deep trench, the polysilicon is removed by isotropic etching, and the deep trench is re-filled with a conductive material. Alternatively, the polysilicon filling remains and a contact is formed to provide an electrical connection to the polysilicon. In another aspect, a deep trench is disposed in the wafer such that a lower portion thereof is located within a deep buried layer, and after the polysilicon is removed, an anisotropic etch removes a portion of the deep trench liner from the bottom of the deep trench, thereby allowing a tungsten deposition to make electrical contact with the deep buried layer.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

Abstract: A trench IGBT is disclosed. One embodiment includes an embedded structure arranged above a collector region and selected from a group consisting of a porous semiconductor region, a cavity, and a semiconductor region including additional scattering centers for holes, the embedded structure being arranged below the body contact region such that the embedded structure and the body contact region overlap in a horizontal projection.

Abstract: A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick gate electrode and the integral first layer also provides a first part of a stack of materials which constitute a thick trench sidewall insulating layer for a thin field plate. Consistent with an example embodiment, there is a method of manufacture. A hardmask used to etch the trenches is removed before providing the silicon dioxide layer. The layer is then protected by successive selective etching of the oxide layer and the nitride layer in the upper parts of the trenches. After the gate electrodes are provided, layers for the channel accommodating regions and source regions may be formed through the oxide layer on the upper surface.

Abstract: Provided is a manufacturing method of a semiconductor device wherein the generation of voids is prevented in aluminum-based electrodes or the like. The method is suitable for manufacturing a semiconductor device adapted for vehicles, which is required to have a high reliability. However, it is very difficult that power semiconductor devices such as power MOSFETs, in particular, trench gate type power MOS devices are formed without having any void since the thickness of aluminum-based electrodes thereof is as large as about 3500 to 5500 nm (2.5 ?m or more). In the present invention, a method is provided wherein at the time of forming an aluminum-based electrode metal film positioned over a wafer and having a thickness of 2.5 ?m or more over a highland/lowland-repeated region in a line and space form by sputtering, the temperature of the wafer is set to 400° C. or higher and lower than 500° C.

Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Abstract: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 ?m.

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract: A high voltage device with constant current source and the manufacturing method thereof. The device includes a P type silicon substrate (1), an oxide layer (6), a drain metal (2), a source metal (3), a gate metal (4), a P+substrate contact region (51), a N+drain region (52), an N+source region (53), an N?channel region (54) connecting the said N+drain region (52) and N+source region (53), and an N?drain region (92) enveloping the said N+drain region (52); the drain metal (2) fills drain through hole (82) and connects the N+drain region (52); the source metal (3) fills source through hole (83), and connects the N+source region (53) and P+substrate contact region (51); the source metal (3) and gate metal (4) are electrically connected by connecting metal (34). The manufacturing method includes steps of forming N+drain region, N+source region, N?drain region, P+substrate contact region, N?drain region and metal layer.

Abstract: A power semiconductor component is described. One embodiment provides a semiconductor body having an inner zone and an edge zone. A base zone of a first conduction type is provided. The base zone is arranged in the at least one inner zone and the at least one edge zone. An emitter zone of a second conduction type is provided. The emitter zone is arranged adjacent to the base zone in a vertical direction of the semiconductor body. A field stop zone of the first conduction type is provided. The field stop zone is arranged in the base zone and has a first field stop zone section having a first dopant dose in the edge zone and a second field stop zone section having a second dopant dose in the inner zone. The first dopant dose is higher than the second dopant dose.

Abstract: A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; an annular deep trench penetrating the semiconductor layer in the depth direction to surround an element forming region; a drain region of a second conductivity type formed in a surface layer portion of the semiconductor layer in the element forming region; a drift region of the second conductivity type formed in the surface layer portion of the semiconductor layer to come into contact with the drain region in the element forming region; a body region of the first conductivity type formed in the surface layer portion of the semiconductor layer at an interval from the drift region in the element forming region; a source region of the second conductivity type formed in a surface layer portion of the body region; and a first high-concentration buried region, formed in the semiconductor layer between a portion opposed to the source region in the depth direction and the deep trench, having a high

Abstract: A semiconductor device which can avoid increase of a conduction loss of an IGBT, secure a low noise characteristic and also reduce a switch loss. The switching device is of a trench gate type, in which a drift n? layer 110 is exposed to its main surface to a floating p layer 126 and to trench gates. In other words, the floating p layer 126 is provided within the drift n? layer 110 to be spaced from the trench gates.

Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.

Abstract: The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

Abstract: An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

Abstract: A semiconductor device having both vertical and horizontal type gates and a method for fabricating the same for obtaining high integration of the semiconductor device and integration with other devices while also maximizing the breakdown voltage and operational speed and preventing damage to the semiconductor device.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first plane-like metal layer and the N plane-like metal layers are located separate planes. First and second drain regions have a symmetric shape across at least one of horizontal and vertical centerlines. First and second gate regions have a first shape that surrounds the first and second drain regions, respectively. First and second source regions are arranged adjacent to and on one side of the first gate region, the second gate region and the connecting region. The first source region, the second source region, the first drain region and the second drain region communicate with at least two of the N plane-like metal layers.

Abstract: To provide a semiconductor device in which dielectric breakdown strength in a peripheral region is increased without increasing on-resistance. An IGBT comprises a body region, guard ring, and collector layer. The body region is formed within an active region in a surface layer of a drift layer. The guard ring is formed within a peripheral region in the surface layer of the drift layer, and surrounds the body region. The collector layer is formed at a back surface side of the drift layer, and is formed across the active region and the peripheral region. A distance F between a back surface of the guard ring and the back surface of the drift layer is greater than a distance between a back surface of the body region and the back surface of the drift layer. A thickness H of the collector layer in the peripheral region is smaller than a thickness D of the collector layer in the active region.

Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

Abstract: The present invention provides a semiconductor apparatus having high reliability with respect to a withstand voltage, leakage characteristics, etc. by disposing a structure of preventing stress occurring by metal wiring from directly acting on a trench relating to the semiconductor apparatus having a trench gate.

Abstract: A semiconductor device in which both an IGBT element region and a diode element region exist in the same semiconductor substrate includes a low lifetime region, which is formed in at least a part of a drift layer within the diode element region and shortens the lifetime of holes. A mean value of the lifetime of holes in the drift layer that includes the low lifetime region is shorter within the IGBT element region than within the diode element region.

Abstract: A semiconductor device with switch electrode and gate electrode and a method for switching a semiconductor device. One embodiment provides a semiconductor substrate with an emitter region, a drift region, a body region and a source region. The drift region is formed between the emitter and the body region while the body region is formed between the drift and the source region. A first trench structure extends from the source region at least partially into the drift region. The first trench structure includes a gate electrode arranged next to the body region and a switch electrode arranged in portions next to the drift region, wherein the switch and gate electrodes are electrically insulated from each other in the trench structure. A first gate driver is electrically connected to the gate electrode while a second gate driver is electrically connected to the switch gate.

Abstract: A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the die at one edge of the die. Various packages for the die having a reduced foot print on a support substrate are disclosed.

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract: A semiconductor device includes an insulated gate transistor and a resistor. The insulated gate transistor includes a plurality of first cells for supplying electric current to a load and a second cell for detecting an electric current that flows in the first cells. A gate terminal of the plurality of first cells is coupled with a gate terminal of the second cell and a source terminal of the plurality of first cells is coupled with a source terminal of the second cell on a lower potential side. The resistor has a first terminal coupled with a drain terminal of the second cell and a second terminal coupled with a drain terminal of the first cells on a higher potential side. A gate voltage of the insulated gate transistor is feedback-controlled based on an electric potential of the resistor.

Abstract: A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.

Abstract: A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to be formed, the first site being disposed under the first gate insulating film in the active region; forming a gate electrode on each of the first gate insulating film and the second gate insulating film; and introducing an impurity of the first conductivity type into the first site and a second site where a second body region is to be formed, the second site being disposed under the second gate insulating film in the active region, to form the first body region and the second body region, respectively.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

Abstract: In a high voltage MOS transistor, in a portion immediately below the gate electrode, peaks of concentration distribution in depth direction of a first conductivity type impurity and a second conductivity type impurity in the drain offset region are in the same depth, the second conductivity type impurity being higher concentrated than the first conductivity type impurity.

Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least a gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises an at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

Abstract: An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.

Abstract: Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.

Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.

Abstract: A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of ion-doped deep wells, and the ion-doped deep wells are separated but partially linked with each other.

Abstract: A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

Abstract: A power semiconductor device includes: a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on a first semiconductor layer and alternately arranged along at least one direction parallel to an upper face of the first semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively formed in an upper face of the second and third semiconductor layers; and a control electrode formed above the second, third and fourth semiconductor layers via a gate insulating film. The control electrode includes: first portions periodically arranged along a first direction selected from arranging directions of the third semiconductor layer, the third semiconductor layer has a shortest arrangement period in the first direction, and second portions periodically arranged along a second direction, the second direction being parallel to the upper face of the first semiconductor layer and crossing the first direction.