Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.

Abstract: A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one nonsemiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A gate wiring electrode is formed into a ladder-like pattern. Moreover, between source electrodes and drain electrodes in the entire Switch MMIC, the gate wiring electrodes are disposed. Furthermore, at a cross part between the gate wiring electrode and the source electrode or the drain electrode, a nitride film having a large relative dielectric constant and a polyimide or a hollow part having a small relative dielectric constant are disposed. Accordingly, a capacitance at the cross part is reduced. Thus, a second harmonic wave level can be lowered. Moreover, a leak of a high-frequency signal between the drain electrode and the source electrode can be prevented. Thus, a third harmonic level can be lowered. Consequently, distortion characteristics of the Switch MMIC can be significantly improved.

Abstract: An LDMOS transistor includes a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, a drain well of a first conductivity type formed in the substrate so as to include a gate region covered with the gate electrode, a channel well of a second conductivity type formed in the drain well in a partially overlapped relationship with the gate region, a source region of the first conductivity type formed in the channel well in an overlapping manner or adjacent with a side surface of the gate electrode, a medium-concentration drain region of the first conductivity type having an intermediate concentration level and formed in the drain well at a side opposing to the source region in a manner partially overlapping with the gate region, the medium-concentration drain region being formed with a separation from the channel well, a drain region of the first conductivity type formed in the medium-concentration drain region with a separation from the gate region, a low

Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Abstract: An igniter of the present invention has an insulated gate semiconductor device having a collector terminal, an emitter terminal and a gate terminal, a current control circuit which limits current by controlling voltage at the gate terminal when current for flowing through the insulated gate semiconductor device exceeds a fixed value, a voltage monitor circuit for detecting a potential of the collector, and a control current adjusting circuit for controlling current which flows through the gate terminal by receiving output from the voltage monitor circuit.