Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate under the gate metal runner at a termination area. At least one of the trench-gate fingers intersects with the trenched gate under the gate metal runner near the termination area having trench intersection regions vulnerable to have a polysilicon void and seam developed therein.

Abstract: A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.

Abstract: A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench.

Abstract: A cell of a semiconductor device comprises a substrate of n-type with a trench formed in a portion of a first main surface of the substrate and filled with insulator. Two device-feature regions are formed beneath the first main surface of the substrate, the first one at one side and the second one at the other side of the trench. A region of a p-type and/or a region of metal is formed in the first device feature region and is connected to a first electrode. A p-n junction is formed in the second device feature region and the p-region of the p-n junction is connected to a second electrode. A U-shaped region is formed between the two device regions. An IGBT without tail during turning-off can be fabricated with a simple process at a low cost.

Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

Abstract: The invention provides a semiconductor structure. A first type body doped region is deposited on a first type substrate. A first type heavily-doped region having a finger portion with an enlarged end region is deposited on the first type body doped region. A second type well region is deposited on the first type substrate. A second type heavily-doped region is deposited on the second type well region. An isolation structure is deposited between the first type heavily-doped region and the second type heavily-doped region. A gate structure is deposited on the first type substrate between the first type heavily-doped region and the isolation structure.

Abstract: A semiconductor component is described. In one embodiment, the semiconductor component includes a semiconductor body with a first side and a second side. A drift zone is provided, which is arranged in the semiconductor body below the first side and extends in a first lateral direction of the semiconductor body between a first and a second doped terminal zone. At least one field electrode is provided, which is arranged in the drift zone, extends into the drift zone proceeding from the first side and is configured in a manner electrically insulated from the semiconductor body.

Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

Abstract: A high-breakdown voltage semiconductor switching device includes a resurf region of a second conductivity type; a base region of a first conductivity type formed to be adjacent to the resurf region; an emitter/source region of the second conductivity type formed in the base region to be spaced from the resurf region; a gate electrode formed to cover a portion of the emitter/source region and a portion of the resurf region; a drain region of the second conductivity type formed in the resurf region to be spaced from the base region; and a collector region of the first conductivity type formed in the resurf region to be spaced from the base region. Furthermore, it includes an electrode connected to the collector region and the drain region and an electrode connected to the base region and the emitter/source region.

Abstract: An n-type buffer region 6 is arranged between an n? drift region 1 and a p-type collector region 7, and has a higher impurity concentration than n? drift region 1 Assuming that ? represents the ratio (WTA/WTB) between WTA expressed as: WTA = 2 ? ? s ? ? 0 ? V qNd and the thickness WTB of the drift region held between the base region and the buffer region, the ratio (DC/DB) of the net dose DC of the collector region with respect to the net dose DB of the buffer region is at least ?. Thus, a semiconductor device capable of ensuring a proper margin of SCSOA resistance can be obtained.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes an offset body region.

Abstract: In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as to be aligned in a second direction perpendicular to a first direction going from a collector region of the first conductivity type, which is formed so as to be spaced away from the base region, toward the base region. The width of the sense region, the width of the emitter region, the width of a part of the base region that is adjacent to the sense region, and the width of a part of the base region that is adjacent to the emitter region in the second direction are set in such a manner that a sense ratio varies in a desired manner in accordance with variation in collector current.

Abstract: A lateral DMOS device includes a body diode region and a protective diode region. The body diode region has a second conduction type well region formed in a first conduction type semiconductor substrate, the second conduction type well region including a first conduction type body region and a drain region each formed in the second conduction type well region, a first conduction type impurity region and a source region formed in the first conduction type body region, and a gate insulating film and a gate electrode formed on the first conduction type semiconductor substrate. The first conduction type body region and the second conduction type well region compose a body diode. In the protective diode region, the first conduction type impurity region is formed at a prescribed interval and the first conduction type body region and the second conduction type well region compose a protective diode.

Abstract: A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region with the second impurity region. A control electrode layer is opposite to the second impurity region with an insulating film interposed. That portion of the second main surface which is opposite to the portion of the first main surface where the first impurity region is formed surrounds the regions for forming the fourth and fifth impurity regions of the second main surface, and it is a region of the first conductivity type or a region of the second conductivity type having impurity concentration not higher than that of the first impurity region.

Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Abstract: In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: A power semiconductor device includes a power device and a current sense device formed in a common semiconductor region.

Abstract: An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 ?m resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 ?m and resistivity in te range of 14 to 18 ohm cm.

Abstract: There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

Abstract: A semiconductor device including a horizontal unit semiconductor element, the horizontal unit semiconductor element including: a) a semiconductor substrate of a first conductivity type; b) a semiconductor region of a second conductivity type formed on the semiconductor substrate; c) a collector layer of the first conductivity type formed within the semiconductor region; d) a base layer of the first conductivity type having an endless shape and formed within the semiconductor region such that the base layer is off the collector layer but surrounds the collector layer; and e) a first emitter layer of the second conductivity type formed in the base layer, the horizontal unit semiconductor element controlling, within a channel region formed in the base layer, movement of carriers between the first emitter layer and the collector layer, wherein the first emitter layer is formed by plural unit emitter layers which are formed along the base layer.

Abstract: An integrated circuit comprises first and second drain regions have a generally rectangular shape. First, second and third source regions have a generally rectangular shape, wherein the first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. Fourth and fifth source regions, wherein the fourth source region is arranged adjacent to third sides of the first and second drain regions and wherein the fifth source region is arranged adjacent to fourth sides of the first and second drain regions. A gate region is arranged between the first, second, third, fourth and fifth source regions and the first and second drain regions. First and second drain contacts that are arranged in the first and second drain regions.

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region of the first conductive type formed in the base region. Also, the semiconductor device includes a buffer layer of the first conductive type formed on the second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity therein of approximately 5×1015 cm?3 or less, and the collector layer has a maximal concentration of the second conductive type impurity therein of approximately 1×1017 cm?3 or more. Further, the ratio of the maximal concentration of the collector layer to the maximal concentration of the buffer layer being greater than 100.

Abstract: The IGBT is described here that exhibits high breakdown voltage, low on-voltage together with high turn-off speed. The collector of IGBT is formed on the backside of the wafer which has n type float zone. Methods for the p-type collector is implemented by depositing a layer of BSG which is 0.05˜0.1 um on the backside of the wafer and removing it after short time deposition. A thin and high surface concentration p+ layer acts as P type collector of the IGBT is formed on the bottom surface of the wafer. The back metal electrode is sintered to form ohmic contact on the P type collector with high surface concentration. The hole injection efficiency is decreased with a thin layer p+ layer which hat means no P implantation is needed to form the collector and the speed performance of the IGBT is therefore improved.

Abstract: A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and the first width is equal to a product of the second impurity concentration and the second width. The first width is equal to or smaller than 4.5 ?m. The first impurity concentration is lower than a predetermined concentration satisfying a RESURF condition. A ratio between on-state resistances of the device at 27° C. and at 150° C. is smaller than 1.8.

Abstract: A trench MOSFET includes mesa regions between the trenches. The mesa regions are connected to an emitter electrode to fix the mesa region potential so that the mesa regions do not form a floating structure. P-type base regions are distributed in the mesa regions, and the distributed p-type base regions (e.g., the limited regions in the mesa regions) are provided with an emitter structure. The trench MOSFET can lower the switching losses, reducing the total losses while suppressing the ON-state voltage drop of the trench IGBT as low as the ON-state voltage drop of the IEGT, and improving the turn-on characteristics thereof. The trench MOSFET also can reduce the capacitance between the gates and the emitter thereof, since the regions where the gate electrode faces the emitter structure are reduced. The trench MOSFET can have trench gate structures set at a narrow interval to relax the electric field localization to the bottom portions of the trenches and obtain a high breakdown voltage.

Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Abstract: A semiconductor component has a semiconductor body (100) having a basic doping and a first and second side, an inner region (103) arranged between the first and second sides, and an edge region (104) adjacent to the inner region in a lateral direction, at least one active component zone (12) which is arranged in the inner region (103) in the region of the first side (101) and is doped complementarily to the basic doping, and a channel stop zone (20), which is arranged in the edge region (104) in the region of the first side (101), is of the same conduction type as the basic doping and is doped more heavily than the basic doping, the doping concentration in the channel stop zone (20) decreasing continuously at least in sections in a lateral direction in the direction of the active component zone (12) at least over a distance (d1) of 10 ?m.

Abstract: An LDMOS transistor comprises source, channel and extended drain regions. The extended drain region comprises a plurality of islands that have a conductivity type that is opposite to the extended drain region. The islands have a depth less than a depth of the extended drain region.

Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.

Abstract: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

Abstract: A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drain portion having a second surface and a fourth surface, wherein the second and fourth surfaces are (A) parallel to each other and (B) not coplanar, and (iii) a channel region; (b) a gate dielectric layer; (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region; and (d) first second strain creating regions on the third and fourth surfaces, respectively, wherein the first and second strain creating regions comprise a strain creating material.

Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.

Abstract: The present invention provides a technique for accumulating minority carriers in the body region, that is, the intermediate region interposed between the top region and the deep region, and thus increasing the concentration of minority carriers in the intermediate region. A semiconductor device has a top region (34) of a second conductivity type, a deep region (26) of the second conductivity type, and an intermediate region (28) of a first conductivity type for isolating the top region and the deep region. The semiconductor device further has a trench gate (32) facing a portion of the intermediate region via an insulating layer (33). The portion facing the trench gate isolates the top region and the deep region. The trench gate extends along a longitudinal direction. The width of the trench gate is not uniform along the longitudinal direction; instead the width of the trench gate varies along the longitudinal direction.

Abstract: A wafer level image module includes a photo sensor for outputting an electrical signal upon receiving light, a lens set for focusing incident light onto the photo sensor, and an adjustment member disposed between the photo sensor and the lens set for controlling the distance between the photo sensor and the lens set to compensate the focus offset of the photo sensor for enabling the lens set to accurately focus the incident light onto the photo sensor in an in-focus manner so as to provide a high image quality.

Abstract: A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to be formed, the first site being disposed under the first gate insulating film in the active region; forming a gate electrode on each of the first gate insulating film and the second gate insulating film; and introducing an impurity of the first conductivity type into the first site and a second site where a second body region is to be formed, the second site being disposed under the second gate insulating film in the active region, to form the first body region and the second body region, respectively.

Abstract: To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region 111 and gate electrode 106, having N+ emitter region 104 and P+ emitter region 100, and controlling conduction between emitter and collector by voltage applied to gate electrode 106, the shape of contact opening 108 contacting emitter (N+ emitter region 104 and P+ emitter region 100) and emitter electrode is formed of curved lines at four corners. Hence, eliminating right-angle apex, hole current from the field region into the emitter electrode after switching off is prevented from concentrating at one point.

Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

Abstract: A trench IGBT is disclosed which includes a semiconductor substrate having formed therein a set of cell trenches formed centrally and a set of annular guard trenches concentrically surrounding the cell trenches. The cell trenches receive cell trench conductors via cell trench insulators for providing IGBT cells. The guard trenches receive guard trench conductors via guard trench insulators for enabling the IGBT to withstand higher voltages through mitigation of field concentrations. Capacitive coupling conductors overlie the guard trench conductors via a dielectric layer, each for capacitively coupling together two neighboring ones of the guard trench conductors. The capacitive coupling conductors are easily adjustably variable in shape, size and placement relative to the guard trench conductors for causing the individual guard trench conductors to possess potentials for an optimal contour of the depletion layer.

Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

Abstract: The power conversion apparatus uses the semiconductor device. Said semiconductor device includes a first group of power semiconductor elements at least one of which is electrically connected between a first potential and a third potential, a second group of power semiconductor elements at least one of which is electrically connected between a second potential and the third potential, and a third group of power semiconductor elements at least one of which is electrically connected between the first potential and the third potential. The second group is disposed between the first group and third group. Thereby, a low-loss semiconductor device having both inductance reducibility and heat generation balancing capability and also an electric power conversion apparatus using the same is provided.

Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Abstract: To provide a TEG capable of early stage feedback of testing contents and a method of testing using the TEG. TFTs for TEG are manufactured on a different substrate than actual panel TFTs by using from among processes for manufacturing actual panel TFTs, processes that may easily lead to dispersion in the TFT characteristics, and the minimum number of processing steps necessary for TFT manufacture. The number of processing steps is fewer than the number for the actual panel, and therefore it is possible to complete the TFTs for TEG quicker than those of the actual panel, and it becomes possible to feed back an evaluation of the TEG TFT characteristics to the actual panel manufacturing process at an early stage. Time and costs associated with manufacture of the actual panel can therefore be suppressed.

Abstract: A semiconductor device according to the invention has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.