Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.

Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

Abstract: A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material having a first concentration of an electrically active dopant therein. A second of the gate electrodes is formed of the first gate electrode material having less than the first concentration of the electrically active dopant therein, and formed at least partially as an alloy with a second gate electrode material. The semiconductor product may be formed with enhanced efficiency.

Abstract: The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.

Abstract: A semiconductor device provided with a semiconductor silicon substrate and gate wiring provided on the semiconductor silicon substrate via a gate oxide film, where the gate wiring has a gate electrode, a gate wiring upper structure provided in contact with the gate electrode, and a side wall spacer, the side wall spacer is comprised of one kind or two or more kinds of inorganic compound insulating layers, and at least one kind of the inorganic compound insulating layer is comprised of silicon oxy nitride with a nitrogen content ranging from 30 to 70%.

Abstract: A semiconductor device which includes a field effect transistor having a gate electrode on the upper side of a semiconductor substrate, with a gate insulation film therebetween, wherein at least the gate insulation film side of the gate electrode includes a film containing hafnium and silicon.

Abstract: Methods of forming semiconductor devices and the devices so formed include forming an oxidation barrier pattern to cover sidewalls of a metal-containing pattern. The metal-containing pattern is located on a gate polysilicon layer and includes a metal silicide pattern, a metal barrier pattern and a gate metal pattern which are sequentially stacked. An oxide layer is not formed between the metal barrier pattern and the gate polysilicon pattern. Furthermore, a metal silicide pattern located between the metal barrier pattern and the gate polysilicon pattern functions not only as an ohmic layer decreasing a contact resistance between the metal barrier pattern and the gate polysilicon pattern but also as an oxidation barrier to prevent a metal such as tungsten from being oxidized. Therefore, semiconductor devices have improved operational speed and/or reliability.