Abstract: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.

Abstract: A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. Wherein the first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second drain electrode of the JFET respectively.

Abstract: A power semiconductor device includes a semiconductor body. The semiconductor body includes a body region of a first conductivity type for forming therein a conductive channel of a second conductivity type; a gate electrode arranged next to the body region; and a floating electrode arranged between the gate electrode and the body region.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, an insulating layer laminated on the semiconductor substrate, a semiconductor layer laminated on the insulating layer, an annular deep trench having a depth reaching the insulating layer from the surface of the semiconductor layer, a source region formed on the surface layer of the semiconductor layer in a transistor forming region enclosed with the deep trench, a drain region formed on the surface layer of the semiconductor layer in the transistor forming region, an isolation region formed between the source region and the drain region for electrically isolating the source region and the drain region from each other, and a current path formed on the transistor forming region for guiding a current from the drain region to a position opposite to the source region in the vertical direction perpendicular to the surface of the semiconductor device.

Abstract: A trench-gate metal oxide semiconductor field-effect transistor includes a field plate that extends into a drift region of the transistor. The field plate is configured to deplete the drift region when the transistor is in the OFF-state. The field plate is formed in a field plate trench. The field plate trench may be formed using a self-aligned etch process. The conductive material of the field plate and gate of the transistor may be deposited in the same deposition process step. The conductive material may be etched thereafter to form the field plate and the gate in the same etch process step.

Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the semiconductor substrate. The highly doped active zone has a central aperture and a channel region that is generally centrally located within the central aperture. A terminal region of the second conductivity type is disposed in the voltage sustaining layer proximate the highly doped active zone. The terminal region has a central aperture with an opening dimension generally greater than an opening dimension of the central aperture of the highly doped zone. An extension region is disposed in the voltage sustaining region within the central aperture of the highly doped active zone.

Abstract: A trench-gate metal oxide semiconductor field-effect transistor (MOSFET) includes a field plate that extends into a drift region of the MOSFET. The field plate, which is electrically coupled to a source region, is configured to deplete the drift region when the MOSFET is in the OFF-state. The field plate extends from a top surface of a device substrate, which comprises an epitaxial layer formed on a silicon substrate. The field plate has a depth greater than 50% of a thickness of the epitaxial layer. For example, the field plate may extend to a full depth of the drift region. The field plate allows for relatively easy interconnection from the top surface of the device substrate, simplifying the fabrication process.

Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.

Abstract: The present invention is for weakening an electric field between a gate and a drain and preventing an electronic short between them. An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising forming a highly doped region in a semiconductor substrate through a first ion implantation process, forming a lightly doped region over the highly doped region through a second ion implantation process, forming a vertical transistor including the lightly doped region and a channel region having a pillar shape over the lightly doped region.

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Abstract: A charge compensation component having a drift path between two electrodes, an electrode and a counterelectrode, and methods for producing the same. The drift path has drift zones of a first conduction type and charge compensation zones of a complementary conduction type with respect to the first conduction type. A drift path layer doping comprising the volume integral of the doping locations of a horizontal drift path layer of the vertically extending drift path including the drift zone regions and charge compensation zone regions arranged in the drift path layer is greater in the vicinity of the electrodes than in the direction of the center of the drift path.

Abstract: Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

Abstract: Provided are a semiconductor device which can shorten reverse recovery time without increasing leakage current between the drain and the source, and a fabrication method for such semiconductor device.

Abstract: In a semiconductor element (20) including a field effect transistor (90), a schottky electrode (9a) and a plurality of bonding pads (12S, 12G), at least one of the plurality of bonding pads (12S, 12G) is disposed so as to be located above the schottky electrode (9a).

Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

Abstract: An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material.

Abstract: A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost.

Abstract: A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.

Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

Abstract: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Abstract: A power semiconductor device which includes a plurality of gate trenches and a perimeter trench intersecting the gate trenches.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: A semiconductor device is discloses that includes an n-type semiconductor substrate; an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately; p-type channel regions on the alternating conductivity type layer; and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions. The bottom of each trench is over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.

Abstract: A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner.

Abstract: A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.

Abstract: An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions.

Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Abstract: A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.

Abstract: A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.

Abstract: Power devices and associated methods of manufacturing are disclosed herein. In one embodiment, a power device includes a drain at a first end, a source and a gate at a second end, and a drift region between the drain at the first end and the source at the second end. The drift region includes a p-type dopant column juxtaposed with an n-type dopant column. The p-type dopant column and the n-type dopant column together have a width less than 12 microns.

Abstract: A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the N-epitaxial layer; a cap insulator disposed on top of the gate electrode; and an N+ doped spacer disposed along a sidewall of the source and a sidewall of the gate insulator. The source includes N+ dopants diffused from the spacer. A body contact region containing P-type dopants is formed from the N-epitaxial layer. The contact region touches one or more P-doped regions of the P-body layer and the source. Methods for manufacturing such a device are also disclosed. Embodiments of this invention may also be applied to P-channel devices.

Abstract: In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.

Abstract: A semiconductor device includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The semiconductor device also includes: a second trench that is formed in the semiconductor substrate with a width wider than the width of the first trench; and a terminal-embedded insulation layer that is formed so as to bury the second trench. The semiconductor device further includes: a third trench that is formed in the semiconductor substrate with a width wider than the width of the second trench; and a trench contact electrode that is formed so as to bury the third trench.

Abstract: An improved power device with a self-aligned suicide and a method for fabricating the device are disclosed. An example power device is a vertical power device that includes contacts formed on gate and body contact regions by an at least substantially self-aligned silicidation (e.g., salicide) process. The example device may also include one or more sidewall spacers that are each at least substantially aligned between edges of the gate region and the body contact region. The body contact region may also be implanted into the device in at least substantial self-alignment to the sidewall spacer. The method may also include an at least substantially self-aligned silicon etch.

Abstract: A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions.

Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.

Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Abstract: An ON-resistance of a semiconductor device including a vertical MOSFET whose source electrode, gate electrode, and drain electrode are formed on a single surface is reduced. A drift region which is lower in impurity concentration than a drain region is formed over the drain region. A gate trench and a drain contact trench are simultaneously formed in the drift region. A gate insulating film and a gate electrode are formed in the gate trench. A drain electrode is formed in the drain contact trench. A drain contact region which is higher in impurity concentration than the drift region is formed immediately under the drain contact trench.

Abstract: A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first conductive well region in a semiconductor substrate and a second conductive well region on or in the first conductive well region. A gate electrode is in a trench on a gate insulation layer, and the trench is in the second conductive region and the first conductive well region. A drain includes a drain insulation layer, a (polysilicon) shield layer, and drain plug. The drain insulation layer is in a trench in the second conductive region and the first conductive well region. The shield layer encloses the drain plug. A lower portion of the drain plug contacts the second conductive well region. A first conductive source region is at a side of the gate electrode.

Abstract: A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Abstract: Semiconductor component including a drift region and a drift control region. One embodiment provides a drift zone and a drift control zone. A drift control zone dielectric is arranged between the first drift zone and the drift control zone and has at least two sections arranged at a distance from one another in a current flow direction of the component. At least one separating structure is arranged between the drift zone and the drift control zone in the region of an interruption, defined by the at least two sections, of the drift control zone dielectric and has at least one PN junction.

Abstract: According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.

Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

Abstract: Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration.