Having Vertical Bulk Current Component Or Current Vertically Following Trench Gate (e.g., Vertical Power Dmos Transistor) (epo) Patents (Class 257/E29.257)
-
Publication number: 20110006364Abstract: According to one embodiment, a semiconductor device includes a first-conductivity-type semiconductor layer, a first and second-conductivity-type semiconductor pillar regions, a second and first-conductivity-type semiconductor regions, a first and second main electrodes, and a control electrode. Each of the first and second-conductivity-type pillar regions extends in a first direction and is alternately provided along a second direction generally perpendicular to the first direction. The second-conductivity-type semiconductor region is provided in a cell region and connected to the second-conductivity-type semiconductor pillar region. The first-conductivity-type semiconductor region is selectively provided in a surface of the second-conductivity-type semiconductor region. The first main electrode is connected to the first-conductivity-type semiconductor layer. The second main electrode is connected to the first and second-conductivity-type semiconductor region.Type: ApplicationFiled: July 7, 2010Publication date: January 13, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Syotaro ONO, Wataru SAITO, Munehisa YABUZAKI, Nana HATANO, Miho WATANABE
-
Publication number: 20110001187Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.Type: ApplicationFiled: August 26, 2010Publication date: January 6, 2011Inventor: François Hébert
-
Patent number: 7863675Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.Type: GrantFiled: March 22, 2008Date of Patent: January 4, 2011Assignee: Alpha & Omega Semiconductor, Ltd.Inventors: Anup Bhalla, Sik K. Lui
-
Publication number: 20100327342Abstract: In various embodiments, the invention relates to semiconductor structures, such as planar MOS structures, suitable as voltage clamp devices. Additional doped regions formed in the structures may improve over-voltage protection characteristics.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Inventors: Javier Salcedo, Alan Righter
-
Patent number: 7858477Abstract: A method for manufacturing a semiconductor device includes forming a bulb-type trench separated from a surrounding gate and forming a buried bit line in the bulb-type trench, thereby preventing electric short of a word line and the buried bit line. A semiconductor device includes a vertical pillar formed over a semiconductor substrate, a surrounding gate formed outside the vertical pillar, and a buried bit line separated from the surrounding gate.Type: GrantFiled: May 8, 2008Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventor: Han Nae Kim
-
Patent number: 7855415Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.Type: GrantFiled: February 15, 2008Date of Patent: December 21, 2010Assignee: Fairchild Semiconductor CorporationInventors: Ashok Challa, Jaegil Lee, Jinyoung Jung, Hocheol Jang
-
Publication number: 20100314681Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.Type: ApplicationFiled: June 11, 2009Publication date: December 16, 2010Applicant: FORCE MOS TECHNOLOGY CO. LTD.Inventor: Fu-Yuan Hsieh
-
Patent number: 7851852Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.Type: GrantFiled: October 7, 2009Date of Patent: December 14, 2010Assignee: Semiconductor Components Industries, L.L.C.Inventor: Prasad Venkatraman
-
Patent number: 7851316Abstract: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.Type: GrantFiled: January 29, 2009Date of Patent: December 14, 2010Assignee: Panasonic CorporationInventor: Hiroyuki Kamada
-
Publication number: 20100308399Abstract: A power semiconductor device includes: a first semiconductor layer of the first conduction type; second semiconductor layers of the first conduction type and third semiconductor layers of the second conduction type alternately provided transversely on the first semiconductor layer; fourth semiconductor layers of the second conduction type provided on the surfaces of the third semiconductor layers; fifth semiconductor layers of the first conduction type provided selectively on the surfaces of the fourth semiconductor layer; sixth semiconductor layers of the second conduction type and seventh semiconductor layers of the first conduction type alternately provided transversely on the second and the third semiconductor layers; a first main electrode electrically connected to the first semiconductor layer; an insulation film provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers; a control electrode provided on the fourth semiconductor layers, the sixth semiType: ApplicationFiled: March 22, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro ONO, Munehisa YABUZAKI, Nana HATANO, Miho WATANABE
-
Publication number: 20100308401Abstract: A semiconductor layer has a first layer of first conductive type, a second layer of second conductive type, and a third layer. The third layer has a first region of first conductive type, and a second region of second conductive type. A second electrode is in contact with each of the first and second regions. A trench is formed on the semiconductor layer at a surface opposite to its surface facing a first electrode. A gate electrode is embedded in the trench with a gate insulating film interposed therebetween. The gate electrode includes a first portion projecting into the first layer through the first region and the second layer, a second portion projecting into the first layer through the second region and the second layer. The second portion projects into the first layer deeper than a depth in which the first portion projects into the first layer.Type: ApplicationFiled: March 16, 2010Publication date: December 9, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Atsushi NARAZAKI
-
Patent number: 7847296Abstract: On a major surface of an n-type silicon carbide inclined substrate (2) is formed an n-type voltage-blocking layer (3) made of silicon carbide by means of epitaxial growth. On the n-type voltage-blocking layer (3) is formed a p-type silicon carbide region (4) rectangular when viewed from above. On the surface of the p-type silicon carbide region (4) is formed a p-type contact electrode (5). In the p-type silicon carbide region (4), the periphery of the p-type silicon carbide region (4) that is parallel with a (11-20) plane (14a) of the silicon carbide crystal, which is liable to cause avalanche breakdown, is located on the short side. In this manner, the dielectric strength of a silicon carbide semiconductor device can be improved.Type: GrantFiled: April 24, 2006Date of Patent: December 7, 2010Assignee: Mitsubishi Electric CorporationInventors: Hiroshi Sugimoto, Yoshinori Matsuno, Kenichi Ohtsuka, Noboru Mikami, Kenichi Kuroda
-
Publication number: 20100276751Abstract: An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.Type: ApplicationFiled: July 16, 2010Publication date: November 4, 2010Applicant: PTEK TECHNOLOGY CO., LTD.Inventors: MING TANG, SHIH-PING CHIAO
-
Patent number: 7825465Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.Type: GrantFiled: December 8, 2008Date of Patent: November 2, 2010Assignee: Fairchild Semiconductor CorporationInventors: James Pan, Qi Wang
-
Publication number: 20100264488Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trench gates sidewalls for reducing Qgd; a source dopant region disposed below a bottom surface of all trench gates for functioning as a current path for preventing a resistance increased caused by the body dopant regions.Type: ApplicationFiled: April 15, 2009Publication date: October 21, 2010Applicant: FORCE MOS TECHNOLOGY CO. LTD.Inventor: FU-YUAN HSIEH
-
Patent number: 7816210Abstract: A method is disclosed for producing a trench transistor which has at least two trenches with in each case a field electrode arranged therein and a gate electrode arranged therein. In the method, it is provided to implement the trenches with different trench widths and then to produce the field electrodes by filling up the trenches with an electrode material and subsequent cutting back of the electrode material. The different trench width leads to different etching rates during the cutting back of the electrode material, and thus to field electrodes which are spaced apart from a top edge of the trenches by different amounts. Following this, the gate electrodes are produced which, due to the different dimensions of the field electrodes, extend into the trenches to a different depth, resulting in different gate capacitances for the gate electrodes in the two trenches.Type: GrantFiled: August 30, 2006Date of Patent: October 19, 2010Assignee: Infineon Technologies AGInventors: Martin Poelzl, Franz Hirler
-
Patent number: 7816720Abstract: A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Gaussian-distribution from trenched source-body contact to channel region.Type: GrantFiled: July 8, 2009Date of Patent: October 19, 2010Assignee: Force Mos Technology Co., Ltd.Inventor: Fu-Yuan Hsieh
-
Publication number: 20100258862Abstract: A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.Type: ApplicationFiled: February 2, 2010Publication date: October 14, 2010Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
-
Publication number: 20100258853Abstract: A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost.Type: ApplicationFiled: June 2, 2009Publication date: October 14, 2010Inventors: Wei-Chieh Lin, Li-Cheng Lin
-
Publication number: 20100258864Abstract: In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Inventors: Izak Bencuya, Brian Sze-Ki Mo, Ashok Challa
-
Patent number: 7812409Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells wherein the layout of the trenched gate surrounding the transistor cells as closed cells having truncated corners or rounded corners. In an exemplary embodiment, the closed cells further includes a contact metal to contact a source and a body regions wherein the contact metal the trenched gate surrounding the transistor cell have a uniform space between them. In another exemplary embodiment, the semiconductor power device further includes a contact dopant region disposed below the contact metal to enhance an electrical contact between the metal contact and the source region and the body region, and the contact dopant region having substantially circular shape to achieve a uniform space between the contact dopant region and the trenched gate surrounding the closed cells.Type: GrantFiled: December 4, 2006Date of Patent: October 12, 2010Assignee: Force-MOS Technology Corp.Inventor: Fwu-Iuan Hshieh
-
Patent number: 7808040Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall and includes a mixture of a first semiconductor material, having a first lattice constant and a second semiconductor material with a second lattice constant differing from the first lattice constant, wherein a proportion of the second semiconductor material increases with increasing distance from the side wall.Type: GrantFiled: April 26, 2007Date of Patent: October 5, 2010Assignee: Infineon Technologies AGInventor: Christian Foerster
-
Patent number: 7808029Abstract: A mask structure and process for forming trenches in a silicon carbide or other wafer, and for implanting impurities into the walls of the trenches using the same mask where the mask includes a thin aluminum layer and a patterned hard photoresist mask. A thin LTO oxide may be placed between the metal layer and the hard photoresist mask.Type: GrantFiled: April 23, 2007Date of Patent: October 5, 2010Assignee: Siliconix Technology C.V.Inventors: Luigi Merlin, Giovanni Richieri, Rossano Carta
-
Patent number: 7804150Abstract: A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.Type: GrantFiled: June 29, 2006Date of Patent: September 28, 2010Assignee: Fairchild Semiconductor CorporationInventors: Chang-ki Jeon, Gary Dolny
-
Patent number: 7804131Abstract: A multi-chip module that includes a conductive element connecting at least two semiconductor devices, the conductive element including enhancements for improving the mechanical coupling between the conductive element and the molded housing of the MCM.Type: GrantFiled: April 30, 2007Date of Patent: September 28, 2010Assignee: International Rectifier CorporationInventors: Chuan Cheah, Kunzhong Hu
-
Publication number: 20100237847Abstract: A power supply circuit has a first MOSFET having a body region between the source and drain. The body region is connected so as to be at the same potential as the source. Application of a suitable potential to the gate causes the MOSFET to switch to a conductive on state. The power supply circuit also has signal generation circuitry, which generates a signal indicative of a conductive state of the first MOSFET. The signal generation circuitry generates a reference voltage of a predetermined potential difference from the source potential. The power supply circuit further comprises a second MOSFET having a body region connected so as to be at the same potential as the drain of the first MOSFET, and the second gate is connected to receive the reference voltage.Type: ApplicationFiled: August 3, 2007Publication date: September 23, 2010Applicant: ZETEX SEMICONDUCTORS PLCInventor: Adrian Finney
-
Publication number: 20100237409Abstract: A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.Type: ApplicationFiled: June 1, 2010Publication date: September 23, 2010Inventors: Prasad Venkatraman, Gordon M. Grivna, Francine Y. Robb, George Chang, Carroll Casteel
-
Patent number: 7800175Abstract: A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a second conductivity type provided in a surface portion of the semiconductor layer in a edge termination region outside a device region in which a main current path is formed in a vertical direction between the first main electrode and the second main electrode; and a plurality of buried semiconductor regions of the second conductivity type provided in the semiconductor layer in the edge termination region, spaced from the semiconductor regions, and spaced from each other. The buried semiconductor regions provided substantially at the same depth from the frontside of the semiconductor layer are numbered as first, second, . . .Type: GrantFiled: October 1, 2008Date of Patent: September 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Wataru Saito
-
Patent number: 7799636Abstract: A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall.Type: GrantFiled: September 25, 2009Date of Patent: September 21, 2010Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Becky Losee, Dean Probst
-
Patent number: 7800171Abstract: An integrated circuit including a semiconductor device is disclosed. One embodiment provides a load current component, having a multiplicity of trenches in a cell array. A sensor component is integrated into the cell array of the load current component and has a sensor cell array, the area of which is smaller than the area of the cell array of the load current component by a specific factor. The trenches forming the cell array of the sensor component correspond to the trenches of the cell array of the load current component, configured such that the trenches of the sensor component at the at least one side merge uniformly into the trenches of the cell array of the load current component without interruptions or disturbances of the trench geometry.Type: GrantFiled: October 11, 2007Date of Patent: September 21, 2010Assignee: Infineon Technologies Austria AGInventors: Mathias Von Borcke, Markus Zundel, Thorsten Meyer, Uwe Schmalzbauer
-
Publication number: 20100230746Abstract: A semiconductor device includes an epitaxial layer having a first conduction type, a base layer formed adjacent and on the epitaxial layer and having an opposite second conduction type to the first conduction type, a source layer formed selectively on the base layer and having the first conduction type, a trench which passes through the base layer and the source layer and which reaches the epitaxial layer, an insulation film formed along an interior wall of the trench, a control electrode formed within the trench via the insulation film, and a semiconductor region formed along the bottom part of the trench at the epitaxial layer and having the first conduction type.Type: ApplicationFiled: December 30, 2009Publication date: September 16, 2010Applicant: Sanken Electric Co., Ltd.Inventors: Hironori AOKI, Shuichi Kaneko
-
Publication number: 20100224932Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.Type: ApplicationFiled: January 26, 2007Publication date: September 9, 2010Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi
-
Publication number: 20100219468Abstract: Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling.Type: ApplicationFiled: November 25, 2009Publication date: September 2, 2010Applicant: MAXPOWER SEMICONDUCTOR INC.Inventors: Jun Zeng, Mohamed N. Darwish
-
Publication number: 20100219463Abstract: A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.Type: ApplicationFiled: February 3, 2010Publication date: September 2, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Hsiao Chin Tuan
-
Publication number: 20100219462Abstract: MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.Type: ApplicationFiled: November 25, 2009Publication date: September 2, 2010Applicant: MAXPOWER SEMICONDUCTOR INC.Inventors: Mohamed N. Darwish, Jun Zeng
-
Publication number: 20100219461Abstract: A structure that includes a rectifier further comprises a semiconductor region of a first conductivity type, and trenches that extend into the semiconductor region. A dielectric layer lines lower sidewalls of each trench but is discontinuous along a bottom of each trench. A silicon region of a second conductivity type extends along the bottom of each trench and forms a PN junction with the semiconductor region. A shield electrode in a bottom portion of each trench is in direct contact with the silicon region. A gate electrode extends over the shield electrode. An interconnect layer extends over the semiconductor region and is in electrical contact with the shield electrode. The interconnect layer further contacts mesa surfaces of the semiconductor region between adjacent trenches to form Schottky contacts therebetween.Type: ApplicationFiled: May 13, 2010Publication date: September 2, 2010Inventor: Mark Rinehimer
-
Publication number: 20100213506Abstract: A component arrangement including a MOS transistor having a field electrode is disclosed. One embodiment includes a gate electrode, a drift zone and a field electrode, arranged adjacent to the drift zone and dielectrically insulated from the drift zone by a dielectric layer a charging circuit, having a rectifier element connected between the gate electrode and the field electrode.Type: ApplicationFiled: May 4, 2010Publication date: August 26, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Armin Willmeroth, Franz Hirler
-
Patent number: 7781292Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.Type: GrantFiled: April 30, 2007Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Jeffrey Peter Gambino, Steven Howard Voldman, Michael Joseph Zierak
-
Patent number: 7781828Abstract: An integrated semiconductor with lateral thermal insulation is disclosed. In one embodiment, the chip has, on a common substrate, at least one power semiconductor circuit region and, laterally adjacent to the power semiconductor circuit region, at least one further temperature-sensitive semiconductor circuit region, interspaces being maintained between the circuit regions. At least one thermally insulating trench is provided at least in each interspace in each case between power semiconductor circuit region(s) and temperature-sensitive semiconductor circuit region(s), which at least one thermally insulating trench extends into the depth of the chip right into the substrate and in the longitudinal direction of the chip at least over a lateral side of the at least one power semiconductor circuit region and/or the temperature-sensitive semiconductor circuit region and is either unfilled or filled with a thermally insulating filling material.Type: GrantFiled: July 6, 2007Date of Patent: August 24, 2010Assignee: Infineon Technologies Austria AGInventor: Matthias Stecher
-
Publication number: 20100207198Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.Type: ApplicationFiled: May 3, 2010Publication date: August 19, 2010Applicant: GS GENERAL SEMICONDUCTOR LLCInventors: Richard A. Blanchard, Jean-Michel Guillot
-
Patent number: 7777273Abstract: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.Type: GrantFiled: May 15, 2007Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Ji-Young Kim
-
Patent number: 7772644Abstract: A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions.Type: GrantFiled: July 27, 2009Date of Patent: August 10, 2010Assignee: Texas Instruments IncorporatedInventors: Sameer Pendharkar, Binghua Hu
-
Patent number: 7772668Abstract: A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.Type: GrantFiled: December 26, 2007Date of Patent: August 10, 2010Assignee: Fairchild Semiconductor CorporationInventor: James Pan
-
Patent number: 7772621Abstract: A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions are arranged in a first plane on the drift portion, wherein the current spread portion surrounds at least partially the first portions. The semiconductor body further includes spaced apart body regions of a second conductivity type which are arranged on the current spread portion. Further, the doping concentration of the current spread portion is higher than the doping concentrations of the drift portion and of the first portions.Type: GrantFiled: September 20, 2007Date of Patent: August 10, 2010Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Rudolf Elpelt
-
Publication number: 20100193796Abstract: The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.Type: ApplicationFiled: December 24, 2009Publication date: August 5, 2010Applicant: ROHM CO., LTD.Inventor: Yuki Nakano
-
Publication number: 20100193864Abstract: A semiconductor device includes a plurality of first gate electrodes that are arranged above a semiconductor substrate in a first direction, and a plurality of second gate electrodes that are arranged above the semiconductor substrate in a second direction. The semiconductor device further includes a first gate lead-out electrode to which the first gate electrodes are connected, a second gate lead-out electrode to which the second gate electrodes are connected, and a third gate lead-out electrode to which the first gate lead-out electrode and the second gate lead-out electrode are connected. In the semiconductor device according to the present invention, a punched pattern is formed in the third gate lead-out electrode.Type: ApplicationFiled: January 14, 2010Publication date: August 5, 2010Inventor: Satoru TOKUDA
-
Publication number: 20100193863Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: April 14, 2010Publication date: August 5, 2010Applicants: RENESAS TECHNOLOGY CORP., HITACHI ULSI SYSTEMS, CO., LTD.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
-
Patent number: 7767529Abstract: A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.Type: GrantFiled: April 20, 2007Date of Patent: August 3, 2010Assignee: Semiconductor Componenets Industries, LLCInventors: Prasad Venkatraman, Gordon M. Grivna, Francine Y. Robb, George Chang, Carroll Casteel
-
Patent number: 7763893Abstract: A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.Type: GrantFiled: November 8, 2007Date of Patent: July 27, 2010Assignee: DENSO CorporationInventors: Eiichi Okuno, Toshio Sakakibara
-
Patent number: 7759733Abstract: A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode; and a second main electrode. A concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions is lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions.Type: GrantFiled: March 26, 2008Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Wataru Saito