Abstract: The manufacturing method includes the steps of: providing a semiconductor base of a first conduction type; forming a first epitaxial layer with a plurality of epitaxial pillars of therein on a first surface of the semiconductor base, wherein the epitaxial pillars have a conduction type opposite to the first epitaxial layer; forming a plurality of first shallow trenches and a plurality of second shallow trenches alternately on the epitaxial pillars and the first epitaxial layer, wherein the first shallow trench has a width greater than the width of the second shallow trench and the first shallow trench is extended downward to the epitaxial pillar; and forming a plurality of gate regions in the first shallow trenches respectively; forming a plurality of source regions on both sides of the first shallow trench; and forming a source metal conducting wire to connect the source regions.

Abstract: An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET.

Abstract: In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

Abstract: A semiconductor device includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode housed in the trench with a gate insulator intervening, a top surface of the gate electrode being lower than a top surface of the second diffused region, a first oxide film housed in the trench and formed over the gate electrode, a second oxide film housed in the trench and formed over the first oxide film, a third oxide film housed in the trench and formed over the second oxide film, and a source electrode formed over the third oxide film and electrically connecting to the first and second diffused regions.

Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer, a first semiconductor region provided on the semiconductor layer, a second semiconductor region, a first control electrode and a second control electrode. The first control electrode faces the first and second semiconductor regions through an insulating film in a trench, the trench piercing through the first semiconductor region, the trench having a bottom face at a position deeper than the first semiconductor region. The second control electrode extends to the bottom face of the trench and has a portion between the bottom face and the first control electrode. The semiconductor layer includes a first portion between an end of the first semiconductor region and an end of the second control electrode, a first conductive type carrier concentration in the first portion being lower than a first conductive type carrier concentration in other portions in the semiconductor layer.

Abstract: In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.

Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Abstract: A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Abstract: A device isolation layer is formed in a substrate to define spaced-apart linear active regions in the substrate. Buried gate patterns are formed in the substrate and extending along a first direction to cross the active regions. An etch stop layer and a first insulating layer are formed on the substrate. Bit line structures are formed on the first insulating layer and extending along a second direction transverse to the first direction to cross the active regions. A second insulating layer is formed on the bit line structures. Contact plugs are formed penetrating the second insulating layer, the first insulating layer, and the etch stop layer to contact one of the active regions between adjacent ones of the bit line structures.

Abstract: This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

Abstract: A trench semiconductor power device and a fabrication method. The fabrication method includes: eroding an n epitaxial layer on an n+ substrate to form multiple gate trenches, and implanting with dopants to form source regions and P type base regions, respectively; eroding an interlayer dielectric to form a trench plug; and eroding an aluminum copper alloy to form a metal pad layer and wires. The method forms the source regions and the base regions by directly implanting, does not need source region masks and base region masks, has a simple fabrication process, and improves the quality and reliability of the device.

Abstract: An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Abstract: A semiconductor device includes a semiconductor layer provided with a gate trench, a first conductivity type source region exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to aback surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and agate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

Abstract: A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.

Abstract: The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

Abstract: A MOSFET includes a semiconductor substrate having a top surface, a body region of a first conductivity type in the semiconductor substrate, and a double diffused drain (DDD) region having a top surface lower than a bottom surface of the body region. The DDD region is of a second conductivity type opposite the first conductivity type. The MOSFET further includes a gate oxide, and a gate electrode separated from the body region by the gate oxide. A portion of the gate oxide and a portion of the gate electrode are below the top surface of the body region.

Abstract: A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.

Abstract: A transistor, such as a vertical metal field effect transistor, can include a substrate including a ZnO-based material, and a structure disposed on a first side of the substrate comprising of AlGaN-based materials and electrodes disposed on the second side of the substrate. The transistor can also include a plurality of semiconductor layers and a dielectric layer disposed between the plurality of semiconductor layers and electrode materials.

Abstract: A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench.

Abstract: In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate.

Abstract: A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor.

Abstract: A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.

Abstract: A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode.

Abstract: According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

Abstract: A data storing device may include a substrate, transistors on the substrate that include gate line structures, and conductive isolation patterns defining active regions of the transistors. Each conductive isolation pattern includes at least one portion buried in the substrate and the conductive isolation patterns are electrically connected with each other.

Abstract: The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer.

Abstract: A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.

Abstract: A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar.

Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and bodies (252). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Abstract: A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 ?. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.

Abstract: A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film.

Abstract: A method for fabricating VDMOS devices includes providing a semiconductor substrate; forming a first N-type epitaxial layer on the semiconductor substrate; forming a hard mask layer with an opening on the first N-type epitaxial layer; etching the first N-type epitaxial layer along the opening until the semiconductor substrate is exposed, to form P-type barrier figures; forming a P-type barrier layer in the P-type barrier figures, the P-type barrier layer having a same thickness as that of the first N-type epitaxial layer; removing the hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate on the second N-type epitaxial layer; forming a source in the second N-type epitaxial layer on both side of the gate; and forming a drain on the back of the semiconductor substrate relative to the gate and the source.

Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.

Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide and trenched contacts is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.

Abstract: A method of producing a semiconductor device including a MOS transistor includes steps of forming a plurality of pillar semiconductor layers and forming a gate electrode formed around each of the pillar-shaped semiconductor layers. The method also includes steps of forming a source or drain region in an upper portion of each of the pillar-shaped semiconductor layers and forming a first silicide layer for connecting at least a part of a surface of a drain or source region formed in a planar semiconductor layer.

Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide and split gate electrodes is disclosed. The inventive structure can apply additional freedom for better optimization of device performance and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. Furthermore, the fabrication method can be implemented more reliably with lower cost.

Abstract: A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.

Abstract: When forming sophisticated semiconductor devices including high-k metal gate electrode structures and N-channel transistors, superior performance may be achieved by incorporating epitaxially grown semiconductor materials, for instance a strain-inducing silicon/carbon alloy in combination with an N-doped silicon material, which may provide an acceptable sheet resistivity.

Abstract: A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.

Abstract: According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

Abstract: One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The device includes a plurality of electrode films stacked along a first axis perpendicular to a major surface of a substrate, a plurality of semiconductor layers penetrating through the electrode films, and a memory film provided between the electrode films and the semiconductor layer. The method can include forming a first stacked body by alternately stacking a plurality of first films and second films. The method can include forming a support unit supporting the first films. The method can include forming a first hole and removing the second films via the first hole to form a second stacked body. The method can include forming a plurality of through holes penetrating through the first films. In addition, the method can include burying the memory film and the semiconductor layers in the through holes.

Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.

Abstract: Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.

Abstract: A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface.