Abstract: The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate. The method etches the semiconductor substrate to form a non-planar transistor structure having sidewalls. On a standard (100) <110> substrate the fin sidewalls have (110) surface plane if the fins are aligned or perpendicular with the <110> wafer notch. The method includes depositing a sacrificial liner along the sidewalls of the non-planar transistor structure. Further, a confining material is deposited overlying the semiconductor substrate and adjacent the sacrificial liner. The method includes removing at least a portion of the sacrificial liner and forming a void between the sidewalls of the non-planar transistor structure and the confining material. A cladding layer is epitaxially grown in the void. Since the sidewall growth is limited by the confining material, a cladding layer of uniform thickness is enabled on fins with (110) sidewall and (100) top surface.

Abstract: A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.

Abstract: A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode.

Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced.

Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor includes: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.

Abstract: Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

Abstract: A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.

Abstract: Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

Abstract: A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 ?m.

Abstract: A semiconductor device includes a trench region extending into a drift zone of a semiconductor body from a surface. The semiconductor device further includes a dielectric structure extending along a lateral side of the trench region, wherein a part of the dielectric structure is a charged insulating structure. The semiconductor device further includes a gate electrode in the trench region and a body region of a conductivity type other than the conductivity type of the drift zone. The charged insulating structure adjoins each one of the drift zone, the body region and the dielectric structure and further adjoins or is arranged below a bottom side of a gate dielectric of the dielectric structure.

Abstract: Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.

Abstract: A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.

Abstract: A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length LD of the device. A surface doped region is formed adjacent to the gate.

Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.

Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.

Abstract: A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate.

Abstract: A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.

Abstract: A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.

Abstract: A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed.

Abstract: A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween.

Abstract: A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.

Abstract: A semiconductor power device with trenched floating gates having thick bottom oxide as termination is disclosed. The gate charge is reduced by forming a HDP oxide layer padded by a thermal oxide layer on trench bottom and a top surface of mesa areas between adjacent trenched gates. Therefore, only three masks are needed to achieve the device structure.

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

Abstract: A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Abstract: A semiconductor device includes a semiconductor substrate having a groove and an active region adjacent to the groove; a buried gate electrode in the groove; and a capacitor contact including a first portion and a second portion over the first portion. The first portion is greater in horizontal dimension than the second portion. The first portion has a bottom surface that is in contact with an upper surface of the active region.

Abstract: Disclosed herein are a semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a base region formed on an upper region of an inside of the semiconductor substrate, at least one gate electrode that penetrates through the base region and has an inverted triangular shape, a gate insulating film formed to enclose an upper portion of the semiconductor substrate and the gate electrode, an inter-layer insulating film formed on an upper portion of the gate electrode and the gate insulating film, an emitter region formed inside the base region and on both sides of the gate electrode, an emitter metal layer formed on an upper portion of the base region and inter-layer insulating film, and a buffer region formed to enclose a lower portion of the gate electrode and to be spaced apart from the base region.

Abstract: A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.

Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.

Abstract: Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface.

Abstract: The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.

Abstract: An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET.

Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.

Abstract: A semiconductor device may include, but is not limited to: a semiconductor structure extending upwardly; a first insulating film covering at least a side surface of the semiconductor structure; a gate electrode extending upwardly, the gate electrode being adjacent to the first insulating film; and an insulating structure extending upwardly, the insulating structure being adjacent to the gate electrode.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.

Abstract: A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

Abstract: In one embodiment, a semiconductor device is formed to include a gate structure extending into a first portion of a semiconductor material that is underlying a first region of semiconductor material. The gate structure separates a portion of the first region into at least a first current carrying electrode region and a second current carrying electrode region. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies a gate conductor of the gate structure. The gate structure also includes a shield conductor overlying the gate conductor and having a shield insulator positioned between the shield conductor and the gate conductor. The shield insulator also having a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.

Abstract: A method for forming a semiconductor device includes forming a sealing insulation film over a semiconductor substrate including a device isolation film and an active region, forming a bit line contact plug that protrudes from an upper part of the sealing insulation film and is coupled to the active region, forming a spacer over a sidewall of the protruded bit line contact plug, and forming a bit line coupled to an upper part of the bit line contact plug.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region.

Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.

Abstract: A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.

Abstract: A MOS diode includes a substrate with a mesa, a P-type semiconductor region with etched shallow trench surrounding the mesa, that cause an increasing metal contact area to reduce Vf value, a gate oxide layer arranged on the mesa, a polysilicon layer arranged on the gate oxide layer, and a shielding oxide layer arranged on the polysilicon layer. The termination structure includes a trench, an oxide layer arranged at least within the trench, at least one sidewall polysilicon layer arranged on the oxide layer within the trench. In the MOS diode, the shielding oxide layer is thicker than the gate oxide layer to prevent leaking current. The oxide layer and the sidewall polysilicon layer can enhance the reverse voltage tolerance of the MOS diode. A metal layer covers the polysilicon region, shielding oxide layer, semiconductor regions with etched shallow trench, termination region and some parts outside the termination region.