Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

Abstract: Provided are a phase-change memory device using insulating nanoparticles, a flexible phase-change memory device and a method for manufacturing the same. The phase-change memory device includes an electrode, and a phase-change layer in which a phase change occurs depending on heat generated from the electrode, wherein insulating nanoparticles formed from a self-assembled block copolymer are provided between the electrode and the phase-change layer undergoing crystallization and amorphization.

Abstract: A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage.

Abstract: A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.

Abstract: A memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer.

Abstract: Various embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to one or more memory elements, to store information. The electrode may comprise a number of metals, where a first one of the metals has a Gibbs free energy for oxide formation lower than the Gibbs free energy of oxidation of a second one of the metals.

Abstract: A memory element includes: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer containing one or more of metallic elements, and the ion source layer being provided on the second electrode side. The ion source layer includes a first ion source layer and a second ion source layer, the first ion source layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and being provided on the resistance change layer side, and the second ion source layer containing the chalcogen element with a content different from a content in the first ion source layer and being provided on the second electrode side.

Abstract: In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.

Abstract: Provided is an electronic component that includes a first bi-layer stack including a first silicon oxide layer and a first silicon nitride layer, a second bi-layer stack including a second silicon oxide layer and a second silicon nitride layer, and a convertible structure which is convertible between at least two states having different electrical properties, where the convertible structure is arranged between the first bi-layer stack and the second bi-layer stack.

Abstract: A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.

Abstract: A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.

Abstract: A phase change memory cell includes a first circuit and a second circuit. The first circuit comprises a first electrode, a carbon nanotube layer and a second electrode electrically connected in series. The first circuit is adapted to write data into the phase change memory cell or reset the phase change memory cell. The second circuit comprises a third electrode, a phase change layer and a fourth electrode electrically connected in series, at least part of the phase change layer is overlapped with the carbon nanotube layer. The second circuit is adapted to read data from the phase change memory cell or reset the phase change memory cell.

Abstract: A phase-change random access memory device includes a semiconductor substrate, an interlayer dielectric layer formed over the semiconductor substrate and having contact holes defined therein, metal contacts formed in the contact holes, an ohmic contact layer formed over the metal contacts and having recesses defined therein, and switching elements formed over the recesses of the ohmic contact layer.

Abstract: A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials.

Abstract: A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.

Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.

Abstract: The present invention provides a variable resistive element that can perform a stable switching operation at low voltage and low current, and also provides a low-power consumption large-capacity non-volatile semiconductor memory device including the variable resistive element. The non-volatile semiconductor memory device is a device using a variable resistive element, which includes a variable resistor between a first electrode and a second electrode, for storing information, wherein an oxygen concentration of a hafnium oxide (HfOx) film or a zirconium oxide (ZrOx) film constituting the variable resistor is optimized such that a stoichiometric composition ratio x of oxygen to Hf or Zr falls within a range of 1.7?x?1.97.

Abstract: A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure.

Abstract: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.

Abstract: A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed.

Abstract: Provided is a resistance change type nonvolatile semiconductor storage device including a diode capable of passing therethrough a sufficient current to a resistance changing operation even when the memory cell is miniaturized. A nonvolatile semiconductor storage device has first wires extending in X direction, second wires extending in Y direction, and memory cells disposed at intersection points of the first wires and the second wires. The memory cell includes a diode disposed over the first wire, and coupled to the first wire at one end, and a resistance change part disposed over the diode, and series-coupled to the diode at one end, and coupled to the second wire at the other end, and storing information through changes in resistance value. The diode includes a first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer extending into the inside of the first semiconductor layer.

Abstract: A controlled switching memristor includes a first electrode, a second electrode, and a switching layer positioned between the first electrode and the second electrode. The switching layer includes a material to switch between an ON state and an OFF state, in which at least one of the first electrode, the second electrode, and the switching layer is to generate a permanent field within the memristor to enable a speed and an energy of switching from the ON state to the OFF state to be substantially symmetric to a speed and energy of switching from the OFF state to the ON state.

Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.

Abstract: A memory element includes: a memory layer disposed between a first electrode and a second electrode. The memory layer includes: an ion source layer containing one or more metallic elements, and one or more chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se); and a resistance change layer disposed between the ion source layer and the first electrode, the resistance change layer including a layer which includes tellurium and nitrogen (N) and is in contact with the ion source layer.

Abstract: An electronic device (100), the electronic device (100) comprises a substrate (101), a first electrode (102) formed at least partially on the substrate (101), a second electrode (103) formed at least partially on the substrate (101), a convertible structure (104) connected between the first electrode (102) and the second electrode (103), and a spacer element (105) connected between the first electrode (102) and the second electrode (103) and adapted for spacing the convertible structure (104) with regard to a surface of the substrate (101).

Abstract: A method of changing a state of a memristor having a first intermediate layer, a second intermediate layer, and a third intermediate layer positioned between a first electrode and a second electrode includes applying a first pulse having a first bias voltage across the memristor, wherein the first pulse causes mobile species to flow in a first direction within the memristor and collect in the first intermediate layer thereby causing the memristor to enter into an intermediate state and applying a second pulse having a second bias voltage across the memristor, in which the second pulse causes the mobile species from the first intermediate layer to flow in a second direction within the memristor and collect in the third intermediate layer, wherein the flow of the mobile species in the second direction causes the memristor to enter into a fully changed state.

Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

Abstract: A method of manufacturing a PCRAM device includes forming a switching device in a contact hole of a first interlayer insulating layer, forming a second interlayer insulating layer having an opening exposing the switching device, forming a lower electrode pattern along a sidewall of the second interlayer insulating layer to be coupled to the switching device, forming an insulating layer to be buried within the lower electrode pattern, forming a lower electrode by removing an exposed surface of the lower electrode pattern by a set height, wherein a height of a sidewall of the lower electrode is lower than that of the second interlayer insulating layer, forming a phase-change layer filing a hole of the second interlayer insulating layer from which the exposed surface of the lower electrode pattern is removed, and forming an upper electrode on the phase-change layer and a portion of the second interlayer insulating layer.

Abstract: A phase change memory device includes a vertically-stacked capacitor structure having large capacitance and small area. The phase change memory device includes a phase change memory structure, and the vertically-stacked capacitor structure electrically connected to the phase change memory structure and comprising a first capacitor and a second capacitor that are stacked and electrically connected in parallel to each other.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Abstract: An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode.

Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

Abstract: A method for forming a non-volatile memory device includes forming a dielectric material overlying a semiconductor substrate, forming a first wiring structure overlying the first dielectric material, depositing an undoped amorphous silicon layer, depositing an aluminum layer over the amorphous silicon layer at a temperature of about 450 Degrees Celsius or lower, annealing the amorphous silicon and aluminum at a temperature of about 450 Degrees Celsius or lower to form a p+ polycrystalline layer, depositing a resistive switching material comprising an amorphous silicon material overlying the polycrystalline silicon material, forming a second wiring structure comprising a metal material overlying the resistive switching material.

Abstract: A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer.

Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.

Abstract: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: According to an example embodiment, a variable resistance memory device includes a lower electrode that includes a spacer-shaped first sub lower electrode and a second sub lower electrode covering a curved sidewall of the first sub lower electrode. The second sub lower electrode extends upward to protrude above the top of the first sub lower electrode. The lower electrode includes an upward-tapered shape.

Abstract: A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.

Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.

Abstract: Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.

Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.

Abstract: A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.

Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.

Abstract: Resistance variable memory cells and methods are described herein. One or more methods of forming a resistance variable memory cell include forming a silicide material on a terminal of a select device associated with the resistance variable memory cell, forming a modified region of the silicide material by modifying a resistivity of a region of the silicide material, forming a conductive element on at least a portion of the modified region, and forming a resistance variable material on the conductive element.

Abstract: The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell.

Abstract: A substrate having buried address lines and a first dielectric layer is provided. A conductive electrode is formed in the first conductive layer. A top portion of the conductive electrode is exposed. A second dielectric layer is deposited on surface of the exposed top portion. The second dielectric layer defines a recess around the top portion. A third dielectric layer is deposited over the second dielectric layer. A portion of the third dielectric layer and a portion of the second dielectric layer are removed, thereby exposing a top surface of the top portion of the conductive electrode. The top portion of the conductive electrode is salicidized to form a heating stem. The remaining third dielectric layer is selectively removed from the recess. A phase-change material layer covers the heating stem and the second dielectric layer. The phase-change material layer is etched, thereby forming a phase-change storage cap.

Abstract: This disclosure is directed to a phase change semiconductor device and a manufacturing method thereof, comprising: forming an insulating layer on a substrate and a metal layer on the insulating layer; forming a via hole penetrating from the metal layer to the insulating layer; forming a phase change material layer on the metal layer and the via hole to at least fill up the via hole; and performing a planarization process, wherein after forming the metal layer and before forming the via hole, or after forming the via hole and before forming the phase change material layer, or after forming the phase change material layer and before the planarization process, subjecting the metal layer to an annealing treatment to form a metallic compound layer at an interface between the metal layer and the insulating layer. Adhesion between the phase change material layer and the insulating layer can be improved.