Abstract: An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.

Abstract: A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions; a lower electrode formed in each of the phase change cell regions on the semiconductor substrate; an insulation layer formed on the semiconductor substrate to cover the lower electrode and defined with a contact hole which exposes the lower electrode; a heater formed in the contact hole; a conductive pattern formed on the insulation layer to be spaced apart from the heater; a phase change layer formed on the heater, the conductive pattern, and portions of the insulation layer between the heater and the conductive pattern; and an upper electrode formed on the phase change layer. This phase change memory device allows the phase change layer to be stably formed and prevents the phase change layer from lifting.

Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on and in contact with the second electrode layer.

Abstract: A phase change memory device includes a switching device and a storage node connected to the switching device. The storage node includes a bottom stack, a phase change layer disposed on the bottom stack and a top stack disposed on the phase change layer. The phase change layer includes a unit for increasing a path of current flowing through the phase change layer and reducing a volume of a phase change memory region. The area of a surface of the unit disposed opposite to the bottom stack is greater than or equal to the area of a surface of the bottom stack in contact with the phase change layer.

Abstract: A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.

Abstract: A phase change memory device includes a plurality of word lines, a plurality of bit lines disposed to be crossed with the plurality of word lines, switching devices disposed at intersections of the plurality of word lines and the plurality of bit lines, heating electrodes connected to the switching devices respectively, heat absorbing layers disposed between adjacent heating electrodes, and phase change layers formed on the heating electrodes and the heat absorbing layers and extended in the same direction of the bit line.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.

Abstract: A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.

Abstract: Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

Abstract: A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer.

Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.

Abstract: Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode.

Abstract: The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa.

Abstract: Disclosed are a resistive random-access memory (ReRAM) based on resistive switching using a resistance-switchable conductive filler and a method for preparing the same. When a resistance-switchable conductive filler prepared by coating a conductive filler with a material whose resistance is changeable is mixed with a dielectric material, the dielectric material is given the resistive switching characteristics without losing its inherent properties. Therefore, various resistance-switchable materials having various properties can be prepared by mixing the resistance-switchable conductive filler with different dielectric materials. The resulting resistance-switchable material shows resistive switching characteristics comparable to those of the existing metal oxide film-based resistance-switchable materials. Accordingly, a ReRAM device having the inherent properties of a dielectric material can be prepared using the resistance-switchable conductive filler.

Abstract: A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.

Abstract: There are provided a memory element and a memory device with improved writing and erasing characteristics during operations at a low voltage and a low current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer, and the barrier layer containing a transition metal or a nitride thereof.

Abstract: According to one embodiment, a memory cell includes a resistance change layer, an upper electrode layer, a lower electrode layer, a diode layer, a first oxide film, and a second oxide film. The upper electrode layer is arranged above the resistance change layer. The lower electrode layer is arranged below the resistance change layer. The diode layer is arranged above the upper electrode layer or below the lower electrode layer. The first oxide film exists on a side wall of at least one electrode layer of the upper electrode layer or the lower electrode layer. The second oxide film exists on a side wall of the diode layer. The film thickness of the first oxide film is thicker than a film thickness of the second oxide film.

Abstract: On example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and a device layer. The device layer comprises a first dielectric material, between the first and second conductive electrodes, that includes an effective device layer, a first barrier layer near a first interface between the first conductive electrode and the device layer, and a second barrier layer near a second interface between the second conductive electrode and the device layer. A second example of the present invention is an integrated circuit that incorporates nanoscale electronic devices of the first example.

Abstract: A phase change memory device includes a mold oxide layer on a substrate, a lower electrode on the mold oxide layer and connected to the substrate, a blocking structure covering a part of the lower electrode and including an etch-stop layer and a blocking structure insulating layer, and a phase change layer covering a remaining part of the lower electrode not covered by the blocking structure, The etch-stop layer includes a material having a higher etching selectivity than that of the lower electrode.

Abstract: A phase change material layer includes a Ge-M-Te (GMT) ternary phase change material, where Ge is germanium, M is a heavy metal, and Te is tellurium. The GMT ternary phase change material may also include a dopant.

Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100?x composition. According to another embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between chalcogenide glass layers and further having a silver layer above at least one of said chalcogenide glass layers and a conductive adhesion layer above said silver layer.

Abstract: A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode.

Abstract: A method of manufacturing a memory device is provided. The method includes forming an electrode over a substrate. The method also includes forming an opening in the electrode to provide a tapered electrode contact surface proximate the opening. The method further includes forming a phase change feature over the electrode and on the tapered electrode contact surface.

Abstract: A thin film storage device includes a first electrode (3), a first variable resistance thin film (2), and a second electrode (1). The first electrode (3) is formed over a surface of a substrate (4). The first variable resistance thin film (2) is formed over a surface of the first electrode (3). The second electrode (1) is formed over a surface of the first variable resistance thin film (2). The first variable resistance thin film (2) comprises a material whose resistance in a bulk state changes in accordance with at least one of a lattice strain and a change of charge-order.

Abstract: A reversible resistance-switching metal-insulator-metal (MIM) stack is provided which can be set to a low resistance state with a first polarity signal and reset to a higher resistance state with a second polarity signal. The first polarity signal is opposite in polarity than the second polarity signal. In one approach, the MIM stack includes a carbon-based reversible resistivity switching material such as a carbon nanotube material. The MIM stack can further include one or more additional reversible resistivity switching materials such as metal oxide above and/or below the carbon-based reversible resistivity switching material. In another approach, a metal oxide layer is between separate layers of carbon-based reversible resistivity switching material.

Abstract: In a variable resistance memory device and a method of manufacturing the variable resistance memory device, the generation of a seam, or void, is avoided in the device that, if present, may otherwise reduce the reliability of the resulting device.

Abstract: A nanoscale switching device is constructed such that an electroforming process is not needed to condition the device for normal switching operations. The switching device has an active region disposed between two electrodes. The active region has at least one switching layer formed of a switching material capable of transporting dopants under an electric field, and at least one conductive layer formed of a dopant source material containing dopants that can drift into the switching layer under an electric field. The switching layer has a thickness about 6 nm or less.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.

Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.

Abstract: A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a substrate (10), lower-layer electrode wires (15) provided on the substrate (11), an interlayer insulating layer (16) which is disposed on the substrate (11) including the lower-layer electrode wires (15) and is provided with contact holes at locations respectively opposite to the lower-layer electrode wires (15), resistance variable layers (18) which are respectively connected to the lower-layer electrode wires (15); and non-ohmic devices (20) which are respectively provided on the resistance variable layers (18) such that the non-ohmic devices are respectively connected to the resistance variable layers (18). The non-ohmic devices (20) each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer.

Abstract: A method of forming a semiconductor memory device comprises a step of forming an electrode pattern extending in a first direction on a substrate, a step of forming a pair of mask patterns on the electrode pattern, the mask patterns extending a second direction perpendicular to the first direction, a step of partially etching the electrode pattern using the pair of mask patterns as etch masks to form a first recessed region in the electrode pattern, a step of forming a pair of sidewall spacers on either inner sidewalls of the first recessed region, a step of etching the electrode pattern of the first recessed region using the pair of sidewall spacers as etch masks to form a heating electrode contacting the pair of sidewall spacers, and a step of forming a variable resistive pattern on the heating electrode.

Abstract: A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, and forming a reversible resistance-switching element coupled to the steering element. The reversible resistance-switching element includes one or more of TiOx, Ta2O5, Nb2O5, Al2O3, HfO2, and V2O5, and the reversible resistance switching element is formed without being etched. Numerous other aspects are provided.

Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

Abstract: A memory device having at least one layer of oxygen ion implanted conductive metal oxide (CMO) is disclosed. The oxygen ion implanted CMO includes mobile oxygen ions. The oxygen ion implanted CMO can be annealed and the annealing can optionally occur in an ambient. An insulating metal oxide (IMO) layer is in direct contact with the oxygenated CMO layer and is electrically in series with the oxygenated CMO layer. A two-terminal memory element is formed by the IMO and CMO layers. The oxygenated CMO layer includes additional mobile oxygen ions operative to improve data retention and cycling of the two-terminal memory element. As deposited, the CMO layer can lose mobile oxygen ions during the fabrication process and the ion implantation serves to increase a quantity of mobile oxygen ions in the CMO layer.

Abstract: Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film.

Abstract: Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials.

Abstract: A typical switching device according to the present invention comprises first insulating layer 1003 having an opening and made of a material for preventing metal ions from being diffused, first electrode 104 disposed in the opening and including a material capable of supplying the metal ions, ion conduction layer 105 disposed in contact with an upper surface of the first electrode 104 and capable of conducting the metal ions, and second electrode 106 disposed in contact with an upper surface of the ion conduction layer 105 and including a region made of a material incapable of the metal ions. A voltage is applied between the first electrode 104 and the second electrode 106 for controlling a conduction state between the first electrode 104 and the second electrode 106.

Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.

Abstract: Disclosed herein is a storage element including: a first electrode; a second electrode formed in a position opposed to the first electrode; and a variable-resistance layer formed so as to be interposed between the first electrode and the second electrode. The first electrode is a tubular object, and is formed so as to be thicker on an opposite side from the variable-resistance layer than on a side of the variable-resistance layer.

Abstract: A phase change memory device having multiple metal silicide layers which enhances the current driving capability of switching elements and a method of manufacturing the same are presented. The device also includes switching elements, heaters, stack patterns, top electrodes, bit lines, word line contacts and word lines. The bottom of the switching elements are in electrical contact with the lower metal silicide layer and with an active area of silicon substrate. An upper metal silicide layer is interfaced between the top of the switching elements and the heaters. The stack patterns include phase change layers and top electrodes and are between the heaters and the top electrodes are in electrical contact with the top electrodes. The bit lines contact with the top electrode contacts. The word line contacts to the lower metal silicide film.

Abstract: An integrated circuit with an embedded memory comprises a substrate and a plurality of conductor layers arranged for interconnecting components of the integrated circuit. An intermediate layer in the plurality of conductor layers includes a first electrode having a top surface, a second electrode having a top surface, an insulating member between the first electrode and the second electrode. A bridge overlies the intermediate layer between the first and second electrodes across the insulating member, wherein the bridge comprises a programmable resistive memory material, such as a phase change material. A conductor in at least one layer in the plurality of conductor layers over said intermediate layer is connected to said bridge.

Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.

Abstract: Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include self-aligned side wall memory members comprising an active programmable resistive material. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process used to manufacture the memory cell, and more preferably F being equal to a minimum feature size. Arrays of memory cells described herein include memory cells arranged in a cross point array, the array having a plurality of word lines and source lines arranged in parallel in a first direction and having a plurality of bit lines arranged in parallel in a second direction perpendicular to the first direction.

Abstract: In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (MIM) stack, the MIM stack including (a) a first conductive carbon layer; (b) a low-hydrogen, silicon-containing carbon layer above the first conductive carbon layer; and (c) a second conductive carbon layer above the low-hydrogen, silicon-containing carbon layer; and (2) forming a steering element coupled to the MIM stack. Numerous other aspects are provided.

Abstract: A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by InXSbYTeZ or, alternatively, with substitutions of silicon and/or tin for indium, arsenic and/or bismuth for antimony, and selenium for tellurium; and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer.