Abstract: An automatic interface identification technique for an apparatus capable of supporting both USB and PS/2 interfaces comprises connecting a detector to first and second ports provided for the apparatus connected to a host computer through a USB or PS/2 interface. The detector has an interface detect function including a logic confirming mechanism and an interface identifying algorithm and a mode select function receiving first and second control signals such that the logic confirming mechanism is connected to the first and second ports by the interface detect function to detect the logic states of the first and second ports in association with the interface identifying algorithm to thereby correctly identify a USB or PS/2 interface is connected and to further determine USB or PS/2 mechanism in response to signal transmissions.

Abstract: In a level shift circuit, for example, when an input signal IN changes from the L level to the H level, an N-type signal input transistor is made conducting and current flows in the N-type transistor. Accordingly, a first current mirror circuit amplifies the current flowing in the N-type transistor by predetermined number of times, increases the current driving capability for an inverted output node, and changes the inverted output node quickly to the L level. With the change to the L level of the inverted output node, an output node changes to the H level, a P-type transistor (first current interrupting circuit) is made non-conducting by the change, and the current fed from the first current mirror circuit is interrupted. Therefore, even when the power source voltage for the input signal and the inverted input signal is lowered, the operation is performed at high speed.

Abstract: In an I/O buffer circuit for solving problems occurred due to I/O voltage level difference, the I/O buffer circuit includes a logical controller for generating an enable signal and data according to an internal core voltage (VDDC); a level converter for converting the internal core voltage (VDDC) into an output voltage level when the internal core voltage (VDDC), an input signal voltage (VDDI) and an output signal voltage (VDDO) are different; and a pull-up unit for permitting a voltage level in specific level order through the level converter when a power voltage level in a semiconductor chip and a voltage level of an input signal are different from each other.

Abstract: A signal transmission system is provided which can accurately recognize data even if two signals are superimposed on each other on the same signal line. The potential of a read signal indicating read data is designated (a), and the potential of a write signal indicating write data is designated (b). Consequently, the potential of a signal where the read signal and the write signal are superimposed (that is, the superimposed signal) is designated as (c). As a result, the value of write data can be accurately recognized from the superimposed signal, using a reference potential of 1.75V. On the other hand, the value of read data can be accurately recognized from the superimposed signal, using the reference potential of 2.25V when the write data is “H”, or 1.25V when the write data is “L”.

Abstract: Recent efforts are underway to develop LSI circuits that operate at power supply voltages of 1-V or lower. It is a desire that this low core voltage circuits interface to 3.3-V I/O supply. A charge pump level converter for dual power supply application is proposed using low power and high speed interface to higher I/O supply. This circuit does not consume DC power it is suitable for low power and high speed interface and can be implemented using complementary metal-oxide-semiconductor (CMOS) fabrication processes.

Abstract: A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage generator that produces a reference voltage corresponding to the value of the internal voltage, a comparator having opposite polarity inputs for producing an amplified output control signal, and a pull-up device operating from the external voltage that receives the control signal from the comparator to produce the internal voltage as an input. A dual source follower is located between the reference voltage generator and comparator and has two sections having cross-coupled inputs which respectively receive the internal reference voltage and the internal voltage to produce output voltages moving in opposite directions, each of which is applied to one input of the comparator, thereby translating the difference between Vintref and Vint to a level in a range that can be better amplified by the comparator.

Abstract: When a circuit that is likely to cause noise is enabled, a control circuit turns on a switch so that an inverter will be formed by one P-channel MOSFET and two parallel-connected N-channel MOSFETs. This helps enhance the current capacity of the inverter on its N-channel MOSFET side, and thereby lower the threshold voltage of the inverter.

Abstract: A level shift circuit that reduces PMOS to NMOS device contention whole decreasing output rise delays. The invention includes a device, comprising: a level shift circuit for shifting a signal at a first voltage at an input node to a second voltage at an output node; a boost circuit, driven by the second voltage, for decreasing a transition time of the signal between the first and second voltage; and a trigger circuit, coupled to an input of the boost circuit, for turning off the boost circuit when the signal at the output node reaches a predetermined voltage level.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: A bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line includes: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.

Abstract: A scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector section, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array are provided. In a scan flip-flop circuit, an output terminal is provided in addition to an output terminal. One of the output terminals is used for a logic circuit and the other output terminal is used for a scan flip-flop circuit of the next stage. At the output terminal for the scan flip-flop circuit 1 of the next stage, an output is fixed in a normal operation, thereby achieving higher operation speed in the normal operation and lower power consumption. A selector section can employ a relatively simple OR-AND-INVERTER structure.

Abstract: A circuit for a transceiver output port of a local area networking device is provided and includes a first and a second current source coupled to the ground, a first and a second resistor coupled to the supply voltage, wherein the resistances of the first and the second resistors each are equal to half that of the equivalent resistance of the UTP cable for the purpose of impedance matching, and a third current source and a fourth current source coupled to the UTP cable for providing additional current for the circuit. The magnitude of the differential signal output from the circuit can thus sustain in a predetermined range even if the magnitude of the supply voltage is lower than the minimum magnitude required by the conventional circuit.

Abstract: Compositions of biomolecules such as nucleic acids that form molten salts are provided. These compositions molten compositions that have useful electrical properties. Such compositions include a salt of (i) an organic polymer ion such as a polynucleic acid anion, and (ii) a polyether or polysiloxane couterion. Methods of making and using such compositions, along with electrical devices such as memory devices, are also provided.

Abstract: An integrated circuit can be operated in at least three different organization forms that can be set externally. A connection pad receives an external signal for stipulating one of the organization forms. An input of a control circuit for setting one of the organization forms is connected to the connection pad. Depending on the signal on the connection pad, the control circuit can generate at least three different states at the output to identify the respective organization forms. When the signal state has been read and the corresponding organization form has been activated, the control circuit is disconnected from a voltage supply for the integrated circuit. The inventive circuit allows the number of connection pads for stipulating the organization form to be kept low.

Abstract: An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

Abstract: A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage generator that produces a reference voltage corresponding to the value of the internal voltage, a comparator having opposite polarity inputs for producing an amplified output control signal, and a pull-up device operating from the external voltage that receives the control signal from the comparator to produce the internal voltage as an input. A dual source follower is located between the reference voltage generator and comparator and has two sections having cross-coupled inputs which respectively receive the internal reference voltage and the internal voltage to produce output voltages moving in opposite directions, each of which is applied to one input of the comparator, thereby translating the difference between Vintref and Vint to a level in a range that can be better amplified by the comparator.

Abstract: A level translating digital switch in which a switching element provides switching and level translation between a first system and a second system that operate using different logic supply voltages. In a situation where the supply voltage for the first system is larger than the supply voltage for the second system, the switching element is driven by a voltage lower than the logic supply voltage of the first system.

Abstract: A computer facility includes a synchronizing interface device coupled between a high and a low speed processing devices for allowing the processing devices having different operating speeds or velocities to be suitably coupled and communicated with each other without occurring errors. The synchronizing interface device includes a read/write device coupled between the high and the low speed processing devices, and a delay counting device coupled between the processing devices and the read/write device for suitably communicating between the high and the low speed processing devices.

Abstract: A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a physical interface, a plurality of data line amplifiers, a clock line amplifier, a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner. The training sequence may received during startup or reset, immediately after startup or reset completes, or may be received periodically during training intervals.

Abstract: The present invention provides an improved input/output (I/O) circuit that comprises a pair of buffers, a voltage reference circuit that provides first and second reference voltages to the buffers respectively, and a detection circuit. The detection circuit detects whether a supply voltage is below a switching voltage, which is a pre-selected value between operating ranges of two pre-defined supply voltages, e.g., 3.3V and 5V, respectively. If the supply voltage is below the switching voltage, the detection circuit controls the voltage reference circuit to set the first and second reference voltages to first and second predetermined values, e.g., a ground level and the supply voltage, respectively. In this way, the large signal swings of the signals output by the buffers can be substantially maintained. Therefore, high speed operations can be achieved.

Abstract: Even if a power supply potential VDD of a core section is set in an off state, a latch of a level conversion circuit holds a value corresponding to an output. It is, therefore, possible for a semiconductor device to hold an output state of an output node. Thereafter, an enable signal is deactivated, whereby the output node can be set in a high impedance state and a bus or the like can be released to the other device.

Abstract: Upon generating an inversion input signal to be inputted to a level shifter section in an inverter section, a voltage VHL, which gives an output voltage of a high level in the inverter section, is generated by a resistance division from the power supply voltages VHH and VLL in a voltage-dividing section. Thus, it becomes possible to provide a level shift circuit which can realize a reduction in the number of terminals and low power consumption by using a simple circuit construction.

Abstract: The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors 24 and 26 and pull-down transistors 20 and 22. The falling-edge 1-shot circuits 34 and 36 output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop 38. The flip flop 38 provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.

Abstract: Circuitry for providing a method (semi-analog) for normalization procedure of the Head Driver ASIC is disclosed. The circuitry utilizes current DAC's (Digital-to-Analog Converts) to adjust the amplitudes of the voltages across piezo-electric elements, based on predetermined normalization (calibration) data which are stored in separate latches (a different normalization data for each individual transducer). The transducers all receive their respective calibrated voltage values all at the same time by varying the current slope delivered to each. This method provides more simplicity and more accuracy for normalization procedure and results in better performance then using digital circuitry and digital counters.

Abstract: An inventive driver stage for driving an output on one of n-levels, which are each spaced from each other by a voltage difference of &Dgr;V, includes a plurality of field effect transistors for driving the output by supplying or removing a current to or from the output, with the relationship of the channel widths of at least two field effect transistors, which both function either to lead a current to or away, being set in dependence on the value of the voltage difference.

Abstract: A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

Abstract: The present invention provides a circuit to shift the level of an arbitrary input signal level higher than the power supply voltage to a reference logic level controlled by the power supply voltage quickly, reliably, and accurately. When a signal input to port A changes from the low level to the high level, the potential at node S1 is immediately increased to a potential significantly higher than the power supply voltage due to the capacitive coupling of the drain-gate capacitance of NMOS transistor 10, so that NMOS transistor 14 turns on at bias circuit 12 in order to allow current to flow from node S1 to power supply voltage terminal C, and the potential of node S1 is clamped to level (VCC+VTN14), that is, above power supply voltage VCC by threshold voltage VTN14. As a result, a high level equal to the level below gate potential (VCC+VTN14) by threshold voltage VTN10, that is, the potential of VCC, is obtained at source of NMOS transistor 10, that is, port B.

Abstract: An input/output buffer is provided with input buffer circuitry which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. The voltage and current on the output of the input buffer as controlled by the CMOS transistors is clamped to levels depending on a mode select signal applied to selectively provide different output levels compatible with PCI, GTL, PECL, ECL and SSTI signals.

Abstract: The invention simplifies the configuration of a level shifter and to allow fast operation. A level shifter includes a capacitor, to a first end of which a low-amplitude logic signal is input; first TFTs to apply an offset voltage to a second end of the capacitor; a capacitor, to a first end of which the low-amplitude logic signal is input; third TFTs to apply an offset voltage to a second end of the capacitor; and second TFTs connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, a node therebetween serving as an output terminal. A threshold voltage of one of the second TFTs is set to be not higher than the offset voltage applied by the first TFTs , and an offset voltage of the other of the second TFTs is set to be higher than or equal to the offset voltage applied by the third TFTs.

Abstract: In a computer system, a passive component minimization of connector pins configuration includes a motherboard and daughterboard. The daughterboard includes a selection switch coupled via passive components to a single connector pin, according to a prescribed state of multiple states of the daughterboard. In one embodiment, the passive components include three series connected resistors collectively coupled to the daughterboard connector pin. The motherboard includes a supply voltage and pull-up resistor circuit coupled to a single connector pin, and further includes decoding circuitry coupled to the motherboard connector pin for decoding a voltage level of the motherboard connector pin into binary data.

Abstract: The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.

Abstract: In a level shift circuit according to the invention, either an input signal IN or an inverted input signal XIN, which are input into the gate electrodes of n-type transistors for signal input, is also given to the substrate of that n-type transistor via p-type transistors for substrate bias. When the signal IN or XIN rises and changes, the threshold voltages of the n-type transistors for signal input is lowered due to the substrate bias effect. Consequently, even if the signal IN or XIN has a low voltage level, operation is carried out at high speeds. Also, when either an output signal OUT or an inverted output signal XOUT is changed to a high voltage level, the transistors for substrate bias become non-conducting, and thus the input signal IN or the inverted input signal XIN is not supplied to the substrate of the n-type transistors for signal input other than when the signal is changing. Consequently, a constant passing-through current does not flow to the substrate of these transistors.

Abstract: An extended voltage range level shifter is provided that includes an input inverter and first and second circuit branches. The input inverter includes thin-gate devices, is coupled to an internal power supply, and is operable to receive internal data and to generate inverted internal data. The first circuit branch includes a p-type, thick-gate transistor that has a source coupled to an external power supply; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive a reference voltage that is less than the external power supply and greater than the internal power supply; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the internal data.

Abstract: An ultra high speed Emitter Coupled Logic (ECL) flip-flop is provided and a method of operating the same. The ECL flip-flop provides for clock levels that operate at logic levels above the data levels. Since the clock operates at logic levels above the data, the clock experiences level shifts that are less than the level shifts of the data. Therefore, the clock will provide a higher fidelity signal relative to the conventional clock signal. The ECL flip-flop can operate at significantly higher data rates than conventional flip-flop circuitry.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.

Abstract: A signal interface circuit (10) having a terminal (14) for connection to a simulator system indicated schematically at (16), and a terminal (18) for connection to a system under test, indicated generally at (20). The simulator system may, for instance, be a PC based software simulation and the system under the test may, for instance, be an engine management system. The circuit (10) provides a reconfigurable interface between the systems (16, 20), allowing analog or digital signals to pass in either direction, in accordance with the configuration of the circuit (10).

Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: An ADSL transceiver chip is provided that includes an analog front-end and a digital signal processor (DSP) integrated on the same substrate. A line driver for the ADSL transceiver can be located on a separate substrate. In embodiments of the invention, the transceiver chip is implemented in a CMOS process. For example, the process could be a low voltage CMOS process. It is highly advantageous to build the analog front-end and the DSP on a single integrated IC because it allows for reduced manufacturing part count, reduced assembly time and cost. Furthermore, the line driver substrate can require a high voltage semiconductor process (e.g. 18 volts peak-to-peak) in some applications, because of the need for adequate voltage to drive the ADSL line. Whereas, the analog front-end and the DSP do not need the such a high-voltage process as required for the by the line driver 102. For example, the analog front-end and DSP can operate with 3.3 v or 5.

Abstract: An interface circuit includes a signal sending section having a first MOS transistor and a second MOS transistor which are alternately turned ON in accordance with a binary input signal. A signal receiving section has a third MOS transistor connected through a first signal transmission path to the first MOS transistor mounted in the signal sending section to feed a current with a predetermined value through the first signal transmission path when the first MOS transistor mounted in the signal sending section is turned ON. A fourth MOS transistor connected through a second signal transmission path to the second MOS transistor mounted in the signal sending section feeds a current with a predetermined value to the second signal transmission path when the second MOS transistor mounted in the signal sending section is turned ON.

Abstract: An apparatus comprising one or more output circuits each configured to configure a pad as either an input/output pad, a power pad, or a ground pad in response to a plurality of configuration inputs.

Abstract: A first module is operated at a first power supply voltage and is blocked from the first power supply voltage in a power-off mode. A second module is operated at a second power supply voltage higher than the first power supply voltage and is supplied with the second voltage even in the power-off mode. An interface circuit is connected between the first and second modules. The interface circuit includes a voltage level converting circuit having an input control circuit. The input control circuit allows the voltage level converting circuit to carry out a normal voltage converting operation in a normal operating mode, while interrupting a leakage current path of the voltage level converting circuit due to an input signal in an unstable status in the power-off mode.

Abstract: A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first converter and a second converter, wherein the first converter generates a first output signal, and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a fill swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter.

Abstract: A system and method for designing a digital circuit. The method includes identifying a single phase digital circuit implementing a desired function and operating at a first rate and determining a number of copies of the single phase digital circuit that are required for the digital circuit. Each copy of the single phase circuit is a phase and operates at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate. The method includes identifying the state devices within the single phase digital circuit, replacing each state device in the single phase digital circuit with a multiphase state saving device and providing control signals to each multiphase state saving device to control the reading and writing of state information for each phase into and out of a respective multiphase state saving device.

Abstract: Disclosed is a scan path circuit for testing a logic circuit, which comprises a plurality of scan cells each having a scan in SI, a cell output and a clock input for receiving a clock signal, connected in series with respect to the scan ins and cell outputs. Each scan cell includes a scan flip-flop 21, and a selection circuit 31 which selects either a signal of a scan in SI or a signal of a scan out SO of the scan flip-flop 21 according on a selection controlling signal to provide the selected signal to the cell output. Determining the values of the selector controlling signal with a bypass controlling shift resister 45 permits forming a bypass between the scan data input terminal SDI and the scan in SI of any scan flip-flop except the first stage flip-flop, and/or a bypass between the scan data output terminal SDO and the scan out SO of any scan flip-flop except the final stage scan flip-flop.

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

Abstract: The invention proposes an interface circuit having a very low power consumption and generating very low interference noise in the sensitive band of ratio chips. It is advantageously used to interface a microprocessor with a baseband radio processor in a telecommunication device, for example in DECT or GSM phones. The interface of the invention is current-driven. It comprises a current driver for transmitting a current in a transmission line depending on the data to be transferred. It also comprises a current receiver. The current receiver has an input node and an output node interconnected via a current mirror circuit, so that the voltage on said input node is near to the ground voltage and the voltage on said output node is changing depending on the transferred data.

Abstract: In digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits, the signals are received in analog form and have to be converted into logic levels. This is done in practice by comparing the level of the signal with its mean level. The mean level is established by an RC lowpass filter which introduces an inconvenient delay into the preparation of the mean level. The mean level of the signal, established by an RC filter is compared and applied to an input B of a comparator COMP, at the level of the analog signal delayed by a phase-shifter and applied to another input A of the comparator. In order that the delay introduced by the phase-shifter into the analog signal may be substantially the same as the delay given to the mean value by the RC circuit, the phase-shifter is made with the same RC circuit and an amplifier mounted so as to set up a phase shift transfer function of the (1−RCp)/(1+RCp) type where p is the Laplace variable.