Abstract: Methods and apparatus for bootstrap capacitor sharing in multilevel DC-DC converters are disclosed. In one example, a bootstrap capacitor voltage of the bootstrap capacitor can be alternately shared between respective control gates of a first high side primary switch and a central high side primary switch of the multilevel DC-DC converter at different times during a duty cycle of the multilevel DC-DC converter. In another example, the bootstrap capacitor voltage can be transferred to drive respective control gates of the first and central high side primary switches and can ensure full gate drive of the first and central high side primary switches to avoid channel resistance degradation thereof, even when the multilevel DC-DC converter is operated in a substantially full duty cycle mode.

Abstract: Embodiments of the present disclosure provide a transmitter system including: a source follower (SF) sub-stage having a pair of transistors, one being coupled to a biasing voltage at a gate terminal thereof, and the other including a fully depleted semiconductor on insulator (FDSOI) transistor coupled to an input signal at a gate terminal thereof, and coupled to a calibration voltage at a back-gate terminal thereof. A mixer sub-stage includes a mixer input node coupled to the SF output node of the pair of transistors of the SF sub-stage, and the mixer input node is electrically coupled in parallel to two FDSOI mixer transistors, with the FDSOI mixer transistor being electrically coupled to a respective back-gate voltage. The FDSOI mixer transistors each include a gate terminal coupled to an input voltage, while a second source/drain terminal of the FDSOI mixer transistors are each electrically coupled to a mixer output node.

Abstract: A circuit layout of laser source driving circuit includes a laser element, a first layout layer, a second layout layer, a first trace and a second trace. The first layout layer includes a first transistor. The second layout layer includes a second transistor, a capacitor, a first resistor and a second resistor. The first trace includes a first conductive line connecting the first resistor and the capacitor and a second conductive line connecting the capacitor and the laser element. The second trace includes a third conductive line connecting the second resistor and the second transistor, a fourth conductive line connecting the second transistor and the first transistor and a fifth conductive line connecting the first transistor and the laser element. A total length of the first trace and the second trace ranges from 13 mm to 19 mm.

Abstract: A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

Abstract: A timing adjustment method for a drive circuit, including: a rise detector for a rise start when a voltage-driven semiconductor element is turned off; a timing signal output unit outputting a speed change timing signal after a set delay time has elapsed from the rise start; and a conduction controller for a conduction control terminal of the semiconductor element using the timing signal, comprises: defining an estimated terminal voltage of the conduction control terminal when a rise completion time elapses; increasing a delay time by a predetermined unit time, and changing the drive signal to a turning off level again, when the conduction control terminal doesn't fall below the estimated terminal voltage after the drive signal is changed to a turning off level before the level is inverted; and determining a delay time, when the conduction control terminal falls below the estimated terminal voltage initially, as a set value.

Abstract: A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.

Abstract: A DC converter includes a non-isolated conversion module and an isolated conversion module. The non-isolated conversion module is implemented based on a redundant structure and has a first power conversion loop, a second power conversion loop, and an energy storage element. The first and second power conversion loops are connected and share the energy storage element. The energy storage element is further connected to an input terminal of the isolated conversion module. The first and second conversion loops of the non-isolated conversion module convert DC power outputted from two battery sets and output the converted power to the isolated conversion module. The isolated conversion module further supplies DC power to a load. Accordingly, power supply systems using the foregoing DC converter can reduce the number of transformer therein and thus size reduction of the power supply system can be achieved.

Abstract: A high-voltage micro-ampere current regulator which can provide stable current regulation to a corona discharge without requiring a portion of that corona discharge to be sampled. The current regulator can optionally include a first feed-back circuit which provides rapidly-adapting current regulation, and an optional second feedback circuit which provides slowly-adapting current regulation to avoid changes in corona discharge due to oxidation of the corona emitter.

Abstract: A switching gate driver and method of operating the gate driver is described. The gate driver includes a first voltage source, and a clamping voltage source configured to have a voltage that is less than that of the first voltage source. There is also a current path, for initial charging of a gate voltage of the switching gate, between the first voltage source and a ground source; and a comparator which is configured to clamp the gate voltage to the clamping voltage source as it approaches the voltage of said clamping voltage source.

Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).

Abstract: A transmission gate circuit includes a pass gate and a control circuit and provides High Voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native NMOSFET in series with the pass gate provides overvoltage protection for additional circuitry. Well biasing, gate tracking and internal node clamping circuits ensure that all of the devices of the pass gate and control circuit operated within safe operational voltage levels. The two modes of operation can be selected by an enable signal. The transmission gate circuit can support up to a 5.5 volts input in a true open drain mode while an input/output supply voltage of 3.3 volts is supplied.

Abstract: The gate drive circuit includes: a gate resistance RG1 connected to a gate G1 of a switching device Q1; and a gated diode DG1 connected in parallel to the gate resistance RG1, wherein a relationship of Vth(Di)<Vth(Tr) is satisfied, where Vth(Di) is a forward threshold voltage of the gated diode DG1, and Vth(Tr) is a threshold voltage of the switching device Q1. There is provided: a gate drive circuit having high speed switching performance in which a misoperation is suppressed and surge voltage is reduced; and a power supply mounted with such a gate drive circuit.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: Disclosed embodiments relate to a driving device of a gate driver driving a semiconductor switching element, which may include a gate driver unit for outputting a control signal to the semiconductor switching element, and a control unit for controlling an operation of the semiconductor switching element by operating at least one gate driver configuring the gate driver unit, wherein the control unit operates at least one gate driver based on a preset operation range of the semiconductor switching element and a detected operation status thereof.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: A switching device includes first and switching elements connected in series, a capacitor connected to a gate of the first switching element, a diode having an anode connected between the capacitor and the gate of the first switching element and a cathode connected to a source of the first switching element. A capacitance of the capacitor is equal to or greater than a value calculated by a predetermined expression.

Abstract: Methods and apparatuses for sensing biological functions are disclosed. Sensors can be implanted in an organ, such as the brain, and a magnetic field gradient applied to the biological tissue. The field causes the sensors to have different resonant frequencies allowing their spatial localization. The sensors can harvest power from the external coils to be able to retransmit data.

Abstract: A power circuit includes a power transistor flowing a power current to a ground according to the voltage of a driving node, a driving circuit, a first pre-driver, a second pre-driver, and a hysteresis circuit. The driving circuit includes a high-side transistor providing a supply voltage to the driving node according to a high-side voltage of a high-side node, a low-side transistor coupling the driving node to the ground according to a first internal signal, and a charge pump coupled to the high-side node and the driving node and generating the high-side voltage that exceeds the supply voltage according to the first internal signal. The first pre-driver receives a second internal signal to generate the first internal signal. The second pre-driver receives a third internal signal to generate the second internal signal. The hysteresis circuit receives a control signal to generate the third internal signal.

Abstract: Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.

Abstract: The present disclosure provides an OLED array substrate, and a display panel and a display device including the OLED array substrate. A VDD grid is provided in an existing AMOLED array substrate with a compensation function, VDD lines are connected with the VDD grid via switches, which are applied with corresponding voltages to be switched on during a light emitting stage, such that the VDD lines are electrically connected in parallel to the VDD grid, thus a total resistance of the VDD lines and the VDD grid connected in parallel is decreased relative to the own resistance of the VDD line, so as to reduce the voltage drop on the VDD line in a direction in which the scanning control lines extend, and in turn to decrease a variation in a OLED driving voltage signal effectively, ensuring uniformity of luminance across the display area.

Abstract: A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.

Abstract: There provide a shift register unit, a gate driving circuit and a display device. The shift register unit includes an input module, an output module, a pulling-down driving module, a pulling-down module and a resetting module. The input module is connected to a first input signal terminal, a first direct current signal terminal, a second input signal terminal and a second direct current signal terminal respectively. The output module is connected to a first clock signal terminal. The pulling-down driving module is connected to the first clock signal terminal, a second clock signal terminal and a low voltage signal terminal. The pulling-down module is connected to the low voltage signal terminal. The resetting module is connected to the second clock signal terminal and the low voltage signal terminal respectively. The noise of the shift register unit can be reduced and the stability of the shift register unit can be enhanced.

Abstract: A drive circuit including a signal source that outputs an AC signal, a voltage generator circuit that includes a differential amplifier that generates a first AC voltage with a constant amplitude from the AC signal and outputs the first AC voltage to one end of an external load, a voltage-to-current converter circuit that supplies an AC current with a constant amplitude in opposite phase to the first AC voltage to another end of the external load in accordance with the AC signal.

Abstract: The invention provides materials and methods (including driving methods) for reducing the effects of remnant voltages in electro-optic displays.

Abstract: A circuit for generating a constant current includes a first current generator that conducts a first current based upon a supply voltage and a resistive element and that generates a first mirrored current based on the current, a second current generator that generates a second current based on the first current wherein the second mirrored current decreases as the current increases and decreases as the current increases and a summing circuit for summing currents proportional to said first and second currents to generate an output current.

Abstract: According to various embodiments, a circuit arrangement may be provided, comprising a driver circuit configured to deliver a switching signal to a power switch such that the power switch controls a load current, a gate-back regulation circuit selectively connected to the driver circuit and the load current, and a diagnostic circuit configured to provide an enabling signal, which allows the gate-back regulation circuit to become active; and wherein the enabling signal is dependent at least in part on a condition independent of the load current.

Abstract: Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.

Abstract: A power converter includes a high side device, a low side device connected to the high side device at a switch node, an inductor connected to the high side device and the low side device at the switch node, and a high side driver. The high side driver is configured to drive a gate of the high side device at a first current for a first period of time. In response to the first period of time ending, the high side driver is configured to step down the first current for a second period of time. In response to the second period of time ending, the high side driver is configured to drive the gate of the high side device at the first current.

Abstract: A reference stage includes a first transistor, a second transistor and a resistor that are connected in series from a voltage rail to a reference load. The resistor has (i) a resistance that is a function of a digital resistance-controlling value, (ii) a first terminal coupled to a gate of the first transistor, and (iii) a second terminal that has a voltage VG2 and is coupled to a gate of the second transistor. A comparator has a first input that is coupled to the resistor's second terminal. A diode-connected reference transistor is connected from the voltage rail to the comparator's second input to apply a voltage VD at the second input. An adjusting circuit adjusts the digital resistance-controlling value to cause VG2 to approach VD until the comparator's output changes state when VG2 reaches VD.

Abstract: Disclosed herein is a signal potential converter which may perform high-speed operation and which may still maintain intended signal amplitude and operate normally even while operating at a low rate or receiving a burst signal. In this signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential at the terminal node, i.e., a signal IN, within the range of a first potential to a second potential. If a potential at the terminal node is higher than a third potential, a voltage holder circuit operates to raise the potential at the terminal node. If the potential at the terminal node is lower than the third potential, the voltage holder circuit operates to lower the potential at the terminal node.

Abstract: System and method for driving a bipolar junction transistor for a power converter. The system includes a current generator configured to output a drive current signal to a bipolar junction transistor to adjust a primary current flowing through a primary winding of a power converter. The current generator is further configured to output the drive current signal to turn on the bipolar junction transistor during a first time period, a second time period, and a third time period, the second time period separating the first time period from the third time period, drive the bipolar junction transistor to operate in a hard-saturation region during the first time period and the second time period, and drive the bipolar junction transistor to operate in a quasi-saturation region during the third time period.

Abstract: A shield element for mounting on an object, in particular a flat object, such as a chip card. The object has a base body, an RFID or NFC transponder, a transponder chip and a coil-shaped transmission antenna connected to the RFID or NFC transponder chip. The shield element has a carrier made of non-conductive material. The carrier has a closed or closable conducting path which, upon mounting the shield element on the object, shields the object from the electromagnetic fields generated by an external reading device and directed at the transmission antenna of the RFID or NFC transponder chip.

Abstract: A gate driving circuit includes a plurality of driving stages applying gate signals to gate lines of a display panel. Among the plurality of driving stages, a k-th (k being a natural number equal to or greater than 2) includes a first node, an output part that is connected to the first node and outputs a k-th gate signal in response to a voltage of the first node, a control part that controls an electric potential of the first node, an inverter part that outputs a k-th switching signal, and a pull-down part that receives a (k?1)th switching signal from a (k?1)th driving stage of the plurality of driving stages and lowers a voltage of the output part in response to the (k?1)th switching signal.

Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.

Abstract: A display device includes a display unit including a light emitting device, data and gate driver for respectively applying data and gate voltages to the display unit, and a signal controller for transmitting, to the data driver, image data having a clock embedded therein. The data driver recovers a first internal reference clock during a low period of a first frame control signal, using the image data having the clock embedded therein, compares the frequency of the recovered first internal reference clock with the frequency of a previously stored reference clock, when the frequency of the recovered first internal reference clock is within an error range of the frequency of the previously stored reference clock, outputs the recovered first internal reference clock and receives a second frame control signal, and when the second frame control signal corresponds to a CDR unit operating condition, recovers a second internal reference clock.

Abstract: A control circuit comprising a driving circuit, which comprises a voltage adjusting circuit for generating a control voltage, and comprises a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. The control circuit further comprises: a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a voltage selecting circuit, for outputting one of the candidate voltage output from the candidate voltage selecting circuit and a ground voltage as the bias voltage.

Abstract: A driving circuit is a circuit selectively outputting one of a staircase wave and a square wave from an output terminal, to drive a capacitive load, and includes a first power source supplying a constant voltage VH, a first FET connected between the output terminal and the first power source, a first transformer in which an output side coil is connected to a gate of the first FET, a first input terminal connected to an input side coil of the first transformer via a capacitive element, a second power source supplying a constant voltage VL, a second FET connected between the output terminal and the second power source, a second transformer in which an output side coil is connected to a gate of the second FET, and a second input terminal connected to an input side coil of the second transformer via a capacitive element.

Abstract: A full-wave rectifier is disclosed. In one embodiment the full-wave rectifier includes two input paths configured to receive an alternating input voltage, two output paths configured to provide a direct output voltage, and four switched-mode rectifying paths that are connected between each of the input paths and each of the output paths, wherein the switched mode rectifying paths are configured to connect a first input path to a first output path and a second input path to a second output path during a first half wave of the input voltage, and to connect the first input path to the second output path and the second input path to the first output path during a second half wave of the input voltage, and wherein the switched-mode rectifying paths include cascode circuits.

Abstract: A driver of a power switch is described that is used to supply power to a load for at least a switching cycle of the power switch. The driver includes at least one output that contains a high-ohmic output and a low-ohmic output. The high-ohmic output is enabled during at least one portion of a first phase of the switching cycle when the power switch is switched-off. The low-ohmic output is enabled during a second phase of the switching cycle when the power switch is switched-on and during any remaining portion of the first phase other than the at least one portion of the first phase when the high-ohmic output is enabled.

Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a current generator circuit, which generates current-integrator drive currents. The control circuitry generates one or more control signals to control generation of current-integrator drive currents by the current generator circuit during transducer-driving periods. A current integrator integrates current-integrator drive currents generated by current generator circuit to generate transducer drive signals.

Abstract: This document discusses, among other things, apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.

Abstract: An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail.

Abstract: The present disclosure is directed to a current limiting circuit. The current limiting circuit may include a load, a first switch that controls current supplied to the load, and a first resistive network. The current limiting circuit may further include a voltage divider connected across the first resistive network and including a thermistor. The current limiting circuit may further include a first bipolar junction transistor that controls switching of the first switch. The output terminal of the voltage divider may be connected to a base junction of the first bipolar junction transistor.

Abstract: The present disclosure includes a method of charging a battery. In one embodiment, the method comprises receiving, in a battery charging circuit on an electronic device, an input voltage having a first voltage value from an external power source. The battery charger is configured to produce a charge current having a first current value into the battery. The input current limit and/or duty cycle of the charger is monitored. Control signals may be generated to increase the first voltage value of the input voltage if either (i) the input current limit is activated or (ii) the duty cycle reaches a maximum duty cycle. The charger also receives signals indicating a temperature inside the electronic device and generates control signals to decrease the value of the input voltage when the temperature increases above a threshold temperature.

Abstract: One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.

Abstract: In one example, a method includes receiving, at a first time by a power switching device via an input connector of the power switching device, a signal that causes the power switching device to output a power signal to a load via an output connector of the power switching device. In this example, a voltage level of the power signal satisfies a voltage threshold at a second time that is later than the first time. In this example, the method also includes communicating, by the power switching device and during a time period between the first time and the second time, with an external device via the input connector.

Abstract: A power module includes: an insulating layer; a leadframe disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip and at least a part of the metal layer, wherein a groove into which a part of the insulating layer is inserted is formed on a surface of the leadframe facing the insulating layer. Accordingly, there can be provided the power module with improved reliability so that the insulating layer and the leadframe may be hardly deviated from each other even if external force is applied thereon; and a fabrication method for such a power module.

Abstract: A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node.