Abstract: An input protection circuit for a semiconductor memory device senses when the level of an external input signal drops below a reference voltage corresponding to a predetermined logic level, thereby enabling instant correction. The input protection circuit is interposed between an external power voltage terminal and an input terminal of the input buffer, and the external power voltage is transferred to the input terminal of the input buffer when the level of the external input signal applied to the input terminal drops below the predetermined logic level. The circuit includes an internal reference voltage generator which supplies a voltage having a level corresponding to the predetermined logic level and designed to compensate for a known device offset so that the external input signal applied to the input terminal can be instantly corrected.

Abstract: An electrical overstress power protection device consists of a diode limiter array and an input and output electrical matching network. All of these functions are integrated monolithically on a single semiconductor chip which allows ease of use, small size, and high frequency operation. The device is used to protect instrument input and output circuitry from damage.

Abstract: An output buffer is provided with a terminal, a first driver, a second driver and enable circuitry. The first driver is for driving the terminal to a voltage corresponding to a logic value of the output signal. The second driver is for driving the terminal to the same voltage as the first driver, when the output signal transitions in logic value. The enable circuitry responds to a transition in logic value of the output signal by, after a predetermined delay, enabling the second driver to drive the terminal. However, the enable circuitry only enables the second driver to drive the terminal for a predetermined time period.

Abstract: A multi-bit data output buffer for a semiconductor memory device, comprising a data input circuit for inputting at least two bit data, at least two bit data buffering circuits, each of at least two bit data buffering circuits buffering a corresponding one of at least two bit data from the data input circuit, and a bit data comparison circuit for controlling the amounts of current flowing to at least two bit data buffering circuits according to logic values of at least two bit data from the data input circuit. According to the present invention, the multi-bit data output buffer is capable of minimizing the generation of noise in the output data and enhancing a response speed of the output data with respect to the input data.

Abstract: In an output buffer circuit for a semiconductor integrated circuit, the waveform of an input to the gate of each output transistor slowly changes not only when the transistor is turned on but also when it is turned off.

Abstract: Novel high voltage electronic amplifiers that are capable of being monolithically integrated using low voltage semiconductor fabrication processes are described and claimed. A cascade of low voltage current mirrors is described that can act as a high voltage amplifier output circuit. A transconductor and level shift circuit is also described that can be employed in the high voltage amplifier output circuit. A high voltage current source is described and is constructed from the series combination of a low voltage transistor and a parasitic field oxide transistor. Additionally, a differential amplifier having bias-current shunting transistors is described that can be used to limit quiescent current from the output power supply of the high voltage amplifiers.

Abstract: An inverter device is provided which comprises an inverter including a pair of transistors, and first and second delay circuits. The first and second delay circuits are connected to respective inputs of the pair of transistors so as to cause the transistors of the pair to switch with a greater time difference, thereby reducing noise due to switching operations in the inverter.

Abstract: A single-ended input amplifier circuit for use within a magnetic media storage system includes circuits for concurrently biasing and amplifying signals generated by a magnetoresistive element. The amplifier receives power from a single-ended power supply. A first resistor is included for setting the gain of the amplifier and providing an output signal corresponding to the signals generated by the magnetoresistive element. A first feedback circuit generates a first biasing current provided to the magnetoresistive element. The first feedback circuit includes a first transconductance amplifier which amplifies the difference between the output signal and a reference voltage. A second feedback circuit generates a second biasing current provided to the magnetoresistive element. The second feedback circuit includes a second transconductance amplifier which amplifies the difference between the reference voltage and a voltage signal taken from a node between two resistors.

Abstract: An amplifier controller (104) is described for operating from a single voltage power supply (105). A switch (103) is coupled between the amplifier (102) and the power supply (105). The controller (104) includes a power conditioning circuit (106) for generating doubled and tripled voltages and positive and negative voltages for operating the controller (104) and the amplifier (102). Internal voltage regulators (138, 142) control the magnitude of the generated voltages. The controller (104) further includes: (i) a circuit (172) for disabling the controller (104) and amplifier (102) in response to an idle signal presented thereto, (ii) a circuit (178) for energizing the switch in response to a turn-on signal (128) so that the amplifier (102) can amplify, and (iii) a circuit (176) for sensing the presence or absence of negative polarity (Vss) on a second lead (188) of the amplifier (102) and, if not present, disabling the switch (103) despite the presence of the turn-on signal.

Abstract: A data line for an integrated circuit such as field programmable gate array, has a relatively fast rise time, consumes relatively low amount of current, and maintains a relatively fast fall time. A data conductor is connected to a circuit element providing a current path from the data conductor to a source of the supply voltage. A plurality of data-in drivers are connected to the data conductor which act in one state to pull the data conductor from the supply voltage to ground, and act in another state to present high impedance to the data conductor. A dynamic element is included, which connects an additional current path between the data line and the supply during transitions from ground to the supply, and which disconnects the additional current path otherwise. This speeds up the transitions from low to high, while not opposing the transitions from high to low.

Abstract: A semiconductor memory device 200 includes: a memory cell array 101 including a plurality of pairs of bit lines (BL, XBL), a plurality of word lines WL and a plurality of memory cells 100; a decoder 104 for decoding address information to activate one of the plurality of word lines WL in accordance with the address information; precharge circuits 105 for setting each of the plurality of pair of bit lines (BL, XBL) to a predetermined precharge potential; sense amplifiers 110; and potential difference transmission circuits 109 provided between the memory cell array 101 and the sense amplifiers 110. The potential difference transmission circuits 109 hold a potential difference V.sub.d0 between respective pair of bit lines among the plurality of pairs of bit lines (BL, XBL) and transmit the held potential difference V.sub.d0 between the pair of bit lines to a respective sense amplifier 110. The sense amplifier 110 amplifies the potential difference V.sub.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: Fault protection using parallel output CMOS devices for integrated circuit analog switches prevents damage to circuits incorporating the same by not coupling analog input voltages beyond the power supply voltages to the analog output, and by preventing the forward biasing of any P/N junction to provide a low impedance path between such fault analog input voltage and either power supply terminal. Circuitry is provided for having the analog output electrically floating whenever the switch is commanded off, regardless of whether the analog input is within the power supply voltage range or not, to provide the analog input as the analog output whenever the switch is commanded on and the analog input is within the power supply voltage range, and to clamp the analog output at the closest power supply voltage whenever the switch is commanded on and the analog input is beyond the power supply voltage range. Alternate embodiments are disclosed.

Abstract: An electronic clamping circuit is provided in one preferred embodiment, the clamping circuit includes a pair of series-connected diodes, both having the same bias, which are shunted across a feedback path of a transimpedance amplifier circuit. A capacitive element is connected to a node in-between the diodes and a potential (e.g., ground). The arrangement of the diodes and capacitive element serve to keep the amplifier circuit's operation within its linear limits without severely degrading its bandwidth.

Abstract: A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit.

Abstract: An output driver including pull-up and pull-down output transistors is formed in a silicon substrate. The source and the drain of the pull-up output transistor are formed in a common bulk region of the substrate. A bulk potential control circuit for controlling the voltage of the bulk region, a resistive element and a gate drive control circuit are also formed in the silicon substrate. A layer of interconnect formed over a top surface of the silicon substrate may selectively couple into the output driver circuit one or more of the resistive element between a source of the pull-down output transistor and a reference voltage source, the bulk potential control circuit to control the voltage of the bulk region of the silicon substrate, and the gate drive control circuit to control the rate of change of voltage on the gate of the pull-down transistor as a function of the voltage on this gate.

Abstract: Power consumption by the driving circuitry of an output stage, employing a slew-rate controlling operational amplifier, is reduced by modulating the level of the current output by the operational amplifier in function of the working conditions of the output stage. Switching delay may also be effectively reduced. An auxiliary current generator forces an additional current through the conducting one of the pair of input transistors of the operational amplifier only during initial and final phases of a transition, essentially when the slew rate control loop ceases to be effective. The boosting of the bias current through the conducting input transistor is determined by the degree of unbalance of the differential input stage of the operational amplifier, without the use of dissipative sensing elements.

Abstract: An object of the present invention is to provide a power line connection circuit which obtains a desired turn-on resistance and a turn-off resistance without using a complex external circuit. The power line connection circuit provides a MOS transistor arranged in a power supply line, whose continuity is changed by applying a control signal from a control unit; a voltage conversion means for converting the voltage of the control signal; and a clamp means for clamping the converted voltage output from the voltage conversion means so as to have a predetermined voltage difference with respect to the voltage of said power supply line.

Abstract: An integrated circuit (IC) with metal-oxide semiconductor field effect transistor (MOSFET) circuitry and on-chip protection against oxide damage caused by plasma-induced electrical charges includes a MOSFET circuit for receiving and processing an input signal and a complementary MOSFET pass gate coupled to the input thereof for receiving and passing the input signal thereto. The complementary MOSFET pass gate includes complementary MOSFETs with control terminals, input terminals and output terminals, with the control terminals being connected for receiving the IC power supply voltage and ground potentials, the input terminals connected together for receiving the input signal and the output terminals connected together and to the input of the MOSFET circuit for passing the input signal thereto in response to the receiving of the IC power supply voltage and ground potentials.

Abstract: A current switch for borehole logging tools operating at high temperatures with high load currents, which includes a driver unit that responds to an input digital control signal by holding an output field effect transistor in a turn-off state until its gate electrode is fully charged before allowing the transistor to supply current to an inductive or acoustic load, and by effecting a rapid discharge of the gate electrode to turn the transistor off. A digital coupler is inserted between the source of the input digital control signal and the driver unit to electrically decouple the load current from the source. The effects of spurious noise contaminants including power spikes in the load, fly-back coupling, and Miller's capacitance thereby are minimized and a switching action with minimal transition time is achieved.

Abstract: The inventor has created several methods to eliminate or greatly reduce the ground loop problem. The inventor has discover that ground loop distortion is caused by the switching from positive to negative in alternating current. He has designed several devices to eliminate this problem. In his first embodiment he places a set of two diodes either cathode to cathode or anode to anode, or a neon bulb, or piezoelectric crystals in parallel with all the capacitors in an amplifier or other electronic device. These sets of diodes eliminate the ground loop distortion within the amplifier or electronic device. The applicant has also devises several power supply that eliminate or greatly reduce the ground loop distortion in an amplifier or electronic device they are attached to. Also the applicant has found that by attaching two diodes either anode to anode or cathode to cathode, or a neon bulb, or a piezoelectric crystals between an audio, video or digital cable and its ground will reduce distortion within the cable.

Abstract: An adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the signal propagation speed as noise conditions worsen. This active filter has a level shifting inverter, which inverts the input signal and converts the logic levels of the input signal into chip logic levels. This inverted input signal is presented at the input of a driver inverter, which once again inverts the signal. This second inversion filters out input noise, because a voltage controlled device (which is attached to the driver inverter) reduces the switching speed of this inverter as the noise condition worsen; this reduction in switching speed reduces the propagation speed and thus filters out noise.

Abstract: A voltage overshoot limiter having a detector circuit that looks at the node at which the undesirable overshoot would occur and provides a signal that is proportional to the unipolar rate of change of voltage at the node. This output is fed back to the first stage of the control circuit, error amplifier, etc. in such a manner as to reduce the rate of change of the circuit's nodal voltages to less than their slewing rates. By modifying the value of the detector's output for a given detected slew rate at the node, it is possible to reduce both its overshoot significantly and to reduce its unipolar rate of voltage change. The invention is described as being unipolar, that is, responding to rates of change of voltages which are either positive or negative, though bipolar implementations may be realized.

Abstract: A system and method for increasing clock edge transition speed and edge phase accuracy. A split clock buffer provides separate controls of a pull-up transistor and a pull-down transistor. The buffer is off (high impedance) between clock edge transitions. Clock edge transition speed is improved by avoiding the transient condition of a conventional clock buffer where both of the pull-up and pull-down transistors are both on during clock edge transition.

Abstract: A load adaptive pad driver for integrated circuits provides a substantially constant speed output at the pad regardless of the load connected to the pad. A reference slope signal, based on variables such as fabrication process, and operational voltage and temperature ranges and biased to give a substantially flat response, is compared to the signal output of a resistive-based pad driver circuit. When a transition between output signal levels provided by the pad driver circuit is slower than the reference signal slope, an auxiliary driver circuit is used to compensate. Electromagnetic interference is also reduced via said load adaptive pad driver.

Abstract: A circuit for eliminating false triggering of a power device in an optically coupled drive circuit caused by dv/dt sensitivity of an optocoupler of the drive circuit comprising a latch circuit having an input coupled to an output of the optocoupler and having an inhibit input; and an inhibit signal generating circuit coupled to an output of the latch circuit for providing an inhibit signal of a preset period of time to the inhibit input of the latch circuit when the output of the latch circuit changes state, thereby inhibiting the passage of any high dv/dt spurious or noise signals to the output of the latch circuit during the preset period of time.

Abstract: A time domain signal filter detects a change in an input signal and replaces the input signal with an internally generated substitute signal for a filter period. The filter period is user selectable and can be set through a bit in a hardware register. After passage of the filter period, the time domain signal filter resumes direct supply of the input signal as the output signal. The time domain signal filter determines the start of the filter period by using either the falling edge or the rising edge of the clock input, whichever edge comes first after detecting the change in the input signal.

Abstract: An integrated circuit, includes an output stage with an input which is coupled to a first and a second gate of an NMOS transistor and a PMOS transistor, respectively, and an output which is connected to a first and a second supply terminal via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor and a switching circuit. The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching circuit is rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.

Abstract: A row address detection circuit includes a fuse bank, including a plurality of fuses connected to a common node. A precharge circuit is connected to bias the common node at a supply voltage. The fuse bank is also coupled through an isolation circuit to a buffer circuit. Selected ones of the fuses are blown in a pattern corresponding to an address of a defective circuit to enable a redundant circuit to be substituted for the defective circuit. The isolation circuit allows the buffer circuit to measure the node voltage to determine if an input to a group of address select lines corresponds to the address of the defective circuit, yet isolates the buffer circuit from the common node to prevent partially blown fuses from placing an excessive load on the buffer circuit. In one embodiment, the isolation circuit is realized with a pair of transistors of opposite channel type coupled for synchronous switching to provide substantial isolation while minimizing voltage drop.

Abstract: A switching arrangement in motor vehicles for the timed switching-on of inductive consuming devices by a semiconductor power switch timed by a control source has a timing element of the cut-in circuit of the semiconductor power switch that is smaller than the reaction time of the control source. This reaction time is significantly shorter than the rise time of the control voltage of the semiconductor power switch.

Abstract: A variable operation speed MOS transistor having a source, a drain and a gate with a plurality of contacts formed thereon. One end of the gate of the variable operation speed MOS transistor is connected to drains/sources of first MOS transistors, while the plurality of the contacts formed on the gate of the variable operation speed MOS transistor are connected to the drains/sources of second MOS transistors, which are of an opposite type to that of the first MOS transistors, and the source or drains of which are connected to Vcc. Input signals are supplied to the respective gates of the first and second MOS transistors in such a manner as to adjust the turn-on and turn-off speeds of the variable operation speed MOS transistor.

Abstract: Two controlled current gate drives are provided for driving parallel P and N channel pass devices, so that the rise time of the voltage at one gate of the pass devices overlaps with the fall time of the other to reduce capacitive signal coupling of the signal applied to an FET gate to the FET source and drain. Low-level current sources drive the gates of the pass devices with opposite polarities. A current mirror is used to control the currents provided by the gate drives to control the tradeoff between switching speed and switching noise coupling.

Abstract: A buffer circuit, such as for use with a low voltage hearing aid, is disclosed. The hearing aid comprises a microphone, a receiver and an amplifier. The amplifier is disposed between the microphone and the receiver. The buffer circuit has a MOS device including a well terminal and a gate terminal equipotentially coupled together to reduce the effective threshold voltage of the MOS device, thereby reducing the gate-to-source voltage of the MOS device. This permits a greater linear output signal range for the amplifier.

Abstract: A driver for providing binary signals from a data system to a transmission line is disclosed. A first n-channel transistor has its drain coupled to the transmission line and its source coupled to ground. The channel of the first n-channel transistor has a width that is greater than its length. A first inverter stage conducts current from a first voltage supply to the gate of the first n-channel transistor in order to switch the first n-channel transistor into a conductive state and conducts current from the gate of the first n-channel transistor to ground in order to switch the first n-channel transistor into a non-conductive state. A discharge circuit provides a discharge path from the gate of the first n-channel transistor to ground during a discharge time period and then removes the discharge path at the end of the discharge time period.

Abstract: A current buffer circuit comprises an input terminal, an output terminal, a first transistor of a first conductivity type having a base connected to the input terminal and an emitter, and a second transistor of a second conductivity type having a base connected to the input terminal and an emitter. The buffer circuit further includes a third transistor of the second conductivity type having a base connected to the emitter of the first transistor, a collector connected to a first power supply terminal, and an emitter connected to the output terminal, a fourth transistor of the first conductivity type having a base connected to the emitter of the second transistor, a collector connected to a second power supply terminal, and an emitter connected to the output terminal, and a fifth transistor of the second conductivity type having a base connected to the collector of said fourth transistor, a collector connected to said output terminal, and an emitter connected to the second power supply terminal.

Abstract: A serial differential cell includes complementary positive and negative pass gate networks coupled to a differential amplifier, which produces a valid logic output. The complementary pass gate networks can include one or more pass gate stages coupled in series. In a serial differential multiplexer, a stage includes first and second inputs, and a select input for controlling which input is passed to an output of the stage. For multiple stages, the output of a first stage is coupled to one of the inputs of a next stage. A number of stages can be coupled together in series to form networks, with a differential amplifier coupled between positive and negative networks where necessary to provide a valid logic output.

Abstract: A circuit arrangement for gate-controlling a MOS field-effect transistor (T.sub.o) comprises a discharge circuit (12) via which the charge stored in the gate-source capacitance (C.sub.GS) can be discharged according to a time constant, the value of which depends on the internal impedance of said discharge circuit (12). This discharge circuit (12) can be switched between two conditions determined by a relatively large and a relatively small internal impedance respectively and assumes the condition dictated by the relatively small internal impedance as soon as the gate-source voltage (U.sub.GS) has dropped below a predetermined limit.

Abstract: A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.

Abstract: An integrated circuit output stage is intended for use with an operational amplifier. The output is capable of driving capacitive load to within a V.sub.SAT of the power supply rails. The complementary output transistors are driven by way of a combination of buffers and complementary differential amplifiers which act to bias the stage in class AB. The quiescent current is stabilized and controlled, in part, by simple resistor rationing. The output transistor saturation is sensed and a current limit is imposed so that hard saturation is avoided. Frequency compensation is achieved in a manner that responds to output transistor saturation so as to improve the high frequency transient response. Feedforward capacitors are also included to further improve high frequency response.

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Abstract: A semiconductor integrated bipolar flip-flop circuit prevents or suppresses erroneous operation arising from a current induced by external noise and flowing through a parasitic capacitance associated with a p-type diffused resistor. The semiconductor integrated circuit includes bipolar transistors that are directly involved with set and reset operations of the flip-flop circuit having bases connected to a two-stage inverter including bipolar transistors so that the bases of the bipolar transistors involved in setting and resetting are not connected directly to a p-type diffused resistor.

Abstract: A driver for providing binary signals from a data system to a transmission line and a method of charging and discharging the driver output transistor is disclosed. A preferred embodiment of the driver includes an output transistor having its drain-source circuit connectable between the transmission line and ground. An input stage provides a first charging current to the gate of the output transistor for a first charging time period and a first discharging current for discharging the gate of the output transistor for a first discharging time period. A first falling edge speed-up circuit provides a second charging current to the gate of the output transistor for a second charging time period to charge the voltage level of the gate of the output transistor to approximately its threshold voltage level.

Abstract: A circuit and method for reducing a gate voltage of a transmission gate to prevent overvoltage that could damage or affect reliability of the transmission gate. The transmission gate resides in a charge pump circuit (41) coupled to a capacitor for generating a voltage greater than a power supply voltage. A buffer (44,45) receives a control signal and couples to a gate terminal of the transmission gate. The buffer (44,45) includes a power supply terminal that is coupled to a variable voltage reference (43). The variable voltage reference (43) provides a voltage that reduces the gate voltage of the transmission gate when an output voltage of the charge pump circuit reaches a predetermined voltage. The variable voltage reference (43) reduces a voltage range between logic levels provided by the buffer (44,45) to protect the transmission gate from an excessive voltage.

Abstract: An output driver for use with low voltage level, high speed data transmission busses. An open drain output transistor has a controlled slew rate for a high to low output transition. The slew rate control is provided by controlling the slew rate of the gate voltage of the output transistor in response to an input transition. A slew rate control circuit coupled to the output transistor includes a current source powered by a high stability bias generator, a diode and a capacitance. The current source controls the amount of current available at the gate of the output transistor. The diode and the capacitance combined are used to control the initial voltage at the gate of the output transistor, and the slew rate for the rising voltage waveform at the gate of the output transistor. The resulting circuit has a fast transition time in response to an input transition combined with a tightly controlled slew rate.

Abstract: A circuit and method for reducing voltage error when charging and discharging a variable capacitor (44) through a switch (43). The switch (43) comprises a plurality of transmission gates (53-55) coupled in parallel. A control circuit (42) provides control signals for enabling transmission gates of the plurality of transmission gates (53-55). The control circuit (42) changes the resistance of the switch (43) by selecting an appropriate transmission gate wherein each transmission gate has a different resistance. The resistance of the switch (43) is varied as a capacitance of the variable capacitor (44) is changed to maintain a predetermined RC time constant over the entire range of capacitor values of the variable capacitor (44).

Abstract: A bidirectional input/output buffer is disclosed, where the receiver includes complementary bus keeper transistors. The keeper transistors are of opposite conductivity types, and have their gates coupled to the output of a receiver inverter. The keeper transistors thus reinforce the driven data state at the input of the receiver, in CMOS latch fashion, and hold the prior data state thereon after the driving output driver is in tristate. The keeper transistors have significantly weaker drive characteristics than the other receiver transistors, and than typical output drivers, so that the keeper transistors can be easily overdriven with the next data state, if different. In addition, the source/drain resistance of the keeper transistors is also preferably quite high, so that the power dissipation on switching is relatively low. These characteristics are readily achievable by providing relatively long channel lengths for the keeper transistors, relative to other transistors in the circuit.

Abstract: A balanced driver circuit which essentially eliminates inductive noise without a power dissipation penalty is disclosed. The balanced driver circuit is similar to a conventional balanced driver circuit however the circuit is impedance matched at both ends and has resistors connected in series with the outputs of the emitter followers in the chip. The resistors are equal in value to a termination resistor less the output impedance of the emitter followers. The impedance between the pair of signal leads, referred to as the primary and secondary leads is equal to the sum of the termination resistors. The current traversing the secondary lead has the same amplitude, but the opposite sign as the current traversing the primary lead. Thus, there is negligible current return through the common ground leads.

Abstract: An apparatus for preventing transferring noise of a digital signal comprises, a noise-transfer preventing circuit 11 which transfers a signal D whose potential represents data to be transferred originally in binary data and a signal DB whose potential represents the other data at the same time, inputs the signals D and DB at an input block 10 side, outputs one signal D as an input signal as a normal state when the signals D and DB are the potentials representing different data "1" and "0", and when the signals D and DB are the potentials representing same data, continues to output the signal previously outputted as the input signal as an abnormal state, whereby, at the time of transferring the digital signal, it can be avoided to transfer the level change according to fluctuations of the signal potential or the signal change on the other signal lines as the dat signal.

Abstract: A data output buffer for a semiconductor memory device having a plurality of memory cells, each of the memory cells storing a data signal. The data output buffer comprises: an input line for inputting the data signal from each of the memory cells; a pull-up driver connected between a supply voltage source and an output line, the pull-up driver being driven in response to a first logic of the data signal from the input line; a pull-down driver connected between a ground voltage source and the output line, the pull-down driver being driven complementarily to the pull-up driver in response to a second logic of the data signal from the input line; at least one auxiliary pull-up driver connected in parallel to the pull-up driver; and a controller for driving the at least one auxiliary pull-up driver for a predetermined time period from a start portion of the first logic of the data signal from the input line.

Abstract: An interface circuit for interfacing between an integrated circuit (IC) on a transmitting side and an IC on a receiving side over a line on a printed circuit board comprises an output circuit implemented in the IC on the transmitting side and composed of a current source for supplying a given current and a switching circuit for cutting off the given current according to a binary signal and delivering the given current as a current signal to the line, and an input circuit implemented in the IC on the receiving side and composed of a transimpedance circuit whose input impedance is equal to the one of the line and which converts the current signal into a voltage signal, and a comparator for identifying the voltage signal relative to a given threshold voltage and reproducing the binary signal. This circuitry makes it possible to provide an interface circuit that can be implemented in a CMOS IC during CMOS processing and operated at a low voltage.