Signal Transmission Integrity Or Spurious Noise Override Patents (Class 327/379)
-
Patent number: 6765426Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.Type: GrantFiled: August 12, 2003Date of Patent: July 20, 2004Assignee: Broadcom CorporationInventor: Janardhanan S. Ajit
-
Patent number: 6756824Abstract: Disclosed are novel methods and apparatus for efficiently providing self-biased driver amplifiers for high-speed signaling interfaces. In an embodiment of the present invention, a self-biased amplifier driver is disclosed. The driver includes a sensing circuit to sense a presence of noise in a power supply signal. The sensing circuit may include a current source to adjust an output signal of the sensing circuit in accordance with the power supply noise. The driver may further include: an amplifier coupled to the sensing circuit to amplify the sensing circuit output signal, a pre-driver to receive a data signal, and a driver coupled to the amplifier and the pre-driver to receive an amplifier output signal and a pre-driver output signal.Type: GrantFiled: November 12, 2002Date of Patent: June 29, 2004Assignee: Sun Microsystems, Inc.Inventors: Aninda K. Roy, Samudyatha Suryanarayana
-
Patent number: 6756623Abstract: When a driving unit (100) charges gate input capacitance (6) of an IGBT (7), the gate input capacitance (6) accumulates electric charges which are accumulated therein when the driving unit (100) discharges the gate input capacitance (6). Therefore, it is possible to reduce the amount of electric charges to be supplied to the gate input capacitance (6) by the driving unit (100) until the charge of the gate input capacitance (6) is completed. As a result, it is possible to reduce the required power capacity of a control power supply (15a). Further, since the electric charges accumulated in the gate input capacitance (6) are effectively used, it is possible to ensure power savings of a semiconductor device.Type: GrantFiled: April 17, 2002Date of Patent: June 29, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Furuie, Nobuhisa Honda
-
Patent number: 6741114Abstract: An apparatus for finely adjusting the input capacitance of a semiconductor device and a method of fabricating the apparatus are disclosed. The invention adjusts finely the input capacitance without increasing a layout area of the device by using a capacitor constructed with a poly layer/device isolation layer/P-type substrate. The poly layer is formed on an unnecessary space provided by the device isolation layer under an input pad.Type: GrantFiled: December 10, 2001Date of Patent: May 25, 2004Assignee: Hynix Semiconductor Inc.Inventor: Taek Seung Kim
-
Patent number: 6704826Abstract: A digital isolation circuit comprises a plurality of CMOS transistors. The transistors may be connected together to form either a logic NAND gate or a logic NOR gate, but the isolation circuits preferably are not used to provide the NAND or NOR logic functions. The isolation circuit isolates one input data signal from an output signal in response to a control input signal. If the control signal is driven to one state (e.g., logic 1), the isolation circuit can be made to function as an inverter when no isolation is needed. In the opposite logic state, the control signal causes the isolation circuit to isolate the input data signal from the output signal.Type: GrantFiled: September 21, 2000Date of Patent: March 9, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: An H. Lam, Wiley R. Flanakin, Sompong Paul Olarig
-
Patent number: 6674275Abstract: A current source circuit is described for generating control current. The circuit is capable of generating a very accurate reference current and in particular dealing with the problem which can arise from injected noise. A feedback loop is implemented to reject the charge injection noise.Type: GrantFiled: February 14, 2002Date of Patent: January 6, 2004Assignee: STMicroelectronics LimitedInventor: Saul Darzy
-
Publication number: 20030222703Abstract: An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.Type: ApplicationFiled: May 28, 2003Publication date: December 4, 2003Inventors: Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang
-
Patent number: 6650174Abstract: Circuitry and methods are provided for reducing rise time associated with signals on an open-drain or open-collector signal line. Signal line voltage is monitored to determine if the signal line is being pulled LOW. If the signal line is not being pulled LOW, as indicated by signal line voltage exceeding a threshold level, additional pullup current is provided. The additional current may be provided gradually in relation to the signal line voltage, or may be provided in full whenever voltage exceeds the threshold. Circuitry may also be provided to monitor voltage slew rate on the signal line, and to enable the additional pullup current only when the slew rate exceeds a positive threshold level.Type: GrantFiled: December 18, 2001Date of Patent: November 18, 2003Assignee: Linear Technology CorporationInventor: David Bundy Bell
-
Patent number: 6642755Abstract: In a bus driver for driving a bus having first and second power supply terminals, an input terminal for receiving an input signal and an output terminal connected to the bus, a switching element is provided between the output terminal and the second power supply terminal, and the switching element is controlled by a voltage at the input terminal. A pull-up resistor is connected between the first power supply terminal and the output terminal.Type: GrantFiled: March 20, 2001Date of Patent: November 4, 2003Assignee: NEC CorporationInventor: Hiroshi Kamiya
-
Publication number: 20030184359Abstract: A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.Type: ApplicationFiled: October 8, 2002Publication date: October 2, 2003Applicant: Texas Instruments IncorporatedInventors: David A. Gammie, Jeffrey B. Parfenchuck, David M. Jones, Jerry L. Doorenbos
-
Patent number: 6628153Abstract: A phase-locked loop (PLL) circuit performing a fractional division includes a phase comparator circuit, a phase difference signal modulation circuit, and an oscillator circuit. The phase comparator circuit compares phases of two signals and outputs first and second phase difference signals. The phase difference signal modulation circuit modulates the second phase difference signals into third phase difference signals, and the oscillator circuit oscillates based on the first and third signals.Type: GrantFiled: August 10, 2001Date of Patent: September 30, 2003Assignee: Fujitsu LimitedInventor: Shinichi Inoue
-
Patent number: 6621323Abstract: A circuit samples a voltage on a simultaneous bi-directional bus, and subtracts an outbound voltage to determine an inbound voltage. Sampling capacitors are variable to adjust for matching time constants. A mechanism is provided to sample error voltages over clock phase variations and sampling capacitor values.Type: GrantFiled: April 24, 2002Date of Patent: September 16, 2003Assignee: Intel CorporationInventors: Bryan K. Casper, Aaron K. Martin, Stephen R. Mooney, James E. Jaussi
-
Publication number: 20030169091Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch, having a first terminal coupled to two or more voltage sources, with each voltage source providing a distinct voltage level representing a logic high level. The circuit includes first circuitry, having an output coupled to the switch for initially placing a first voltage across the switch representative of a logic low level. The circuit further includes second circuitry having an input coupled to the switch for sensing a voltage differential appearing across the switch and an output for indicating whether the voltage appearing across the switch is at any voltage representative of the logic high level, the second circuitry being controlled to selectively eliminate static current drawn by the circuit based upon the value of the output of the second circuitry.Type: ApplicationFiled: May 17, 2002Publication date: September 11, 2003Inventor: Tom Youssef
-
Publication number: 20030155960Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.Type: ApplicationFiled: June 28, 2002Publication date: August 21, 2003Inventor: Janardhanan S. Ajit
-
Patent number: 6608519Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.Type: GrantFiled: June 28, 2002Date of Patent: August 19, 2003Assignee: Broadcom CorporationInventor: Janardhanan S. Ajit
-
Patent number: 6603684Abstract: A semiconductor memory device is provided, which includes a chip enable buffer and an address buffer. The chip enable buffer generates first and second control signals having opposite phases of logic, the first and second control signals enable and disable operations of the semiconductor memory device, respectively. The address buffer includes an input terminal, and a blocking terminal connected to the input terminal, the input terminal receiving an external address signal under control of the first control signal, and the blocking terminal generating an address signal in response to the second control signal. The address buffer further includes a shift detecting circuit connected to the blocking terminal for generating first and second short pulses by detecting shift of the address signal, wherein the pluses are used as signals for reading data of the semiconductor memory device.Type: GrantFiled: April 18, 2002Date of Patent: August 5, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Heung-Soo Im
-
Patent number: 6603338Abstract: A substantially noise-free address input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates both a logical true and complement representation of an address input signal and includes timing circuitry to place the logical true and complement signals in the same deasserting logical state for a predetermined period of time prior to asserting either the logical true signal or the logical complement signal, in response to a signal edge transition appearing on the address input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the logical true and complement signals.Type: GrantFiled: October 30, 1998Date of Patent: August 5, 2003Assignee: STMicroelectronics, Inc.Inventor: David C. McClure
-
Patent number: 6597164Abstract: An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of switching circuits which selectably provide electrical connections between the respective circuits and the test bus. The plurality of switching circuits are configured to transfer an electrical charge between a node disposed within each switching circuit not selected to provide an electrical connection and a respective charge source or sink. The charge source or sink may consist of a low-impedance, substantially noise-free DC voltage or signal source.Type: GrantFiled: September 12, 2001Date of Patent: July 22, 2003Assignee: Broadcom CorporationInventor: Erlend Olson
-
Patent number: 6591319Abstract: In a processing system, a glitch protection circuit receives a strobe signal and a data receiver captures a data signal in response to an output from the glitch protection circuit. Several embodiments are disclosed. In a first embodiment, a glitch protection circuit generates an output that represents a logical multiplication of a strobe signal with a delayed version of itself. In another embodiment, a pair of glitch protection circuits each sense a strobe transition and become dormant until its partner senses a strobe transition. The pair operates in a toggling fashion.Type: GrantFiled: October 31, 2002Date of Patent: July 8, 2003Assignee: Intel CorporationInventors: Nasser A. Kurd, Robert J. Greiner
-
Patent number: 6573752Abstract: A new high voltage, high side driver circuit has been achieved. The circuit comprises, first, a top PFET having gate, drain, source, and bulk. The gate is coupled to a switching signal. The source is coupled to a high voltage. Second, a top resistor has first and second terminals. The first terminal is coupled to the high voltage. Third, a middle PFET cell comprises a middle PFET having gate, drain, source, and bulk. The source is coupled to the top PFET drain. The gate is coupled to the top resistor second terminal. A middle resistor has first and second terminals. The first terminal is coupled to the middle PFET gate. Finally, a middle means of claimping the middle PFET gate and a clamping voltage completes the middle PFET cell. Fourth, a bottom PFET cell comprises, first, a bottom PFET having gate, drain, source, and bulk. The gate is coupled to the middle resistor second terminal, the source is coupled to the middle PFET drain, and the drain forms a high side driver output.Type: GrantFiled: January 10, 2002Date of Patent: June 3, 2003Assignee: Dialog Semiconductor GmbHInventor: Dirk Killat
-
Patent number: 6552595Abstract: In a programmable integrated circuit, a discharge circuit for discharging high voltage nodes provides a current path whose current is limited by a control voltage. In one embodiment, the current path is implemented by a transistor coupled to the high voltage nodes, with the control voltage provided by a current mirror coupled to the current path. The control voltage is applied across the gate and source terminals of the transistor. In one embodiment, the source terminal of the transistor is precharged to a supply voltage less a threshold voltage of a transistor. With the current in the current path thus limited, threshold voltage shifts and other damages to the functional circuit of the integrated circuit due to the discharge current of high voltage nodes are avoided.Type: GrantFiled: May 26, 1999Date of Patent: April 22, 2003Assignee: Lattice Semiconductor CorporationInventor: Benny Ma
-
Patent number: 6552571Abstract: A circuit for reducing the noise associated with a clock signal for a latch based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a predetermined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.Type: GrantFiled: July 31, 2001Date of Patent: April 22, 2003Assignee: Sun Microsystems, Inc.Inventors: Brian W. Amick, Claude R. Gauthier
-
Patent number: 6549030Abstract: A method for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.Type: GrantFiled: July 31, 2001Date of Patent: April 15, 2003Assignee: Sun Microsystems, Inc.Inventors: Brian W. Amick, Claude R. Gauthier
-
Patent number: 6542012Abstract: Disclosed is a circuit for driving a gate of an IGBT (insulated gate bipolar transistor) inverter. The present invention includes a first IGBT of which collector is connected to a DC voltage, a second IGBT of which collector is connected to an emitter of the first IGBT, wherein an output signal is outputted from a connection point between the collector of the second IGBT and the emitter of the first IGBT, and of which emitter is connected to a ground, first and second driving circuits supplying gates and the emitters of the first and second IGBTs with DC driving voltages, respectively, through first and second gate resistors, and first and second noise interruption circuits connected between the gates-emitters of the first and second IGBTs and the first and second driving circuits, respectively, so as to interrupt noises.Type: GrantFiled: November 14, 2001Date of Patent: April 1, 2003Assignee: LG Industrial Systems Co., Ltd.Inventor: Min Keuk Kim
-
Patent number: 6535057Abstract: A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is-connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.Type: GrantFiled: May 24, 2001Date of Patent: March 18, 2003Assignee: STMicroelectronics Ltd.Inventor: Kalyana Chakravarthy
-
Patent number: 6535039Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.Type: GrantFiled: August 6, 2001Date of Patent: March 18, 2003Assignee: Fujitsu LimitedInventors: Hiromi Nanba, Tohru Mizutani, Makoto Ikeshita, Masato Takeyabu
-
Patent number: 6525589Abstract: An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.Type: GrantFiled: October 25, 2000Date of Patent: February 25, 2003Assignee: Cirrus Logic, Inc.Inventors: Axel Thomsen, Edwin De Angel, Sherry Wu, Aryesh Amar, Jerome E. Johnston
-
Patent number: 6522179Abstract: A differential line driver circuit having an output impedance matched to the line impedance includes first and second input terminals for the application of an input signal, a fully differential operational amplifier having inverting and non-inverting signal inputs connected to first and second input terminals respectively, first and second signal outputs providing in-phase and quadrature amplified output signals, and gain adjusting impedances connected between the input terminals and the amplifier's signal inputs. First and second feedback impedances connect between inverting and non-inverting signal inputs of the amplifier and its first and second signal outputs. First and second matching impedances connect first and second amplifier outputs to corresponding output terminals of the line-driver circuit. First and second positive-feedback impedances connect the first and second output terminals of the line driver circuit to the non-inverting and inverting inputs of the amplifier.Type: GrantFiled: September 14, 2001Date of Patent: February 18, 2003Assignee: Infineon, AGInventor: Thomas Ferianz
-
Publication number: 20030020530Abstract: A system and method to overcome or nullify a charge injection and clock feed-through error voltage caused by the turning-off charge of a switched element(s) in switched networks. A circuit for nulling a charge injection and clock feed-through error voltage includes, for example, two switched elements and a capacitor. The circuit can be used to replace any switch element in a switched network. The circuit may also include, for example, three switched elements and two capacitors.Type: ApplicationFiled: July 27, 2001Publication date: January 30, 2003Inventors: Wing Foon Lee, Pak Kwong Chan
-
Patent number: 6507219Abstract: A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.Type: GrantFiled: September 21, 2001Date of Patent: January 14, 2003Assignee: Intel CorporationInventors: Sanjay Dabral, Ming Zeng, Subramaniam Maiyuran
-
Patent number: 6505262Abstract: In a processing system, a glitch protection circuit receives a strobe signal and a data receiver captures a data signal in response to an output from the glitch protection circuit. Several embodiments are disclosed. In a first embodiment, a glitch protection circuit generates an output that represents a logical multiplication of a strobe signal with a delayed version of itself. In another embodiment, a pair of glitch protection circuits each sense a strobe transition and become dormant until its partner senses a strobe transition. The pair operates in a toggling fashion.Type: GrantFiled: November 30, 1999Date of Patent: January 7, 2003Assignee: Intel CorporationInventors: Nasser A. Kurd, Robert J. Greiner
-
Patent number: 6489829Abstract: Circuits and methods to turn-on a power MOSFET switch while limiting rush current delivered to a load are disclosed. In an exemplary embodiment, a sense circuit senses when the power MOSFET is enhanced by a first level and a second level. A control circuit controls application of three drive forces to the gate of the power MOSFET in response to the sense circuit. The first drive force adjusts the voltage applied to the gate at a first rate. The second drive force adjusts the voltage applied to the gate at a second rate less than the first rate. The third drive force adjusts the voltage applied to the gate at a third rate greater than the second rate. The circuit utilizes most of the allotted turn-on time to linearly control the power MOSFET enhancement, providing optimal slew rate control and limiting the rush current delivered to the load.Type: GrantFiled: April 12, 2001Date of Patent: December 3, 2002Assignee: Advanced Analogic Technologies, Inc.Inventor: Tim Wen Hui Yu
-
Patent number: 6462588Abstract: A circuit for controlling signal levels on a transmission channel includes a comparator having a reference voltage input and a current control voltage input. A voltage divider is coupled to the current control voltage input of the comparator. The voltage divider includes multiple loads to divide voltages associated with a first output driver and a second output driver. The voltage divider also includes multiple switches to activate and deactivate loads in the voltage divider. A current control circuit is coupled to an output of the comparator. The current control circuit controls signal levels on the transmission channel in response to an output signal received from the comparator. Another circuit for controlling signal levels on a transmission channel includes a comparator that has a reference voltage input, a current control voltage input, and an offset control input. The offset control input is used to adjust the voltage offset on the transmission channel.Type: GrantFiled: April 3, 2000Date of Patent: October 8, 2002Assignee: Rambus, Inc.Inventors: Benedict Chung-Kwong Lau, Huy M. Nguyen
-
Patent number: 6462604Abstract: A circuit for reducing the noise associated with a clock signal for a flip-flop based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal.Type: GrantFiled: May 2, 2001Date of Patent: October 8, 2002Assignee: Sun Microsystems, Inc.Inventors: Brian W. Amick, Claude R. Gauthier
-
Patent number: 6459324Abstract: An active resistance is controlled to modify a drive signal provided to a gated device such as an insulated gate bipolar transistor (IGBT). The active resistance is between an input lead that receives an input drive signal, such as from a conventional gate driver IC, and an output lead at which an output drive signal is provided to the device's gate. The active resistance is controlled in response to a feedback signal that includes information about the output drive signal, so that the output drive signal is a modified version of the input drive signal. To reduce di/dt and hence control EMI emission, the output drive signal can include turn-on and turn-off transitions where the input drive signal includes steps.Type: GrantFiled: October 23, 2001Date of Patent: October 1, 2002Assignee: International Rectifier CorporationInventors: Dorin O. Neacsu, Hoa Huu Nguyen
-
Patent number: 6452442Abstract: A noise immunity circuit has a distributed electrical plane to which noise susceptible components are coupled. Also, in a close proximity are noise generating circuits that generate electrical noise onto the distributed electrical plane that affect the noise susceptible components. A coupling means is used to couple the noise susceptible circuits to the distributed electrical plane so that the noise of the distributed electrical plane is common to all points in the noise susceptible circuit. Also, inputs and power to the circuit are coupled to the distributed electrical plane so that the common noise is imposed upon them. Coupling preferably takes place through a variety of capacitors and resistors so that high frequency noise is coupled to the noise susceptible circuit.Type: GrantFiled: December 4, 1995Date of Patent: September 17, 2002Assignee: Intel CorporationInventor: David P. Laude
-
Patent number: 6448837Abstract: A shunt and shunt control circuit are connected to the wires of an on-chip terminated I/O bus. Each instance monitors the wire that it is connected to. If the wire has been pulled low by any device on the bus, the circuit does nothing. If, however, the wire was not pulled low, then current is shunted from the termination voltage supply to ground. The turn on and turn off rates for this shunt are matched to the ramps of current through the termination impedance of the bus. This makes the variability in current drawn from the termination voltage supply less data dependent.Type: GrantFiled: January 4, 2001Date of Patent: September 10, 2002Assignee: Hewlett-Packard CompanyInventor: Samuel D. Naffziger
-
Patent number: 6441682Abstract: The invention is an improved implementation of an active-RC polyphase band-pass filter with transconductor cross-coupling between filter sections. The polyphase filter has first to fourth inputs, first to fourth outputs, two filter sections, and a block of transconductor pairs. The four input signals to the polyphase filter succeed one another in phase by 90 degrees. The two filter sections have reactances comprised of active balanced operational amplifiers with matched capacitors in their feedback loops. The block of transconductor pairs is coupled between corresponding reactances of each filter. The transconductance of each transconductor pair is set as the product of a desired radian center frequency and the capacitance of the corresponding matched capacitors. In the preferred embodiment, the transconductors are Gm cells and the transconductance of at least one Gm cell is field adjustable.Type: GrantFiled: November 22, 2000Date of Patent: August 27, 2002Assignee: Micro Linear CorporationInventors: Charles Vinn, Gwilym Luff, Carlos Laber
-
Patent number: 6433600Abstract: A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle).Type: GrantFiled: December 1, 1999Date of Patent: August 13, 2002Assignee: Intel CorporationInventor: Alper Ilkbahar
-
Patent number: 6429722Abstract: A method of reducing the noise of a clock signal distribution system for a flip-flop based circuit has been develop. The method first inputs a synchronized clock signal into a noise reduction circuit. The noise reduction circuit then begins to store charge upon receipt of the clock signal. Finally, the noise reduction circuit dumps the charge onto the system power grid at an appropriate time in conjunction with the clock signal.Type: GrantFiled: May 1, 2001Date of Patent: August 6, 2002Assignee: Sun Microsystems, Inc.Inventors: Brian W. Amick, Claude R. Gauthier
-
Patent number: 6429703Abstract: An output circuit applied in the double data rate (DDR) system for generating sampling clocks. Assume that the sampling clocks are initially set as a first logic level. The output circuit comprises an output transistor unit for outputting the sampling clock and a pre-pulling unit that connects to an output terminal of the output transistor unit and a second logic level and receives a control signal. The control signal has a pulse before the first time the sampling clock changes from the initial first logic level at the output terminal of the output transistor unit. This pulse can be used to control the pre-pulling unit, so that the output terminal of the output circuit shifts a voltage difference in advance from the first logic level toward the second logic level, thereby preventing initial oscillation of the sampling clock and maintaining the completeness of the data.Type: GrantFiled: March 13, 2001Date of Patent: August 6, 2002Assignee: Via Technologies, Inc.Inventor: Chi Chang
-
Patent number: 6429701Abstract: In the initial stage of the operation of turning off a semiconductor device, the impedance of a carrier pull out circuit remains low for rapidly pulling out the stored carriers from the control electrode of the device. When the turn-off transition of the device proceeds and becomes close to its completion, the impedance of the carrier pull out circuit is shifted to a higher level for retarding the carrier pull out speed. A detector is provided for detecting a control current developed by pulling out the carriers. When the current measured by the detector drops down to below a predetermined level, it is judged that the turn-off transition is approaching to its end. This permits the turn-off transition to be smoothly finished and can thus prevent unwanted oscillation of the control electrode voltage.Type: GrantFiled: December 26, 2000Date of Patent: August 6, 2002Assignee: Nissan Motor Co., Ltd.Inventors: Toshiro Karaki, Kraisorn Throngnumchai
-
Patent number: 6407612Abstract: An input signal latching circuit for suppressing the effect of any ringing or other irregularities that occur within a specified time period after a transitional voltage level is reached, without significantly delaying the propagation of the input signal.Type: GrantFiled: October 30, 2000Date of Patent: June 18, 2002Assignee: Xilinx, Inc.Inventor: Peter H. Alfke
-
Patent number: 6407608Abstract: A clock buffer circuit (100) for generating buffered clock signals (CLKI and CLKI_) in response to an external clock signal (CLKX) is disclosed. A first buffer section (102) drives to a first output node (114) between high and low logic levels in reponse the CLKX signal. To reverse the adverse effects of noise on the falling edges of CLKX signal, a boost section (108) and clock generator (106) are provided. In response to low-to-high transitions at the first output node (114) the pulse generator (106) generates a pulse at a pulse output (126). In response to the pulse, the boost section (108) provides additional driving capability for further pulling the first output node (114) to the high logic level. The first output node provides the CLKI_ signal. A second buffer circuit (104) provides the CLKI signal in response to the CLKI_ signal. An enabling section (110) is provided for enabling, or alternatively, disabling the preferred embodiment (100).Type: GrantFiled: March 18, 1999Date of Patent: June 18, 2002Assignee: Texas Instruments IncorporatedInventors: Jason M. Brown, Steven C. Eplett
-
Patent number: 6391667Abstract: A power supply unit which supplies voltage to electric components, includes: a DC power supply (40) which supplies DC voltage to the electric components; at least one capacitor (C1), provided between the DC power supply (40) and the electric components, which charges the DC voltage; an input switch (SW1a) which connects or disconnects the capacitor (C1) and the DC power supply (40); and an output switch (SW1b) which connects or disconnects the capacitor (C1) and the electric components (semiconductor device under test); and a switching control unit (60) which charges the capacitor (C1) and supplies the DC voltage charged in the capacitor (C1) to the electric components. Thereby, the DC voltage to be supplied to the electric components or semiconductor device under test can be temporarily switched to low-noise DC voltage supplied from the charged-up capacitor (C1) during the test.Type: GrantFiled: April 3, 2000Date of Patent: May 21, 2002Assignee: Advantest CorporationInventor: Yoshihiro Hashimoto
-
Patent number: 6389086Abstract: A digital circuit has a signal input terminal and a signal output terminal. The digital circuit additionally has a logic circuit unit, whose input is connected to the signal input terminal and whose output is connected to the signal output terminal via a switching element. Furthermore, it has a filter unit, whose input is connected to the signal input terminal and whose output is connected to a control input of the switching element. The filter unit serves for suppressing glitches on a digital signal present at its input.Type: GrantFiled: March 8, 2000Date of Patent: May 14, 2002Assignee: Infineon Technologies AGInventors: Thoai-Thai Le, Eckhard Brass, Markus Biebl
-
Patent number: 6384661Abstract: A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bimodal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit circuit. A fifth section is used for logic testing the driver circuit.Type: GrantFiled: May 30, 2000Date of Patent: May 7, 2002Assignee: International Business Machines CorporationInventor: Robert R. Livolsi
-
Patent number: 6384668Abstract: The present invention provides a charge pump circuit capable of operating at a high speed with a low power source voltage and increasing the synchronization processing speed. The charge pump circuit comprises: a first switch circuit 15 connected between a first input node 12 through which a first signal CPin1 is input and a base of an NPN transistor Q4, for controlling the NPN transistor Q4 in response to the first signal CPin1; and a second switch circuit 16 connected between a second input node 13 and a base of an NPN transistor Q9, for controlling the NPN transistor Q9 in response to a second signal CPin2. The transistors Q4 and Q9, and transistors contained in the first and the second switch circuits 15 and 16 are all NPN transistors.Type: GrantFiled: January 28, 2000Date of Patent: May 7, 2002Assignee: NEC CorporationInventor: Hidehiko Kuroda
-
Patent number: 6380767Abstract: A connection control circuit is provided to guarantee a high quality of port-to-port connection service by enabling to maintain the suspended state even when a disparity exists in the pulse widths of the envelope signals of the tone signals between the sender and receiver, exemplified by a receiver tone pulse width being wider than a sender tone pulse width. Connection control is achieved by providing a signal correction circuit between the receiver circuit of a port that receives incoming signals from an opposing port through a transmission line and a connection state managing machine that manages connection between the ports. The signal correction circuit corrects the tone pulse width of an envelope-signal generated from the incoming tone signal by broadening the pulse width so as to conform to a tone signal having the pulse width specified by own connection state managing machine.Type: GrantFiled: October 26, 2000Date of Patent: April 30, 2002Assignee: NEC CorporationInventors: Takayuki Nyu, Kohichiro Suzuki
-
Patent number: RE38213Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.Type: GrantFiled: August 3, 2001Date of Patent: August 12, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Masakazu Hirose