Abstract: A multi-function output driver that may be used with at least two types of busses includes a multiplexer that shifts calibration bits to the pull-down transistors. This shifting changes which transistors of the transistor array are turned on when the pull-down drive transistors are driving. By changing which transistors are turned on, the impedance of the driver is changed. This shifting is used with a disable function on the pull-up drive-transistors to allow the driver to be used as an end-of-line termination, an open-drain driver, or as a source-terminated driver.

Abstract: Circuitry and methods are provided for reducing rise time associated with signals on an open-drain or open-collector signal line. Signal line voltage is monitored to determine if the signal line is being pulled LOW. If the signal line is not being pulled LOW, as indicated by signal line voltage exceeding a threshold level, additional pullup current is provided. The additional current may be provided gradually in relation to the signal line voltage, or may be provided in full whenever voltage exceeds the threshold. Circuitry may also be provided to monitor voltage slew rate on the signal line, and to enable the additional pullup current only when the slew rate exceeds a positive threshold level.

Abstract: A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.

Abstract: A bus driver circuit has floating gate circuits with three transistors. Two of the transistors for an inverter for operating the output power transistor. The third transistor is connected to receive control signals from well pull circuits. The control signal keeps the third transistor off when the bus driver circuit is not enabled.

Abstract: A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle).

Abstract: Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines and function as a filter. As a result, noise generated by operation of internal circuit is absorbed in propagating to stabilize circuit through first internal power supply line, pad, and second internal power supply line. Therefore, effects of noise given to stabilize circuit is small.

Abstract: When a tuning mode signal VTUNE is activated, control clock signal TCLK is output, and counter counts up tuning signals TSIG1 to TSIG4. Tuning circuits render conductive the terminals of respective transistors, and reference potential Vref lowers in accordance with the reduction in the resistance value. When reference potential Vref attains equal to the external reference potential Ext.Vref, differential amplifier circuit stops output of the control clock signal TCLK In accordance with the plurality of the determined tuning signals TSIG1 to TSIG4, fuse elements inside the tuning circuits are programmed.

Abstract: A transient current producing method, a transient producing circuit, a related semiconductor integrated circuit and logical circuit are provided, which are capable of preventing a flow of a steady state current, consuming little power and switching at high speed. A transient current occurring at a time of switching of a CMOS circuit is amplified to a predetermined value. This amplification prevents the flow of the steady state current in the circuit. The transient current occurring at the time of switching of the CMOS circuit is converted to a transient voltage. The conversion of the transient current to the transient voltage having a predetermined value and the amplification of the transient current allow a simple configuration of the circuit. The transient current is a feedthrough current which flows from a terminal of a power supply to a ground at the time of switching of the CMOS circuit.

Abstract: A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.

Abstract: A power switching circuit with reduced interference radiation includes at least one pair of low-side and high-side MOS power transistors, between which a load resistor is connected. One or at least one of the low-side MOS power transistors is connected to a drive circuit having a divider for dividing a difference between a maximum output voltage of the MOS power transistor and an instantaneous output voltage at the load resistor as a dividend, by a maximum output voltage of the MOS power transistor as a divisor, and a level converter for generating a drive voltage for the MOS power transistor. The drive voltage is proportional to the quotient.

Abstract: A buffer using a dynamic threshold-value MOS transistor reduces its power consumption. Since transmitted to an output signal (S3) with some delay, transition of the input signal (S1) from low to high, for example, is also transmitted to a body of a transistor (N1) for a while. This increases the body potential to reduce the threshold value, thereby shortening time required to turn on the transistor (N1). After that, the output signal (S1) becomes completely high to turn off a transistor (P2), which stops the transmission of the input signal (S1) to the body of the transistor (N1). At the same time, a transistor (N2) is turned on, so that the body potential of the transistor (N1) is grounded to be completely low. Thus, the threshold voltage is increased again. This prevents a current flow from body to source in the transistor (N1), thereby reducing power consumption.

Abstract: A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.

Abstract: A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output signal for a predetermined period of time in response to a signal edge transition appearing on the data input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the data output signal.

Abstract: The present invention relates to an output buffer circuit for transmitting digital signals over a transmission line with pre-emphase. It comprises an output stage and a control circuit. The output stage includes a first impedance circuit connected between an upper power supply potential and an output node. It furthermore includes a second impedance circuit connected between the output node and a power supply node at a lower supply potential. Both impedance circuits receive impedance control signals from the control circuit such that an impedance ratio between the first impedance and the second impedance takes one of at least three different predetermined values in accordance with the present state and the history of a digital data input signal, and such that the sum of the conductance provided by the first impedance circuit and the conductance provided by the second impedance circuit is independent from the generated impedance ratios.

Abstract: A controlled stochastic resonance circuit applies stochastic resonance to bias a nonlinear device with a control signal having a selected amplitude, frequency, and phase to enhance or suppress the response of the device to a periodic signal embedded in noise.

Abstract: An output driver circuit (10) includes a voltage follower (36) having an input coupled for receiving a reference signal (VREF1) and an output for providing an output signal (VOUT). The output driver circuit (10) further includes an amplifier (28) that compares the voltages of the reference (VREF1) and output (VOUT) signals to generate a compare signal for enabling a conduction path (37). The conduction path (37) alters the voltage of the output signal (VOUT) so that the transition time of the output signal (VOUT) is substantially equal to the transition time of the reference signal (VREF1).

Abstract: There is disclosed an electronic circuit comprising a clock driver for generating a clock signal, a clock line on which the clock signal generated by said clock driver is transmitted, a shield-cum-signal line extending along said clock line serving optionally for transmission of a predetermined signal and for shielding of a noise generated from said clock line in accordance with a mode, a transfer gate for transferring a transmitted signal to said shield-cum-signal line, said transfer gate turning on or off in accordance with a mode, and a transistor disposed between said shield-cum-signal line and a power source, said transistor turning on when said transfer gate turns off and turning off when said transfer gate turns on in accordance with a mode.

Abstract: An output buffer circuit has a CMOS output circuit constituted by a p-channel MOS transistor and an n-channel MOS transistor. A combination circuit is provided between an input terminal of the output buffer circuit and the CMOS output circuit. This combination circuit temporarily decreases a signal output to a gate input terminal of the CMOS output circuit when the signal rises from a relatively low first potential level (“L” level) to a relatively high second potential level (“H” level) and temporarily raises the signal when the signal falls from the relatively high second potential level to the relatively low first potential level. Therefore, overshoot, undershoot, and ringing of an output signal can be prevented.

Abstract: An emitter follower circuit with feed forward compensation includes an emitter follower having an emitter follower input and an emitter follower output. An auxiliary emitter follower has an auxiliary emitter follower input and an auxiliary emitter follower output. The emitter follower input is coupled to the auxiliary emitter follower input and the emitter follower output is capacitively coupled to the auxiliary emitter follower output. In this manner, ringing of the emitter follower circuit with feed forward compensation is reduced by the capacitive coupling of the auxiliary emitter follower output to the emitter follower output.

Abstract: A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.

Abstract: When a short-circuit transistor is switched on, an impedance of an emitter-collector path through a switching transistor in a driver stage becomes higher as a load current becomes greater, and the load current and power loss in the switching transistor thus become lower. This effect is increased by connecting a voltage divider in parallel with the emitter-collector path through the switching transistor, by a parallel transistor. When the switching transistor is switched off, the parallel transistor blocks the current path via the voltage divider and the load for undesirable residual currents.

Abstract: An apparatus for eliminating noise is disclosed. The present invention includes a counter, which counts in a first direction when an input signal is active, and in a second direction otherwise. A determining device is used to determine a predetermined first threshold value, and assert an output signal while such value is reached. The present invention also includes a limiting device, which prevents the counter from counting beyond or below a predetermined limit value.

Abstract: A deceleration circuit is operatively coupled to a first and second voltage to reduce noise on each of the voltage lines. For example, one voltage may be a supply voltage and the other voltage may be at a ground potential. The deceleration circuit may be coupled, for example, to each circuit that need not operate at a maximum or high operational speed within an integrated circuit that has other circuits that require high speed operation.

Abstract: After an output signal is inverted by an inverter circuit, the resultant signal is differentiated by a differentiating circuit. The connecting states of selectors are changed so that only when the signal level of the differentiated output exceeds a predetermined threshold value, the output signal is sent through a resistor. After the output signal is buffered by a buffering circuit, the resultant signal is differentiated by a differentiating circuit. The connecting states of selectors are changed so that only when the signal level of the differentiated output exceeds a predetermined threshold value, the output signal is sent through a resistor.

Abstract: The present invention is generally directed to a power control circuit for a line driver circuit in a central office. In a broad sense, the present invention operates to power-down line driver circuitry when it is not in use, and apply power to the line driver circuitry when transmissions are requested by a customer (e.g., customer premises). This reduces the power consumption of the line driver by eliminating the quiescent current draw when the line driver is idle. Recognizing that the typical line driver is in an idle state the vast majority of the time, compounded by the vast number of line drivers that exist within a central office environment, it will be appreciated that the overall power savings may be tremendous. In accordance with one aspect of the invention a circuit is provided for controllably applying power to a line driver.

Abstract: An integrated circuit having an apparatus for automatically adjusting noise immunity is disclosed. The integrated circuit includes multiple functional logic circuits, a clock generator, a group of noise monitor circuits, and a control logic circuit. The clock generator generates a clock signal to all these circuits. The noise monitor circuits are utilized to detect noise occurring in the integrated circuit. In response to any noise detected by the noise monitor circuits, the control logic circuit decreases the speed of the clock signal sent to all the circuits, especially the functional logic circuits, via a slow down signal to the clock generator. Alternatively, the control logic circuit can inform the functional logic circuits via a noise alert signal to increase the noise immunity of certain noise sensitive circuits within the functional logic circuits.

Abstract: A gating circuit for largely glitch-free gating of analog signal values obtained in a periodic sequence, capacitively buffer-stored, digitized by means of an A/D converter and subsequently erased before a next signal value is obtained in the capacitive buffer store. A first operational transconductance amplifier (OTA) capable of being activated by a gating pulse has a non-inverting input connected to the reference-earth point of a capacitive store and an output connected to the charging terminal of the capacitive store. Its inverting input is connected through an impedance converter and a resistor, which limits the discharge current, to the charging terminal of the capacitive store. A second OTA serves as a signal driver whose gain is predetermined by the ratio of the value of a resistor connected in parallel with the capacitive store to that of a series resistor that determines the potential at the inverting input of the second OTA.

Abstract: A digitally controlled signal attenuator circuit which allows an incoming DC-clamped signal to be selectively attenuated using a set of digital control signals while maintaining its DC clamping. Multiple stages of such a circuit can be cascaded to provide for multiple forms of signal attenuation without affecting the clamping. Preferred forms of the attenuator circuit use pass transistors and transmission gates as switches for selectively altering the resistance values of resistive circuits connected in shunt to and in series with the signal being attenuated. In the case of where the subject signal is a variable DC signal such a brightness control voltage, such circuit configurations also allow the output signal voltage range to include values which are more negative than the DC clamp voltage as well as more positive.

Abstract: An integrated device for a switching system is disclosed. The device includes control circuitry for generating at least one switching control signal, reference circuitry for generating at least one reference quantity, a using circuit for using the reference quantity, a circuit for storing the reference quantity, and a switch which, in a first operative condition, connects the reference circuit to the using circuit and to the storage circuit in order to apply the reference quantity thereto. In a second operative condition, the switch disconnects the reference circuit from the using circuit and connects the storage circuit to the using circuit in order to apply the stored reference quantity thereto. Finally, the device includes filtering circuitry for keeping the switch in the second operative condition for a filtering period in accordance with the switching of the control signal.

Abstract: An overshoot and damping control circuit for high speed L-R-C drivers. By properly configuring four transistors in conjunction with a high speed driver, negative feedback can be utilized to generate a spike of current to correct for overshoot which results when driving an inductive load with high speed signals. This same configuration also provides the additional benefit of providing a signal which dampens the ringing which results from driving an inductive load with a high speed signal.

Abstract: An apparatus comprising a charge pump configured to receive an input signal and to output incrementally a fixed amount of voltage for every selected edge of the input signal, an analog buffer coupled to said charge pump, the analog buffer feeding back a second voltage to said charge pump, the output of the charge pump linearly increases as a function of the fixed amount of voltage. A low power ramp generator that is created thereby may be used in analog to digital converters which are employed in devices such as imaging systems.

Abstract: A semiconductor integrated circuit device has an output circuit composed of a P-channel transistor whose source is connected to a terminal for receiving a supplied voltage and an N-channel transistor whose source is connected to a terminal for receiving a ground voltage, with the node between the drains of the two transistors used as the output terminal of the output circuit. A capacitive circuit element is connected between the sources of the two transistors, and thus in parallel with the output circuit, so as to suppress variations that occur in the current supplied from the supplied power as a result of a current being fed through the output circuit to or from a load connected to the output terminal. This helps keep constant the voltage that is supplied to an internal circuit that is connected in parallel with the output circuit, and thereby stabilize the operation of the internal circuit.

Abstract: The output control circuit includes: a first high side transistor 56 coupled to an output node 68; a second high side transistor 59 coupled in parallel with the first high side transistor 56; a first transmission gate 72 coupled between a control node of the first high side transistor 56 and a control node of the second high side transistor 59, the first transmission gate 72 is controlled by feedback from the output node 68; a first low side transistor 50 coupled to the output node 68; a second low side transistor 53 coupled in parallel with the first low side transistor 50; a second transmission gate 74 coupled between a control node of the first low side transistor 50 and a control node of the second low side transistor 53, the second transmission gate 74 is controlled by feedback from the output node 68.

Abstract: An embodiment of a ringback tolerant input buffer in a receiving device is disclosed. The input buffer includes circuitry to provide positive feedback to an input signal once the input signal has crossed a reference voltage threshold. The positive feedback prevents the input signal from recrossing the reference voltage threshold until the receiving device has sampled the input signal. The positive feedback is applied only until the input signal is sampled into the receiving device.

Abstract: An output driver circuit including a first path from an output pad to ground through a first switch, and a second path from the output pad to ground through series-connected second and third switches. The first switch is directly connected to a pull-down signal source, and one of the second and third switches is connected to the pull-down signal source through a one-shot circuit. In a pull-up state, the first and second switches are opened, and the one-shot circuit generates a stabilized output signal which closes the third switch. When the output driver circuit switches to a pull-down state, the first switch is closed, thereby connecting the output pad to ground via the first path. The signal change also closes the second switch. In addition, due to a propagation delay of the second signal through the one-shot circuit, the third switch initially remains closed, thereby also connecting the output pad to ground via the second path.

Abstract: In an output circuit including first and second power supply terminals, an input terminal, an output terminal, a first switching element connected between the first power supply terminal and the output terminal and being controlled by an input voltage at the input terminal, and a plurality of second switching elements connected in parallel between the output terminal and the second power supply terminal and being controlled by the input voltage, a third switching element is connected between the output terminal and one of the second switching elements, and a control circuit is rat provided for controlling the third switching element in accordance with an output voltage at the output terminal.

Abstract: Signal transfer devices enable multiple processors to act as drivers or receivers of signals which can transition from an invalid state to a valid state and then return to the invalid state in one clock cycle. The preferred signal transfer device includes a bus line, a plurality of bus drivers electrically connected to the bus line for initiating wired-OR signal transitions and at least one self-timed booster circuit electrically connected to the bus line. The self-timed booster circuit includes a first field effect transistor electrically connected in series between the bus line and a first reference potential and a second field effect transistor electrically connected in series between the bus line and a second reference potential. A timing circuit is also provided as a plurality of inverters which are electrically coupled in series. The timing circuit, which has an input electrically coupled to the bus line, performs a boolean inversion of the signals on the bus line after a first delay.

Abstract: A power switching device which decreases both surge voltage and switching loss. As the inductor is connected to the emitter electrode of the IGBT element, the potential of the emitter electrode changes in the direction in which the IGBT element maintains the ON state with the attenuation of the main current when the IGBT element turns OFF from ON. Furthermore, as the inductor is included in the path of the OFF driving current for bringing the IGBT element to OFF, the OFF driving current once raises and then decreases. As a result, because the transition from ON to OFF calmly proceeds, the occurrence of the surge voltage is suppressed. On the other hand, since the inductor is not included in the path of the ON driving current, the transition from OFF to ON of the IGBT element is rapidly made. Accordingly, the switching loss occurring in the transition period is decreased. The decrease in the surge voltage and the decrease in the switching loss are compatibly realized.

Abstract: A driver circuit for slope-controlled pulsed switching of a load having a MOS switching transistor switching the load and a control loop with an amplifier having an amplifier input coupled with a switch control pulse source, an amplifier output connected with the gate of the MOS switching transistor, and a feedback capacitor. The driver circuit also includes a switchable current mirror circuit with a current mirror transistor formed by the MOS switching transistor and a diode transistor wired as a current mirror diode, a connection point between the diode transistor and the gate of the MOS switching transistor being connected with the amplifier output. A timer circuit is supplied on the input side with the switch control pulses from the switch control pulse source, and switches the diode transistor into a conductive state for essentially the duration of each switch control pulse edge and otherwise into a nonconductive state.

Abstract: A driver circuit (12) having a reduced propagation delay is provided. The driver circuit (12) includes a first device (56) having an input and operable to switch a supply voltage to a load (14). A second device (54) having an output coupled to the input of the first device (56), operable to turn on the first device upon receipt of a first signal. A third device (66) having an output coupled to the input of the first device (56), operable to turn off the first device upon receipt of a second signal. A kick start circuit (30) coupled to the input for the first device (56), the input for the second device (54), and the input for the third device (66), operable to generate a threshold voltage on the first device (56), the second device (54), and the third device (66). The kick start circuit (30) operable to produce a threshold voltage that is just below the voltage in which the first device (56), the second device (54), and the third device (66) turn on, or conduct.

Abstract: A gate drive circuit for an isolated gate device, a method of driving the same and a switch-mode power supply employing the circuit or the method. In one embodiment, the circuit includes: (1) a capacitor, having a first terminal coupled to a source of drive voltage and a second terminal coupled to a gate of the isolated gate device, that stores a charge therein when the drive voltage maintains the isolated gate device in an "on" state and (2) a conductive path, leading from the first terminal to an output terminal of the isolated gate device and enabled when the isolated gate device is to be transitioned from the "on" state to an "off" state, that provides a negative off-bias voltage to the gate thereby to avoid spurious turn-on of the isolated gate device.

Abstract: Internal power supply voltages at predetermined voltage levels are produced on output nodes of an output circuit in accordance with internal voltages generated by first and second voltage generating circuits which in receive a reference voltage on their inputs having high impedances. Stabilizing capacitors are connected to internal power supply nodes of this output circuit. The internal power supply voltage depends on MOS transistors operating in a source follower mode. During operation of the output circuit, charging and discharging currents are driven through the stabilizing capacitors, and an output signal having a limited amplitude can be reliably generated to an output node.

Abstract: An output circuit which suppresses the occurrence of leakage current from the power supply of an external element to the power supply of an internal device, even if the power supply voltage of the external element is higher than the power supply voltage of the internal device. Even if a voltage (5V) from an external circuit etc. which is higher than a power supply terminal 6 voltage (3V) is input to the output terminal 8, due to the fact that a floating state N-well B1 at the substrate of PMOS transistors P12, P13 and P14 rises to around 5V, PMOS transistor P12 and PMOS transistor P13 are put into an OFF state. If PMOS transistor P12 and PMOS transistor P13 are in the OFF state, the (5V) voltage is applied to PMOS transistor P1 and there is no flow of leakage current to the power supply terminal 6 through the substrate of PMOS transistor P1.

Abstract: A D/A converter of a multibit type has improved performance by reducing dispersion of the electric currents of plural electric current sources as much as possible, in which the D/A converter has a constant electric current source (10) constructed by 2.sup.N (N=2, 3, - - - and here, N=16) constant electric current sources having constant electric current values equal to each other; selectors (7, 8) for selecting Di constant electric current sources according to input data Di {here, Di=0, 1, 2, 3, - - - , (2.sup.N -1)} having N-bits in input word length so as to use these 2.sup.N constant electric current sources one by one until a sum of values of one input data or continuous plural input data among these 2.sup.N constant electric current sources exceeds 2.sup.N ; and an electric current adding means (9) for adding each of the constant electric currents from the Di constant electric current sources selected by the selectors to each other.

Abstract: The present invention comprises positive/negative masking signals which are added to an electronic circuit where ring phenomena may happen during high speed transmission of digital data, so as to eliminate the ring effect, and data can be transferred smoothly. Since the present invention uses only digital electronic circuit to solve the ring effect of related signals, no matter how long the cable between different subsystems is, the ring effect can be masked automatically. The problem of impedance matching is not necessarily considered, so the present invention is very valuable.

Abstract: An output buffer is provided in which the output impedance of the buffer is set relatively low during an initial portion of an output transition. Subsequently, near the end of the output transition, the output impedance of the buffer is increased to more closely follow the characteristic impedance of a transmission line driven by the buffer. The output impedance is automatically changed when the buffer output voltage crosses a predetermined threshold. The output buffer includes a voltage threshold detection circuit comprising a diode and a transistor, the diode being coupled to the gate of the transistor. When a voltage level of a signal applied to one of the diode and the transistor crosses a predetermined threshold, a switch state of the diode and/or transistor changes to thereby change an output of the voltage detection circuit and trigger the change of output impedance of the output buffer in a reliable and consistent manner.

Abstract: An electronic relay for use with an ultrasonic transducer. The electronic relay selectively couples the ultrasonic transducer to an electronic circuit. The transducer includes an input/output port for receiving excitation signals from the circuit and for transmitting echo signals back to the circuit. The electronic relay comprises a solid state switch and a leakage control circuit. The solid state switch is connected between the transducer and the electronic circuit. The switch is responsive to an actuation signal from the circuit for opening and closing the switch. The leakage control circuit is coupled to the switch and functions to control leakage current when the switch is open so as to electrically isolate the transducer from the electronic control circuit.

Abstract: A receiver circuit for an integrated circuit including an input buffer having an input coupled to receive an external input signal and an output coupled to generate a buffered input signal in response to the external input signal. The input buffer is selectively enabled by a control signal. A latch is coupled to receive the buffered input signal and to generate a latched output signal. A delay circuit is coupled to receive the latched output signal and to generate a delayed signal. A comparator is coupled to receive both the latched output signal and the delayed signal. The comparator has an output coupled to the input buffer to generate the control signal.

Abstract: A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle).

Abstract: An Off Chip Driver (OCD) having a high, a low and a high impedance (Hi-Z) state. The OCD includes an up-level pre-drive, a down-level pre-drive and a driver. The driver mirrors current in the up-level pre-drive and down-level pre-drive. Both pre-drive circuits have an unbalanced input-dependant delay to quickly turn off/on the on and off driver devices and, after a delay, reduce the drive on the turned on device to a steady state level. The delay may have a fixed length set by an inverter chain or may be dependent upon output voltage.