Abstract: An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generates N phase comparison target clocks by using predetermined N frequency-divided clocks among the N+2 frequency-divided clocks; a phase comparison reference clock generation circuit that generates N reference clocks by using the N+2 frequency-divided clocks, in accordance with predetermined combinations between the N+2 frequency-divided clocks and an operation criterion; and a phase comparison circuit that detects respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks.

Abstract: In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.

Abstract: A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.

Abstract: Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.

Abstract: Accelerometers have a number of wide-ranging uses, and it is desirable to both increase their accuracy while decreasing size. Here, millimeter or sub-millimeter wavelength accelerometers are provided which has the advantage of having the high accuracy of an optical accelerometer, while being compact. Additionally, because millimeter or sub-millimeter wavelength signals are employed, cumbersome and awkward on-chip optical devices and bulky optical mediums can be avoided.

Abstract: Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.

Abstract: A control indication assembly. A first control mounted on a surface of a computer is coupled to a first sensor, to a first sensing circuit to send an electrical signal to the first control when a user-touch occurs to the first sensor, and to a first indicator to indicate an occurrence of said user-touch. A second control mounted on a surface of a display which is coupled to the computer is coupled to a second sensor, to a second sensing circuit to send an electrical signal to said second control when said user-touch occurs to the display, and to a second indicator to indicate an occurrence of the user-touch. The first and second control are configured such that the first and second indicator are synchronized to exhibit identical behaviors when the user-touch occurs to either the first control or the second control.

Abstract: At least one of a scanning-line drive part and a data-line drive part includes: a shift register for outputting transfer signals in sequence; a first enable supply line for supplying a plurality of series of first enable signals having a first pulse width smaller than that of the transfer signals; a second enable supply line for supplying one series of second enable signal having a second pulse width smaller than the first pulse width; and pulse-width restricting circuits for receiving input of the transfer signals, the first and the second enable signals. The pulse-width restricting circuits restricts the pulse width of the transfer signals to the first pulse width by shaping each pulse of the input transfer signals based on the individual first enable signals, and restricts the pulse width of the transfer signals to the second pulse width by shaping all the pulses of the transfer signals after restricted to the first pulse width based on the second enable signal.

Abstract: A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power than conventional comparator circuits having binary adders. For some embodiments, the comparator circuit is capable of performing full comparison operations on two or more arbitrary binary values. The comparator circuit can be implemented in TCAM devices to perform regular expression search operations.

Abstract: A semiconductor integrated circuit comprises: a first signal delay circuit including a first precharge element configured to precharge a first node with a leakage current and a first signal output circuit configured to output a first signal; a second signal delay circuit including a second precharge element configured to precharge a second node with a leakage current and a second signal output circuit configured to output a second signal. The first signal delay circuit is configured to discharge the first node via a first discharge element, while the second signal delay circuit precharges the second node via the second precharge element and outputs the second signal. The second signal delay circuit is configured to discharge the second node via a second discharge element, while the first signal delay circuit precharges the first node via the first precharge element and outputs the first signal.

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal.

Abstract: A phase-locked loop frequency synthesizer including phase detector circuitry and divider circuitry producing a divided signal. The phase detector circuitry receives a reference signal, a divided signal fed back from the divider circuitry, and generates control pulses which control a charge pump in accordance with a frequency and phase relationship between the reference signal and the divided signal. The divider circuitry has a main divider which divides an input signal by a division ratio selected from a pair of dual modules division ratios, and outputs the divided input signal as an output signal and an auxiliary divider which produces serial output data, each bit of which serves as a dual modules selection signal to cause the main divider to operate using one of the pair of dual modules main division ratios. The auxiliary divider produces the divided signal once per cycle and outputs the pulse to the phase detector circuitry.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the first reset path. The phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the second reset path.

Abstract: A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.

Abstract: A method and circuit for static phase error measurement includes a reference clock delay chain having a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a reference clock signal. A feedback signal delay chain also has a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a feedback signal. A latch tests phase alignment between the delayed reference clock signal and the delayed feedback signal and outputs a measurement of static phase error.

Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Abstract: A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase difference between the input clocks; and a counter unit which samples a level of the phase difference signal using a reference clock having a second frequency which is slower than the first frequency, and counts the number of levels of the phase difference signal using a first weighting according to the sampled level of the phase difference signal. When the count value of the counter unit transits in a predetermined range, the phase difference between the input clocks is detected according to the first weighting.

Abstract: A phase detection module includes a phase detection unit, a plurality of comparators and a decision unit. The phase detection unit is utilized for comparing a first input signal and a second signal to generate a phase detection result. The plurality of comparators is utilized for comparing the phase detection result with a plurality of predetermined voltages to generate a plurality of comparing results, respectively. The decision unit is utilized for deciding a phase relationship between the first and second input signals according to the plurality of comparing results.

Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.

Abstract: A method of synchronization of a digital circuit includes selecting a first site and a second site from a plurality of different sites of the digital circuit where a signal to be synchronized occurs; passing a first signal, which is the signal to be synchronized of the first site, via a first line that starts at the first site, ends at the second site, and contacts each of the sites just once, to the second site; passing a second signal, which is the signal to be synchronized of the second site, via a second line that starts at the second site, ends at the first site, and contacts each of the sites just once, to the first site; determining, for each site, a first phase shift between the signal to be synchronized of this site and the first signal, and a second phase shift between the signal to be synchronized of this site and the second signal; and determining, from the first and second phase shifts of each site, a delay for each site, with which the signal to be synchronized of the respective site is delayed

Abstract: A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.

Abstract: Suppressing one or more frequency ranges of a signal prevents the occurrence of feedback in a voice data communications application. A system recognizes a frequency range in a signal where feedback occurs, or anticipates a frequency range where feedback is anticipated. The signal includes a signal the input system generates or that the output system renders. The system suppresses the signal in the frequency range by disregarding one or more sampling bits representing the frequency range, or by applying one or more filters to attenuate or eliminate the signal in the frequency range. The system may monitor the signal to identify feedback resulting in different or additional frequency ranges and suppress the signal in the different or additional frequency ranges to prevent feedback from occurring.

Abstract: Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal.

Abstract: Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, samples the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and generates one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal and applying the error signal to an oscillator to produce the clock signal.

Abstract: A phase frequency detector comprising a detection circuit and a reset circuit. The phase frequency detector may receive a feedback signal having a predetermined pulse width. The detection circuit may generate a first control signal based on a reference signal, and a second control signal based on the feedback signal. The reset circuit may generate a reset signal used for resetting the detection circuit based on the first control signal, the second control signal, and the feedback signal. The feedback signal may be tied to the generation of the reset signal such that, during a locked state, the pulse width of the second control signal is approximately equal to the pulse width of the feedback signal, which helps reduce the sensitivity of the circuit to nonlinearities.

Abstract: A bus receiver receives at least one first signal and a second signal both generated from a chip connected to a parallel bus. The bus receiver includes a receiving module and a deskewing module. The receiving module is electrically connected to the parallel bus and receives the first signal and the second signal transmitted through the parallel bus. The deskewing module is electrically connected to the receiving module and deskews the phase of the first signal and the phase of the second signal. The first signal and the second signal are in the same phase.

Abstract: System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.

Abstract: In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit.

Abstract: A phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is arranged to compare a first input signal and a second input signal to generate a phase detecting result. The comparator is arranged to compare the phase detecting result and a predetermined voltage to generate a comparing result. The counter is arranged to count one of the first input signal and the second input signal to generate a counting value. The phase detecting result and the counting value are reset if the counting value reaches a predetermined value, and the comparing result is outputted to a target device from the comparator if the counting value reaches a predetermined value.

Abstract: A vernier phase error detection method is provided. The method comprises providing a first signal having a first cycle T1, wherein T1=1/N T; providing a second signal having a second cycle T2, wherein T2=1/M T; aligning a rising edge of the second signal with a rising edge of the first signal; when a second data sampled by the second signal is different from a first data sampled by the first signal at the Xth second cycle, a phase error Ø is evaluated by the following equation: Ø=(N/2?X)*T1.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: A phase discriminator for being used in a phase-locked loop to determine if a phase difference between a reference signal and a target signal has reached a programmable gap value is disclose which comprises a programmable phase gap selector receiving the reference signal, a first phase digital converter converting an output signal from the programmable phase gap selector to a first digital code, a second phase digital converter converting a phase difference between the target signal and the reference signal to a second digital code, and a code comparator comparing the first and second digital code and generating a first instructional signal based on a change of order of the values of the first and second digital code.

Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract: A radio frequency (RF) power generator includes a first switch-mode amplifier that generates a first RF signal in accordance with a first control signal and a second switch-mode amplifier that generates a second RF signal in accordance with a second control signal. The first and second control signals determine a phase difference between the first and second RF signals. An output signal envelope is based on the first and second RF signals and the phase difference. The first control and second control signals alternate phases of the first and second RF signals.

Abstract: A system and method for detecting a phase and a frequency and an arrival-time difference between two signals (118 and 120) that minimizes delay and jitter, and has stable operation even when the two signals (118 and 120) are essentially identical. The system includes two single-ended charge-pump (188), phase-frequency detection (PFD) circuits (280). The first PFD is stable when a reference signal, supplied to a polarity determining flip-flop, leads the signal to be synchronized. A second, complementary, PFD circuit is stable, but has an inverted polarity output, when the signal to be synchronized, supplied to a polarity determining flip-flop, leads the reference signal. A polarity-selection logic-circuit (284) ensures that the first activated PFD controls the polarity a single-ended charge pump (188) for a time-period determined by the delay between the activation of the polarity determining and non-polarity determining flip-flops of the selected PFD.

Abstract: A method and device detect synchronization errors between logic signals of a group of logic signals. A control word is loaded into a shift register arranged in loop and clocked by resulting logic signals equal to the result of the OR logic function and to the result of the AND logic function applied to the logic signals of the group of logic signals. The value of the control word is monitored as it propagates in the shift register, and a synchronization error signal is sent if the control word changes value. Application in particular for checking the integrity of a clock tree in an integrated circuit.

Abstract: It is an object of the present invention to improve the phase difference detection accuracy of a phase comparator. A phase difference signal generation circuit outputs a signal C_SIGNAL which takes a high level for a period corresponding to the phase difference between the comparison target signals COMP1 and COMP2 to the control terminal of a tri-state buffer, based on a signal synchronous with the start-up of the comparison target signal COMP1 detected by an edge detection flag generation circuit and a signal synchronous with the start-up of the comparison target signal COMP2 detected by an edge detection flag generation circuit. A status management circuit outputs a signal A_SIGNAL corresponding to the phase advance or delay of the comparison target signals COMP1 and COMP2 to the input terminal of the tri-state buffer.

Abstract: This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the summed signal to provide an output signal; generating an extracted test signal from the output signal; comparing the extracted test signal with a reference signal representing said periodic test signal; generating an error signal in dependence upon the result of said comparing step. The invention also provides a method and apparatus for testing a plurality of adjacent input circuits.

Abstract: A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.

Abstract: An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.

Abstract: A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.

Abstract: In a method for determining whether multiple power outlets in a 3-wire power line connection are connected to a same outer wire (P1 or P2), the hot terminal of a first power outlet is identified and a first zero cross time of the hot terminal to which AC voltage is applied is detected. The hot terminal of a second power outlet is identified, and second zero cross time of the hot terminal to which AC voltage is applied is detected. It is determined that the first power outlet and the second power outlet are connected to the same power line if the time elapsed AT from the first zero cross time of the first power outlet to the second zero cross time of the second power outlet is an integral multiple of the AC voltage cycle.