Abstract: This invention provides a detection circuit which can reliably detect an out-of-synchronism state of a clock signal with respect to data even if jitter is present in a data signal. A delayed clock signal obtained by delaying a clock signal by 90° through a delay circuit is input to a data input (D) of a flip flop, and the clock signal is read in at the point of change of the data. A logic product of the inverted output of the flip flop and the data signal is obtained by an AND circuit. Then, a logic product output is counted by a counter circuit, and an out-of-synchronism state of the clock with respect to the data is detected based on the output of the counter circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and the reset signal. The second circuit may be configured to (i) switch a pull up signal in response to the pump up signal, (ii) switch a pull down signal in response to the pump down signal, and (iii) present the reset signal in response to switching the pull up signal and the pull down signal.

Abstract: An improved DDLL containing a majority filter counter circuit is disclosed. The majority filter counter circuit is located between the phase detector and the shift register of the DDLL. The majority filter counter circuit receives shifting commands from the phase detector and filters the shift commands from reaching the shift register until a predetermined number (e.g., 16) have been received from the phase detector before transmitting a shift command (either shift right or shift left) to the shift register. Once the shift register receives the shift command, the shift register directs the delay line to shift by one tap in either a shift right or a shift left direction depending upon the phase relationship between CLKIn and CLKOut. By waiting for e.g., 16 shift commands, the majority filter counter circuit ensures that a premature shift command is not delivered to the shift register in the case of a noise event.

Abstract: A frequency doubler circuit implemented in an integrated circuit and having improved doubling performance is provided. The frequency doubler circuit including a phase shifter, a first buffer, a second buffer, a detect-control unit, a third buffer, a fourth buffer, a multiplier and an output buffer. The phase shifter outputs, in response to an input signal having a predetermined frequency, a first signal which is in phase with the input signal and a second signal which is out-of-phase from the input signal. The first buffer filters and buffers the first signal, and the second buffer filters and buffers the second signal. The detect-control unit detects a phase difference between the first and second signals in response to the first signal, the second signal, the output signal of the first buffer and the output signal of the second buffer, and outputs first and second control signals.

Abstract: To provide a phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and have a high linearity of a phase to voltage conversion characteristic around phase-locked point in an operation of comparing phases of random NRZ signals in a phase.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: An improvement to a phase and frequency detector (PFD) employs an additional reset control that acts to effectively reset the registers that generate the phase indicator signals if an undesirable preconditioned state has been entered. The additional reset control signal is generated by a register that is enabled upon detection of the preconditioned state. The new reset control signal is activated upon detection of a synchronizing signal, that is based on an input source signal, while the enable control is active. The improved detector can allows a phase locked loop (PLL) system locking to the nearest input reference clock edge and it can provide immunity to missing input clock edges.

Abstract: A data comparator using a dynamic reference voltage and an input buffer using the same. The data comparator comprises a comparator circuit for receiving a data signal and a pair of non-inverting/inverting signals, which are periodic and complementary. The output signal is generated by comparing twice the data signal with the sum of the non-inverting signal and the inverting signal. The non-inverting/inverting signals are used as a dynamic reference voltage in the data comparator.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: A signal processing method and apparatus in which a horizontal and/or vertical synchronizing signal related to a received video signal is monitored to determine if a relatively large change has occurred in the respective vertical and/or horizontal time period such that a change in video signal source may have occurred. Upon the detection of such a change, the operation of a phase lock loop (PLL) such as horizontal phase lock loop (HPLL) and/or vertical phase lock loop (VPLL) circuit is adapted as appropriate.

Abstract: A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

Abstract: An apparatus and method in an integrated circuit for detecting phase differences between clock signals originating from an oscillator circuit. The oscillator circuit is formed on a substrate, such that the oscillator circuit is coupled to coincidence elements responsive to clock signals originating from the oscillator circuit. In addition, a coincidence circuit is provided that includes the coincidence elements, such that the coincidence circuit provides output signals only in response to a change in all clock signals originating from the oscillator circuit. The apparatus includes a delay circuit responsive to the output signals, such that the delay circuit stretches delays between the clock signals. A phase detector is coupled to the delay circuit, such that the phase detector is responsible for detecting phase differences between the clock signals by identifying the delays.

Abstract: A digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. In one embodiment, the present invention relates to a digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal. The detection circuit is coupled to clock signals that are out of phase with the clock signal that triggers the metastable flip flop in the phase shift amplifier.

Abstract: A semiconductor integrated circuit comprises a phase control unit for shifting the phase of an input signal by two or more different fixed phases so as to generate two or more output signals out of phase. A phase detector detects phase differences among the two or more output signals from the phase control unit, and generates one or more correction signals each having a value corresponding to a deviation of one of the detected phase differences from a desired phase difference. The phase detector feeds the one or more correction signals back to the phase control unit so as to make the detected phase differences equal to desired phase differences, respectively.

Abstract: An improved phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency divider that receives as an input signal one of the first and second oscillator signals. The frequency divider also receives the select signal from the control block. The frequency divider generates a plurality of frequency-divided signals in response to the input signal, and passes through a selected one of the plurality of frequency-divided signals as an output signal in response to the select signal. The frequency divider also synchronizes its output signal to its input signal. The phase-locked loop also includes a frequency comparator that receives the output signal of the frequency divider and a signal derived from one of the first and second oscillator signals.

Abstract: A phase detector including a voltage controlled oscillator generating a voltage controlled oscillator output, and a first logic state device for receiving said voltage controlled oscillator output as an input. The phase detector also includes a reset device, for generating a reset signal to reset the first logic state device such that the output control signal of the first logic state device reaches a low level in response to a first edge of the reset signal.

Abstract: A phase detector is disclosed that detects the phase of two inputs with precision. A method and apparatus of phase detecting that subtracts out common errors due to temperature variations and supply voltage fluctuations. The phase detector and method preferably utilize digital circuitry such as exclusive OR gates and differential amplifiers to perform the accurate phase detection. The inputs and outputs may be attenuated or filtered to produce the desired results.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: A mode control circuit of a PLL circuit for switching the PLL circuit from a high-speed mode to a normal mode. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.

Abstract: A radio device includes phase discriminator with a phase locked loop. Where when there is no phase locking, the output voltage of the phase discriminator remains constant, which provides considerable gain for loop. When there is phase locking, the phase discriminator produces an error proportional to the phase difference. An output of the phase discriminator has a constant amplitude with an input signal and a reference signal have different frequencies.

Abstract: A method for processing time-resolved optical emission data (“waveforms”) comprises processing both a first and a second waveform, and analyzing the results. The processing uses a substantial portion of the waveform and not merely the peaks of the waveform. A system which implements the method, and a computer readable medium which contains instructions for implementing the method, are also disclosed. The embodiments disclose methods for analyzing time-resolved optical emission data using correlation and/or transform techniques on the optical waveforms to extract timing information. The techniques offer more accurate results than direct examination of the waveforms and are additionally useful in tests having high noise or low numbers of detected photons. The techniques allow significant automation and the results lend themselves to graphic display.

Abstract: The present invention provides delay locked loop circuits, phase detectors and methods for producing a delayed signal from a periodic input signal. An intermediate delay signal as well as an input signal and a delayed output signal are provided to a delay control circuit that controls the delay of a delay circuit based on a comparison of the input signal and output signal following a transition of the intermediate signal. The apparatus and methods of the present invention may thereby be able to distinguish between a case in which tTOTAL=T and tTOTAL=2T to reduce the potential for locking in a false state.

Abstract: A method of phase detecting a data input NRZ signal comprises applying the input data signal to a pair of parallel channels each comprising the same phase delay, and each clocked using the same clock signal. The phase delayed input data signal is coupled to respective inputs of a pair of phase comparators. The input data signal is coupled to a further channel comprising the same phase delay, and the further channel is clocked using the same clock signal. The phase delayed input signal is passed from the further channel through a further delay which is a fraction of that same phase delay, and the further delay is clocked using the clock signal. The further delayed input data signal is applied to another input of one of the phase comparators. The input data signal is applied through another phase delay which has the fraction of the aforenoted same phase delay (but is unclocked), to another input of the other of the phase comparators. Output signals are obtained from each of the phase comparators.

Abstract: A phase-comparison circuit includes (a) a first PNP transistor, (b) a second PNP transistor, (c) a third NPN transistor electrically connected to both a collector of the first PNP transistor and a base of the second PNP transistor, and (d) a constant current source electrically connected to an emitter of the third NPN transistor. The phase comparison circuit compensates for an offset current between a reference current and an output current, and as a result, can properly operate at a low voltage.

Abstract: A delay locked loop circuit includes a variable delay circuit that receives an input clock signal and produces a delayed clock signal that is variably delayed with respect to the input clock signal responsive to a delay control signal applied to the variable delay circuit. A delay control circuit is responsive to the input clock signal and to the delayed clock signal, and applies a delay control signal to the variable delay circuit based on a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge of the input clock signal. In an embodiment, the delay control circuit includes a phase comparator circuit that receives the input clock signal and the delayed clock signal and produces a phase comparison signal that indicates whether the edge of the delayed clock signal corresponding to the first edge of the reference clock signal leads or lags the second edge of the input clock signal.

Abstract: The present invention provides a dual mode phase and frequency detector for use with a charge pump and a loop filter. The charge pump is adapted to adjust charging or discharging of the loop filter to adjust a VCO for generating a digital clock. The dual mode phase and frequency detector includes a phase and frequency detector and a first delay element. The phase and frequency detector is arranged to receive the VCO clock for tracking a reference clock signal. The phase and frequency detector generates control signals in response to the VCO clock and the reference clock signal. The control signals control charging or discharging of a loop filter in a DLL when the phase and frequency detector is operating in a phase and frequency detector mode. The first delay element is coupled to receive one of the control signals from the phase and frequency detector for generating an auxiliary control signal in response to the VCO clock.

Abstract: A phase detector circuit (100) operating at a high frequency includes a steering circuit (112) operating on frequency-divided versions of the phase detector signals. The phase detector (100) implements steering by adding dividers (108, 110) at both input ports to the steering circuit (112). This achieves the desired effect of reducing the operating frequency of the input signals to the steering circuit (112) to make operation possible at high frequencies of operation. The phase detector (100) also allows the steer circuit (112) to be turned off in steady state operation, this is accomplished by coupling only the steer outputs of the steering circuit (12) to the tuning line. The phase/frequency detect outputs are not coupled to the tuning line.

Abstract: A digital phase shift amplification and detection system and method for amplifying and detecting a phase shift. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region in which the applied signal transitions at a relatively close time to a trigger in the clock signal of the flip flop. The digital phase shift amplification and detection system and method amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal.

Abstract: An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge. The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting.

Abstract: A phase frequency detection circuit of a phase locked loop (PLL) for liquid crystal display which compares a phase between an external synchronous signal and an internal synchronous signal from the PLL to generate a phase difference detection signal, including: a dividing circuit for dividing the external synchronous signal and the horizontal synchronous signal; a phase difference detecting circuit for detecting the phase difference between the divided external synchronous signal and the divided horizontal synchronous signal from the dividing circuit; a phase discriminating circuit for discriminating whether the divided external synchronous signal is ahead of the divided horizontal synchronous signal and generating the phase discriminating signal; and a comparison device for receiving the phase difference detection signal from the phase difference detection circuit and the phase discriminating signal from the phase discriminating circuit to generate the phase frequency difference signal.

Abstract: By applying a modification considering a frequency difference to a phase error signal, phase lock is established in a short period of time even when there is a frequency difference. A jump detector detects a discontinuous jump of the phase error signal which occurs when there is a frequency difference, and a state transition is caused in a state storage device in accordance with the resulting detection signal. A holding device corrects the phase error signal in accordance with the state stored in the state storage device and outputs the thus corrected phase error signal as a frequency-phase error signal.

Abstract: Phase selection circuit for selecting a phase from signal source generating a multi-phase clock signal is implemented utilizing a single stage of multiplexing gates for receiving taps from signal source, thus minimizing mismatch between phases. Multiplexing gates, connected together at their outputs, select between a tap and an inverse tap and are always left on. The outputs from multiplexing gates are analog summed together to create a single phase output signal which may be shifted in phase by one tap simply by inverting one of the input taps to a multiplexing gate, thus reducing glitching at output signal. Phase interpolation is provided for by further phase shifting the output in steps smaller than one tap utilizing multiplexor circuit which interpolates in multiple steps between a tap and inverse tap. Phase selection circuit provides for provides maximum bandwidth capability, while minimizing mismatch and glitching.

Abstract: A phase comparator that is configured with a fewer number of gates in an ECL circuit configuration as compared to conventional phase comparator circuits. The phase comparator also operates with lower current consumption, and can achieve a suitable detection of small phase difference by substantially suppressing the influence of spike noises which may arise in the signals input to the phase comparator.

Abstract: A circuit monitor performance of an integrated circuit. The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relative phase difference between the clock signal and the output signal on the output pin of the integrated circuit. The phase delay detection circuit includes a digital signal generator and an integrator. The digital signal generator is connected to an output pin of the integrated circuit. The digital signal generator generates a digital signal. Changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal used by the integrated circuit are encoded in a duty cycle of the digital signal generated by the digital signal generator. The integrator is connected to the digital signal generator and integrates the digital signal to produce an integrated signal.

Abstract: A phase detector and a method for detecting phase difference between two high frequency signals, the phase detector is adapted to receive a reference signal REF, a high frequency signal ICOS, and a signal FD synchronized to ICOS. REF, ICOS and FD have opposite edges. The phase detector comprising of: An asynchronous phase detector circuit, for providing an asynchronous control signal CTP, for representing a time interval between a time of occurrence of an edge of REF and the time of occurrence of a corresponding edge of ICOS. A synchronous phase detector circuit, for providing an synchronous control signal TC, for representing a time interval between a time of the occurrence of the corresponding edge of ICOS and the time of occurrence of a corresponding edge of FD.A combing circuit, for receiving TC and CTP and providing an error signal ERS, representing the phase difference between REF and FD.

Abstract: Network elements of a synchronous digital communications system have a clock generator for generating a clock signal locked to an input signal. Such a clock generator comprises a tunable oscillator (OSC) and a phase comparator (PK) for comparing the phase of the input signal (IN) with the phase of the clock signal (CLK) and for generating a correction signal which serves to tune the oscillator (OSC). To avoid phase transients due to interruptions and disturbances in the input signal (IN), means (WD) are provided for determining an expectancy window, for deciding whether the correction signal lies within the expectancy window, and for tuning the oscillator with the correction signal if the correction signal lies within the expectancy window.

Abstract: A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal.

Abstract: A phase locked loop comprises a phase locking circuit (16) which includes a phase/frequency detector (18) capable of outputting up and down signals to a charge pump (22) through separate signal paths (24, 26) and a phase lock detector (34) coupled to receive the up and down signals. The phase lock detector (34) determines the difference between the up and down signals from the phase/frequency detector (18) and in response generates a phase lock indicator signal PLL.sub.-- OUT.

Abstract: A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for

Abstract: The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.

Abstract: A phase detector determines an error value dependent on the relative phase between a local oscillator signal, used as the system clock, and an input signal received over a PR (a, b, a) channel. The phase error value is used to control a phase locked loop (FIG. 1, not shown). The received signal is sampled at regular intervals dependent on the local oscillator signal. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled value to three thresholds provided on respective ones of slicer threshold inputs 23, 24 and 25. A subtracter 27 determines a difference value corresponding to a difference between the ideal sample value and the actual sample value for that sampling point. A delay register 28 and a subtracter 29 operate to determine the sense of change to the current ideal sample value from an ideal sample value for a preceding sample point.

Abstract: A wireless communication system (10) uses a phase detector (28) having a first pair of flip-flops (50, 56) for detecting the phase difference between an input frequency and a reference frequency. The first pair of flip-flops control current sources (66, 70) in the charge pump of the phase detector to modulate the error signal. A second pair of flip-flops (52, 58) detect when the input frequency is more than 2.pi. ahead of or behind the reference frequency. The second pair of flip-flops increment and decrement a counter (54) which in turn controls additional current sources (78-88) in the charge pump. The additional current sources extend the linear operating range of the error signal when the phase error exceeds .+-.2.pi..

Abstract: A phase comparison and error correction circuit which utilizes one of a plurality of outputs of its phase detector as a biasing voltage for its error correction circuit.

Abstract: Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to use source synchronous techniques for data transmission. The circuitry is implemented in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver. The DLL measures the phase difference between a strobe signal and a delayed strobe signal. The DLL can be externally controlled by a source selectable input which allows the delay of the delayed strobe signal to be varied to test T.sub.setup and T.sub.hold in the receiver without varying the timings of the strobe signal and the data signals supplied to the chips. A timing measurement circuit having the strobe signal, the delayed strobe signal, and reference signals as inputs may be used to calibrate the phase difference between the strobe signal and delayed strobe signal.

Abstract: A no-hit switching apparatus includes a phase comparing circuit, a first selecting circuit, a second selecting circuit, a memory circuit, a read address counter, and a switching circuit. The phase comparing circuit compares the phases of two received signals. The first selecting circuit selects a signal with a smaller phase delay from the two received signals on the basis of the comparison result in the phase comparing circuit. The second selecting circuit selects a signal with a larger phase delay from the two received signals on the basis of the comparison in the phase comparing circuit. The memory circuit stores the signal selected by the first selecting circuit. The read address counter reads out the signal stored in the memory circuit with the phase of the signal with the larger phase delay. The switching circuit switches between the signal read out by the read address counter and the signal selected by the second selecting circuit.

Abstract: A phase comparator apparatus compares a first input signal and a second input signal to output first or second compare output signal. The apparatus includes a detector circuit and a compare output generator circuit. The detector circuit detects the phase difference between the first and second signals to output a detection signal. The compare output generator circuit determines the phase deviation between the first and second input signals using the detection signal and the second input signal. The compare output generator circuit outputs the first compare output signal when the second input signal lags behind the first input signal and outputs the second compare output signal when the second input signal leads the first input signal.

Abstract: The present invention is a method and an apparatus for measuring phase differences between signals A and B using an absolute voltage value for each phase difference between .+-.180.degree.. This is accomplished using a third signal C, which is a signal having a phase approximately equal to the average phase between signals A and B. Signals C and A are subsequently amplitude limited and mixed to produce a fourth signal D, which is a signal having associated an absolute voltage value for each degree of phase difference between .+-.180.degree. for signals A and B.

Abstract: A digital phase measuring system and method for measuring the phase difference between two signals including generating quadrature clock signals for a first reference signal, converting a second measured signal from analog to digital form by sampling the second measured signal using the quadrature clock signals to produce quadrature cartesian samples of the measured signal, and converting the quadrature cartesian samples to polar coordinates to define the polar phase coordinate representative of the phase difference between the two signals.

Abstract: A phase detector circuit includes a first flip flop, a second flip flop, a first charge pump and a second charge pump. Outputs of the flip flops directly enable the charge pumps in response to received clocking signals. A first delay circuit delays the output signal from the first flip flop to an AND gate which combines the delayed output signal and the output signal from the second flip flop. The AND gate output is delayed in a second delay circuit to produce a delayed reset signal which resets both flip flops simultaneously and disables the charge pumps. The phase detector circuit balances the amount of charge provided to a phase locked loop near the in-phase condition to improve linearization of the phase detector.