Abstract: In a method for determining whether multiple power outlets in a 3-wire power line connection are connected to a same outer wire (P1 or P2), the hot terminal of a first power outlet is identified and a first zero cross time of the hot terminal to which AC voltage is applied is detected. The hot terminal of a second power outlet is identified, and second zero cross time of the hot terminal to which AC voltage is applied is detected. It is determined that the first power outlet and the second power outlet are connected to the same power line if the time elapsed AT from the first zero cross time of the first power outlet to the second zero cross time of the second power outlet is an integral multiple of the AC voltage cycle.

Abstract: An apparatus may include a first phase control circuit and/or a second phase control circuit. The first phase control circuit may compare the phase of the first clock signal with the phase of the second clock signal, and may control the phase of the first clock signal based on the result of the comparison. The second phase control circuit may control the phase of the second clock signal based on the result of the comparison output from the first phase control circuit. The first phase control circuit may control the phase of the first clock signal and/or the second phase control circuit may control the phase of the second clock signal such that they are synchronized with each other.

Abstract: The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK<1:8>). The sampling (14) delivers a first, more significant digital component (OUT1<9:0>) of the phase detection signal (PD_OUT).

Abstract: The voltage deviation is converted into the time quantity with the first integration circuit for the voltage detection and the second integration circuit for the voltage detection. The current setting value and the current measurements are converted into the time quantity with the second integration circuit for the current control to which the first integration circuit for the current control from which the voltage value of the set current value corresponding is input and the voltage value of the value of the current of the inductor corresponding are input and it controls. And, the start of the first integration circuit for the current control is delayed with operation quantity signal generation circuit only at the time that the high-resolution evaluation or more than the start of the first integration circuit for the current control and corresponds to the voltage deviation.

Abstract: A method and an input signal level detection apparatus that correctly detect a level of an input signal while consuming low power apparatus including: a full-wave rectifier outputting a full-wave rectified waveform by performing a full-wave rectification on a first signal corresponding to an input signal, and on a second signal having a phase difference of 180 degrees from the first signal; a common voltage detector detecting a common voltage of the first signal and the second signal; and a level detection unit detecting a level of the input signal, based on a subtraction result obtained by subtracting the common voltage from the full-wave rectified waveform.

Abstract: A signal detector for detecting and indicating the duration of a signal pulse by comparing the relative polarities of two voltages generated during the two states of the pulsed signal.

Abstract: A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.

Abstract: The present invention discloses a system and method for reducing delay difference of differential transmission, a certain delay difference between waveforms of the P signal and N signal is generated through controlling delay adjustment to P signal or N signal of the differential signals and controlling delay adjustment value simultaneously, to compensate for the delay difference of differential transmission due to the channels. Therefore, the present invention can reduce the delay difference of differential transmission due to property discrepancy of board materials and delay inconsistency among pins of the connectors, and at same time simplify the scheme design.

Abstract: A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit.

Abstract: A fast locking phase locked loop includes a first phase frequency detector (PFD), a second PFD, a lock detector, an up-signal output unit, a down-signal output unit, a selective charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The first PFD outputs a first up-signal and a first down-signal. The second PFD outputs a second up-signal and a second down-signal. The lock detector outputs an inverted lock signal. The selective charge pump outputs a pumping current. The loop filter generates a control voltage in response to the pumping current. The VCO generates the external clock signal having a frequency determined in accordance with the control voltage. The PLL has a faster locking time because the PFDs included in the PLL are capable of detecting a phase difference in a missing edge.

Abstract: The present invention discloses a system and method for reducing delay difference of differential transmission, a certain delay difference between waveforms of the P signal and N signal is generated through controlling delay adjustment to P signal or N signal of the differential signals and controlling delay adjustment value simultaneously, to compensate for the delay difference of differential transmission due to the channels. Therefore, the present invention can reduce the delay difference of differential transmission due to property discrepancy of board materials and delay inconsistency among pins of the connectors, and at same time simplify the scheme design.

Abstract: A clock signal detector is provided. The device comprises a plurality of signal delayers and a plurality of flip-flops for comparing the offset range of the clock signal between two different groups, and transmitting the resulted signal to a phase compensator, which is used to send a regulating clock signal to a clock generator. Therefore, the offset ranges of the clock signals from two different groups will be within the range of the system requirement, such that it can optimize the system operation.

Abstract: A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit. The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control signals. The clock signals have the same frequency but different phases, and the frequency of the data signal is a multiple of the frequency of the clock signals. The logic circuit performs various logic operations according to these control signals to output at least one set of gain control signals for adjusting a gain curve of the phase detecting circuit.

Abstract: There is provided a phase detection apparatus that can accurately detect a phase difference between an input signal and a reference signal even when the input signal and the reference signal have different duty cycles. A phase detection apparatus according to an aspect of the invention may include: a pulse generation unit generating a first pulse signal on an edge of an input pulse signal, and a second pulse signal based on an edge of a reference pulse signal having a predetermined phase; and a detection unit detecting a phase difference between the first pulse signal and the second pulse signal from the pulse generation unit.

Abstract: There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, including a pulse generating section having first pulse generating means for detecting edges of the data-signal-under-measurement to output a first pulse signal having a pulse width set in advance corresponding to the edge and second pulse generating means for detecting boundaries of data sections where data values do not change in the data-signal-under-measurement to output a second pulse signal having a pulse width set in advance over the edge timings of the boundaries of the detected data sections and a jitter calculating section for calculating timing jitter in the data-signal-under-measurement based on the first and second pulse signals.

Abstract: Bang-bang phase detection (BBPD) methods and circuits are presented for providing low latency, low jitter phase detection for use in high data-rate applications. A shortened data-path implementation of BBPD methods and circuits provides low-latency production of two output signals including alternating samples of the input signal. Combinational logic circuitry is also provided to produce a clock-data recovery (CDR) signal indicative of the phase of the input signal with respect to a clock signal. The use of differential signals throughout the BBPD timing circuitry provides for the production of a low jitter CDR signal.

Abstract: A radiation hardened phase frequency detector (PFD) is provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.

Abstract: A phase/frequency comparator is described which includes two edge-triggered storage elements, each set by an edge of a reference frequency signal of a phase—or frequency-locked loop (PLL) and by an edge of an output frequency signal of the PLL. The storage elements are each reset by an output signal of a resetting logic unit, which is activated when both output signals of the storage elements are activated and then deactivated when the output signals are deactivated.

Abstract: A phase-controlled current source for phase-locked loop is provided. The phase-locked loop includes a voltage-controlled oscillator to associate a charging path or discharging path in order to generate an output signal and the output signal is further sensed so as to generate a loop signal. The phase-controlled current source includes a status memory receiving the loop signal and the reference signal so as to output an energy-triggering/energy-removing signal; and a controllable current source, under the control by energy-triggering/energy-removing signal so as to decide whether a charging and discharging action should be performed, wherein after the charging action or discharging action is decided, the charging path or the discharging path is generated through the reference signal and the loop signal.

Abstract: An apparatus of phase-frequency detector for adjusting wobble clock signal and wobble signal in the same phase, comprising: a first logic gate, receiving a first protection signal and a second protection signal and outputting a third protection signal according to a logic operation; a first flip-flop, coupled to the first logic gate, outputting the third protection signal as a first output signal when the wobble clock trigger; a second flip-flop, coupled to the first logic gate, outputting the third protection signal as a second output signal when the wobble signal trigger; a second logic gate, coupled to the first and the second flip-flop, outputting a fourth protection signal according to a logic operation; a third logic gate, coupled to the second logic gate, receiving the third and the fourth protection signal, and outputting a fifth protection signal according to a logic operation; and a control signal generator, receiving the wobble clock, the input signal, and the fifth protection signal and determinin

Abstract: A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions.

Abstract: Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was received first. In response, the phase decision circuit generates respective logic signals to reflect the phase relationship determination. The circuit also includes a latch circuit that receives the logic signals from the phase decision circuit and holds the phase relationship determination of the circuit a predetermined time after a predetermined transition of both clock signals have occurred. Methods and systems are also disclosed.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in response to unassertion of the first signal. The phase detector may include combinatorial logic gates, thereby to generate the third and fourth signals in response to logic levels of the first and second signals. The phase detector may include sequential logic gates, thereby to generate the third and fourth signals in response to transitions of the first and second signals.

Abstract: A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sensing devices, and a reset control circuit. The sensing devices control the pulse generators based on signals received at corresponding first ends of the sensing devices. The inverting circuits generate signals to the first and second output ends of the phase-frequency detector based on signals received at corresponding first ends of the inverting circuits. The reset control circuit generates reset signals based on signals received at the first and second output ends of the phase-frequency detector.

Abstract: A phase-difference detecting method is for detecting phase difference between a first signal and a second signal of the same frequency. First, generate a detection signal. Next, sample the detection signal respectively according to the first signal and the second signal to obtain a first sample value and a second sample value. Then, determine whether a determination condition that the first and the second sample values are respectively equal to the previous first and second sample values is satisfied. When the determination condition is unsatisfied for the first time, record a delay time of the detection signal as a first time. When the determination condition is unsatisfied for the second time, record a delay time of the detection signal as a second time. Obtain the phase difference between the first signal and the second signal according to the first time and the second time.

Abstract: The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a delayed reset signal and a second flip-flop configured to generate a second signal, the second signal transitioning to the first logic level in response to a second edge of a second input signal and transitioning to the second logic level in response to the delayed reset signal. The phase-frequency detector may further include a first delay unit configured to delay a reset signal to generate the delayed reset signal and a second delay unit configured to delay the reset signal to generate an output control signal for adjusting at least one of the first and second signals.

Abstract: Providing a CDR circuit having a stable clock extracting function and a data regenerating function with a high-speed data input process by reducing the operation speed of the phase comparator circuit. With a phase comparator circuit capable of operating with a clock signal whose period is 2 times the unit time width of the inputted data signal, the pulse width of the phase error signal, representing the difference in phase between the transition point of the data signal and the transition point of the clock signal, is extended as much as the unit time width of the data signal.

Abstract: A differential-type high-speed phase detector is provided, and it includes a first DTHT module and a second DTHT module wherein these two DTHT modules are the same. The first DTHT module includes a first input for receiving a signal CK_ref, a second input for receiving a signal CK_fb, a first logic unit, a second logic unit, a third logic unit and an output. An imperceptible delay period difference is produced by the difference of the capacitance value between two capacitors to diminish the size of the dead zone of the phase detector in accordance with the prior art. As a result, the differential-type high-speed phase detector also keeps high speed and tri-state outputs such that the performance of the dead zone is enhanced.

Abstract: A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Abstract: In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock pulses is used for sampling approximately the transition portions between every two adjacent data bits in the incoming data stream to produce a second sampled data stream. By detecting the resemblance of each bit in the second sampled data stream to the corresponding two adjacent bits in the first sampled data stream, a phase detection and correction circuit determines an early condition or a late condition for the phases of the sampling clocks and produces a signal to correct the phases of the sampling clocks by shifting the phases backwards or forwards. According to the invention, sampling clocks with lower frequencies can be used for sampling, and the phase error can be corrected to obtain the correct data recovery.

Abstract: A fast locking phase locked loop includes a first phase frequency detector (PFD), a second PFD, a lock detector, an up-signal output unit, a down-signal output unit, a selective charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The first PFD outputs a first up-signal and a first down-signal. The second PFD outputs a second up-signal and a second down-signal. The lock detector outputs an inverted lock signal. The selective charge pump outputs a pumping current. The loop filter generates a control voltage in response to the pumping current. The VCO generates the external clock signal having a frequency determined in accordance with the control voltage. The PLL has a faster locking time because the PFDs included in the PLL are capable of detecting a phase difference in a missing edge.

Abstract: A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first clock successively delayed through the first delay elements and hold a digital value representing a relative phase difference, in accordance with the second clock successively delayed through the second delay elements. Therefore, the phase detection resolution of the digital phase detector can be improved.

Abstract: An inverted-phase detector is implemented in a system including a first clock circuit that provides a first clock signal and a delayed clock circuit that outputs an delayed clock signal. A reference circuit outputs a reference signal. A feedback circuit generates a feedback signal that is one of greater than and less than the reference signal when the first clock signal changes state before the second clock signal, and that is the other of greater than and less than the reference signal when the first clock signal changes state after the second clock signal.

Abstract: Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) according to delay. Each of the plurality of delay chain units may include a respective phase comparator. Each phase comparator is configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal applied to an input of the delay chain. This fraction of a period may be equivalent to one-half or other percentage of a period of the reference clock signal. The phase comparators with the delay chain units operate to generate a multi-bit delay value signal, which is provided to a delay chain control circuit.

Abstract: A phase comparator includes: first and second detecting units for detecting an amplitude value of a clock signal at falling timing or rising timing of a data signal; an edge comparing unit for identifying as to whether the first detecting unit detects an amplitude value under a rising state or a falling state to output a first identification result, and for identifying as to whether the second detecting unit detects an amplitude value under a rising state or a falling state to output a second identification result; first and second polarity inverting units for inverting a polarity of output of the first and second detecting units; and a signal selecting unit for selecting one of output values of the first and second polarity inverting units in response to a polarity of the data signal to output the selected output value.

Abstract: Methods and apparatus are provided for trimming a phase detector in a delay-locked-loop. A latch that evaluates a phase offset between two signals is trimmed by applying two signals to the latch that are substantially phase aligned; obtaining a phase offset between the two signals measured by the latch; and adjusting a trim setting of one or more buffers associated with the two signals until the phase offset satisfies one or more predefined criteria. The two signals can be a clock signal and an inverted version of the clock signal. The two signals can be a source of phase aligned data generated from a single clock source.

Abstract: Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

Abstract: An improved clock lock detection circuit is disclosed. The circuit has a first input indicating an edge of a first clock and a second input indicating a corresponding edge of a second clock wherein the second clock is expected to be synchronized with the first clock with an allowable time difference. Further, it has a difference generation module for generating a difference signal based on the time difference between the first and second inputs, and a voltage divider module for receiving the difference signal and generating an indication voltage which varies based on a change of the time difference between the first and second inputs.

Abstract: A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock signal at a second frequency. The frequency of the first clock signal is a multiple of the frequency of the second clock signal. The phase detector also includes a second flip flop having a data input coupled to an output of the first flip flop and a clock input coupled to the second clock signal.

Abstract: A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further includes a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal, and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit.

Abstract: A skew-tolerant digital phase detector is provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that may result from clock skew and duty cycle distortion. If the condition is detected, an adjusted signal is generated and the adjusted signal is synchronized with the reference signal. By using the generated signal to provide a lock if certain conditions arise, adjustment errors resulting from duty cycle distortion and clock skew can be minimized.

Abstract: A structure and method for implementing a fully digital frequency difference detector uses an n-bit counter to count cycles of a reference clock signal and an m-bit counter to count cycles of a synthesized clock signal, where m is greater than n. The two counters operate concurrently, and both are halted when the n-bit counter overflows into its nth bit position. Two latches respectively record if bits n and (n+1) in the m-bit become set prior to the n-bit counter overflowing. By observing the state of the two latches and the state of a predefined bit range within the m-counter, the frequency difference detector can determined if the frequency of the synthesized clock is greater than, less than, or locked to the frequency of the reference clock signal.

Abstract: A system and method of reducing the pulse width differential in a phase frequency detector (PFD) is provided. In a first embodiment, a PFD is construed using a plurality of flip-flops (or clocking devices) and a plurality of logic gates. A first set of flip-flops are adapted to receive a plurality of inputs and a plurality of clocks and to latch the inputs at transitions in the clocks. A first logic gate is then used to reset the first set of flip-flops and a second set of flip-flops if the inputs are latched (i.e., the clocks are active). If an input is not latched (i.e., a clock is inactive), then the first and second set of flip-flops are not reset, and the outputs of the PFD are forced to zero. Once the inactive clock is reactivated, a third set of flip-flops is used to hold the first set of flip-flops in a reset state for a period of time (e.g., half a clock cycle). Once the period of time elapses, the first set of flip-flops is released from its reset state, and normal operation is resumed.

Abstract: This invention is to allow accurate high-speed coincidence detection while preventing any increase in circuit scale. To achieve this object, a coincidence detection apparatus includes a detector which outputs at least two periodical signals in accordance with the displacement of an object, a digital interpolator which processes the periodical signal output from the detector at a predetermined time interval to generate a displacement or angle at a period shorter than the period of the periodical signal, a pulse generation unit which generates a constant frequency pulse signal, a counter which counts the pulse signal output from the pulse generation unit, and a pulse conversion unit which calculates a value to be set in the counter from the difference between displacement information corresponding to the target position of the object and the output from the digital interpolator.

Abstract: An input circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal and a second signal and to sample the first signal via the second signal and provide signal samples of the first signal. The second circuit is configured to receive a third signal and the signal samples and to update a second circuit output signal via the third signal and provide the updated second circuit output signal. The third circuit is configured to receive a clock signal and the second signal and to provide the third signal. The third circuit is also configured to synchronize edges in the third signal to edges in the second signal and edges in the clock signal.