Abstract: The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may also have a second switching array, which emits an output signal, which when the first signal first has changed its state, changes its state in reaction to a change in the state of the first signal, and, when the second signal first has changed its state, changes its state in reaction to a change in the state of the first signal.

Abstract: A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Abstract: A phase detector and phase detection method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. At least one first flip flop is operable to sample the first clock signal with a rising edge of the second clock signal and at least one second flip flop is operable to sample the first clock signal with a falling edge of the second clock signal. The sampling produces transitions indicative of the coincident rising edges between the first and second signals.

Abstract: Delay-locked loop (DLL) integrated circuits include digital phase comparators that are unaffected by variable duty cycle ratios. These phase comparators determine a shortest direction to phase lock before establishing a value of a compare signal (COMP) that specifies the shortest direction. The phase comparator is responsive to a reference clock signal REF and a feedback clock signal FB. These clock signals have equivalent periods and may have equivalent non-unity duty cycle ratios. The phase comparator is configured to determine whether a first degree to which the reference clock signal REF leads the feedback clock signal FB is smaller or larger than a second degree to which the reference clock signal REF lags the feedback clock signal FB. Based on this determination, the phase comparator generates a compare signal COMP that identifies a direction in time the feedback clock signal FB should be shifted to bring it into alignment with the reference clock signal REF.

Abstract: A phase detector includes a first selection circuit configured to select a first clock from a first group of clocks supplied to the first selection circuit and to transmit the first clock, and at least one phase comparator configured to detect a difference in phases between the first clock and a second clock supplied to the phase comparator and to transmit the difference as a scan signal.

Abstract: A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting unit. The reset unit outputs reset signals according to the first and second input signals so as to reset the phase error detecting unit without delay time. Thus, it is possible to make the output timing of the phase error signal in a more precisely linear proportion to the phase error value and to enhance the sensitivity of the phase locked loop.

Abstract: A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.

Abstract: First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.

Abstract: A high-speed, half rate phase detector provides an effective solution to the problem of XOR gate response to the minimum width signal precursors (Q1 and Q2) of a phase signal that indicates a phase difference between a data signal and a clock signal by combining the precursor signals in a multiplexer and combining the multiplexed signal with the data signal in an XOR gate. This affords the transition information in the transitions of the precursor signals, which is significant of phase difference, without requiring the XOR gate to respond to the minimum widths of those pulses.

Abstract: Provided is a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL), the phase frequency detector including: an UP signal output unit having a first stage operated according to a reference clock delayed by a predetermined time and a reset signal, a second stage operated according to the reference clock and an output of the first stage, and an inverter for inverting an output of the second stage; a DOWN signal output unit having: a first stage operated according to an outer clock delayed by a predetermined time and the reset signal, a second stage operated according to the outer clock and an output of the first stage, and an inverter for inverting an output of the second stage; and a logic gate logically combining the output of the second stage of the UP signal output unit and the output of the second stage of the DOWN signal output unit to generate the reset signal, thereby a phase range of the input signal with which an effective control signal can be obtained is wide so

Abstract: A phase detector includes a first flip-flop responsive to a reference clock signal, a first inverter responsive to an output of the first flip-flop, a second flip-flop responsive to a feedback clock signal, a second inverter responsive to an output of the second flip-flop, a third inverter responsive to an output of the first inverter, a fourth inverter responsive to an output of the second inverter, a first conjunction circuit responsive to the output of the first inverter and to an output of the fourth inverter, and a second conjunction circuit responsive to the output of the second inverter and to an output of the third inverter. The first conjunction circuit outputs a first alignment signal when the feedback clock signal is earlier than the reference clock signal, and the second conjunction circuit outputs a second alignment signal when the feedback clock signal is later than the reference clock signal.

Abstract: A semiconductor test system having a tester and a prober and the test method thereof are proposed. A test mark signal and a control board having a discrimination circuit and a protection circuit are added to a test connection interface of the tester. When performing multi-chip test, the connection result is displayed after checking the test mark signal by the discrimination circuit. Whether the test can be performed or not is then determined by the protection circuit. When the interface connection is incorrect due to man-made carelessness, an alarm will buzz for warning, and the protection circuit will be simultaneously activated to disable the tester. Normal test can be performed only if the interface connection is correct. Thereby, the correctness of the test results can be ensured to reduce returned purchase and to enhance the quality of production.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: Calibrating return time includes determining clock calibration information based on clock signals local to a master device and return clock signals corresponding to each of at least two slave devices, storing clock calibration information with respect to each of the slave devices with which the master device will communicate using a bus, and, after the clock calibration information has been stored, resynchronizing data signals that are received from each of the slave devices based on the corresponding stored clock calibration information.

Abstract: An apparatus comprising a first circuit configured to generate (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and said reset signal and a second circuit configured to (i) generate said reset signal in response to said pump up signal and said pump down signal.

Abstract: A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the same. The clock generation circuit has: serially-connected inversion circuits IV0 to IV4 in which an output of IV4 is connected to an input of IV0 by a feedback line FL; and buffer circuits BF0 to BF4 which receives outputs from IV0 to IV4. The inversion circuits IV0 to IV4 are disposed along a line LN1 and the buffer circuits BF0 to BF4 are disposed along a line LN2 that is parallel to the feedback line FL but different from LN1. Dummy lines DL0 to DL3 each of which having parasitic capacitance that is equal to that of the feedback line FL are connected to the inversion circuits IV0 to IV3, to equalize the phase differences between clocks CK0 to CK4. The feedback line FL and the dummy lines DL0 to DL3 are disposed in a region between the inversion circuits IV0 to IV4 and the buffer circuits BF0 to BF4.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: A semiconductor integrated circuit includes a first clock input and a second clock input to receive elements of a differential clock signal. Each clock signal element has a logic state. The circuit generates an output activation signal that depends on the states of the differential clock input signals. Operation of the circuit does not require detection of a frequency of the differential clock signal.

Abstract: A half-rate linear phase detector is particularly well-suited to clock data recovery in a serial data interface. The phase detector uses a quadrature clock to process different portions of the incoming data with different phases of the clock. The resulting component signals can be combined to provide the expected UP and DOWN phase detector output control signals. The phase detector output signals are balanced and of uniform width, minimizing oscillator control signal ripple in the clock data recovery circuit, while the linearity of the phase detector makes its output predictable.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: A delay locked loop features a phase comparator. The phase comparator compares a phase of a reference clock signal obtained by dividing a buffered external clock signal with a phase of a feedback clock signal considering delay time of delay lines and inside circuits, and controls a shift register for controlling the delay lines in response not only a rising clock signal outputted from a clock buffer but also a falling clock signal depending on the comparison result, thereby rapidly locking an initial phase and tracking the phase in spite of fast delay variations by external noises.

Abstract: A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminal 3 of a multiplier circuit 62 approaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.

Abstract: A digital phase lock loop circuit including an error generation circuit for generating at least three error signals and a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals. By using at least three error signals, as opposed to just one, the drift in the sampling phase of the recovered clock is easily detected and corrected to reduce burst errors and to improve loss of lock (LOL) performance.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: A digital fractional phase detector is shown that uses a phase error detector for generating a phase error signal based on the phase difference between a reference clock signal and a feedback clock signal. A quantizer directly measures the pulse width of a phase error signal and outputs the value in a digital form. By directly measuring the phase error signal, quantization accuracy is increased. In order to calibrate the digital fractional phase detector, a calibration pulse generator generates a calibration pulse of a known duration and passes it to the quantizer.

Abstract: The invention relates to a new phase detector state machine having a reset state that is released only when both phase detector input signals (R, V) have a common predetermined signal state. In this way, phase inversion is effectively prevented. The complementary phase error is properly masked and the phase detector range is reduced to the interval—180°<&thgr;e<180°, while still maintaining the direction sensitivity. Phase errors &thgr;e larger than half a period are automatically discarded. Consequently, if the phase detector ends up in a state, for example due to reference clock loss, in which the phase error is larger than half a period, the phase detector will be shifted back to normal operation with a phase error less than half a period during the next consecutive phase comparison period. Naturally, this saves valuable time in the lock-acquisition procedure.

Abstract: Systems and methods for synchronizing a system clock signal with a reference clock signal having a reduced phased offset to improve operating speeds of integrated circuits. This is accomplished by generating delayed system and reference clock signals by using the system and reference clock signals. The generated delayed clock signals are then monitored to determine the arrival of the raising and falling edges of the delayed clock signals. The system clock signal is then compensated based on the determination of the arrival of the delayed clock signals to substantially synchronize the system clock signal with respect to the reference clock signal.

Abstract: A bang-bang phase detector circuit for use in a delay lock loop is disclosed. The phase detector includes a data signal line, a clock signal line, and a delay cell having an input coupled to the data signal line. The phase detector further includes a first double flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line, and a second double flip-flop having a data input coupled to an output of the delay cell and a clock input coupled to the clock signal line. A NOR circuit has a first input coupled to an output of the first double flip-flop and a second input coupled to an output of the second double flip-flop. The phase detector provides a lag output signal line coupled to an output of the NOR circuit, and a lead output signal line coupled to the output of the second double flip-flop.

Abstract: The present invention provides a method and an apparatus for generating a phase error signal from a reference signal and a feedback signal using a modified reset generation mechanism. An input circuit receives a reference signal and a feedback signal. A phase error detector circuit generates a phase error signal based on the reference signal and feedback signal. The input circuit is reset and, after a delay, the phase error detector circuit is reset. The delay is selected so that there is no jitter associated with the dead zone.

Abstract: Simple, glitch-free phase detector circuits provide add and subtract output signals indicating the phase relationship between two input clock signals. Some embodiments also provide a lock output signal having a lock window, and in some of these embodiments, the size of the lock window is programmable. An optionally delayed version of the feedback clock signal is stored a first time when the input clock signal goes high, then stored a second time after a predetermined delay. In some embodiments, the predetermined delay is programmable. When both stored values are low, the subtract output signal is active. When the first stored value is high, the add output signal is active, regardless of the state of the second stored value. When the first stored value is low and the second stored value is high, the two clocks are synchronized and the phase detector indicates a lock condition.

Abstract: A system and method of determining an in-situ signal path delay on an integrated circuit. The system and method includes inputting a first signal to a first input node of a first signal path and inputting a second signal to a second input node of a reference signal path. A phase of the first signal output from a first output node of the first signal path is compared to a phase of the second signal output from a second output node of the reference signal path. A phase error signal is output.

Abstract: In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit.

Abstract: A phase frequency detector (PFD) utilizes hysteresis dead zone avoidance while maximizing the linear range and minimizing the power and area consumed by the PFD circuit. The PFD includes a hysteresis in a reset logic gate, which prevents the reset logic gate from switching its output before each of the corrective pulses from the PFD reach final steady state DC voltage values. The PFD response simulates an ideal response, such that linearity is maintained at the phase lock point and throughout a linear range of +/−2&pgr;. In addition, the hysteresis reset logic gate monitors the corrective pulses to insert an appropriate amount of time delay into the PFD reset path without introducing additional delay elements. As a result, the linear range of the PHD is maximized and the power and area consumed by the PFD is minimized, due to the fact that additional delay elements are eliminated from the design.

Abstract: A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

Abstract: A phase detector employing asynchronous level-mode sequential circuitry is described. The phase detector includes edge detection circuitry for generating a first edge detection signal and a second edge detection signal. The first edge detection signal is indicative of an edge in a first clock signal, and the second edge detection signal is indicative of an edge in a second clock signal. The phase detector further includes a state machine that is asynchronously responsive to level changes in the first and second edge signals. The state machine generates a control signal indicative of which of the first and second clock signals is leading the other of the first and second clock signals.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes a phase-frequency detector (PFD) including two clock input ports, an up signal port and a down signal port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up output signal pulse and a down output signal pulse based, at least in part, upon the magnitude of an amount of phase delay between two respective clock signal pulses applied to the two input ports. Of course, additional embodiments are also disclosed.

Abstract: A double phase comparator sets both first and second signals to an “L” level in order to delay a phase of a feedback clock signal when the feedback clock signal is at the “H” level and the “L” level at the rising and falling edges of an internal clock signal, respectively. The double phase comparator also sets both first and third signals to the “L” levels in order to advance a phase of a feedback clock signal when the feedback clock signal is at the “L” level and the “H” level at the rising and falling edges of an internal clock signal, respectively. Moreover, the double phase comparator sets the first signal to the “H” level in order to stop a phase control of the feedback clock signal when the feedback clock signal is at the same level at the rising and falling edges of an internal clock signal.

Abstract: A method and a device for measuring a phase shift between a periodic signal and an output signal at an output of an electronic component. A supply voltage potential is applied to a electronic component, whereby the periodic signal is applied to the output of the electronic component. The current through the supply voltage input is measured, whereby a magnitude of the current corresponds to a phase shift between the periodic signal and the output signal.

Abstract: Improved systems and methods of phase detecting are described. In one aspect, a phase detector includes a latch having an input stage and an output stage. The input stage couples to the output stage through a dynamic storage node and includes a discharge circuit. The discharge circuit has a first input and a second input and defines a discharge path for discharging the dynamic storage node that is substantially symmetric with respect to the first and second inputs. In another aspect, the dynamic storage node is discharged with a characteristic discharge time in response to a transition of the first input from a low logic level to a high logic level when the second input is at a high logic level. The dynamic storage node also is discharged with substantially the same characteristic discharge time in response to a transition of the second input from a low logic level to a high logic level when the first input is at a high logic level.

Abstract: An apparatus and method for deskewing single-ended signals from different driver circuits of an automatic test system provides enough of a reduction in skew to allow differential signals to cross at or near their 50%-points. In accordance with this technique, first and second driver circuits are respectively coupled to first and second inputs of a measurement circuit through pathways having known and preferably equal propagation delays. The first and second driver circuits each generate an edge that propagates toward the DUT, and reflects back when it reaches a respective unmatched load at the location of the DUT. In response to the edge and its reflection, the first and second inputs of the measurement circuit each see a first voltage step and a second voltage step. The interval between the first and second voltage steps is then measured for each input of the measurement circuit.

Abstract: A phase detection system allows the capture range, lock range and jitter tolerance to be extended beyond ±360°. The capture range for the phase detection system may be extended in programmable amounts up to several thousand clock cycles or can be set to any desired maximum capture range in steps of approximately 360°. The phase detection system circuit utilizes a coarse phase detector and a fine phase detector. The phase detection system uses the digital cycle slip counter phase detector to provide a wide phase capture and lock range for a large jitter tolerance. The phase detection system combines this detector with a fine phase measurement from a PFD (phase and frequency detector) for very accurate phase control and low output jitter. The PFD operates in the approximately ±540° range and provides overlap in response with a coarse phase detector using a digital cycle counter approach.

Abstract: A phase-frequency detector (PFD) with increased phase error gain during acquisition of phase lock when used in a phase-locked loop (PLL). The reference and feedback signals are time-multiplexed into N pairs of input signals. Each pair of input signals is detected by one of N phase-frequency detectors, which produce N pairs of detection signals indicative of phase differences between the reference and feedback signals. These N pairs of detection signals are combined in separate logical-OR operations to produce a frequency increase control signal and a frequency decrease control signal indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: A method and circuit for determining variation between an input clock signal (CLK0) and a reference clock signal (REFCLK) is provided. A plurality of time shifted input clock signals (CLK0, CLK1, . . . , CLK09) can be generated from a single input clock signal (CLK0). The plurality of time shifted input clock signals (CLK0, CLK1, . . . , CLK09) can be sampled at successive periodic intervals occurring relative to the reference clock signal (REFCLK). For each of the time shifted input clock signals (CLK0, CLK1, . . . , CLK09), a sampled value for a succeeding and a preceding periodic interval can be compared to determine whether there is a variation between an input clock signal (CLK0) and a reference clock signal (REFCLK).

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first intermediate signal in response to a first differential signal and (ii) a second intermediate signal in response to a second differential signal. The second circuit may be configured (i) to generate one or more output signals in response to a relative arrival time of the first and second intermediate signals and (ii) to clamp a later arriving one of the first and second intermediate signals to a predefined voltage level.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: The invention relates to a new phase detector state machine having a reset state that is released only when both phase detector input signals (R, V) have a common predetermined signal state. In this way, phase inversion is effectively prevented. The complementary phase erros is properly masked and the phase detector range is reduced to the interval −180°<&thgr;e<180°, while still maintaining the direction sensitivity. Phase errors &thgr;e larger than half a period are automatically discarded. Consequently, if the phase detector ends up in a state, for example due to reference clock loss, in which the phase error is larger than half a period, the phase detector will be shifted back to normal operation with a phase error less than half a period during the next consecutive phase comparison period. Naturally, this saves valuable time in the lock-acquisition procedure.

Abstract: To conserve power in a circuit where a high-speed signal HSIG controls combinational logic (10), while a low-speed signal LCLK drives a logic/memory circuit (12) that samples the output of the combinational logic, predictive logic state machine (14) generates a clock, P_LCLK, which has an active level preceding the active edge of LCLK by a period sufficient to allow the combinational logic to reach the desired state prior to the active edge of LCLK and, preferably, allows for possible jitter in LCLK. Responsive to P_LCLK, the signal suspend circuitry (16) either passes HSIG or gates off HSIG. Further reductions in power can be accomplished by predicting which portions of the logic/memory circuit (12) will be used, and clocking those portions.