Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A phase correction circuit for correcting an antiphase component of a one-dimensional input signal is provided. The circuit contains a phase tracker, an antiphase detector, and an antiphase corrector. The phase tracker detects a decision error in the one-dimensional input signal having a phase error and outputs a phase-corrected signal in response to the decision error. The antiphase detector detects whether or not the phase-corrected signal is in antiphase and outputs a corresponding phase control signal. The antiphase corrector corrects a phase of the phase-corrected signal in accordance with the phase control signal. A method for performed by the phase correction circuit is also provided.

Abstract: A phase detector operating in a low voltage environment and providing a substantially constant integral voltage over variations in temperature, supply voltage and process parameters. The quadrature phase detector includes an equalizer, a switching unit, a sampler and comparator unit and a bias generator. The bias generator includes a switched capacitor structure which produces a bias current which tracks fluctuations in capacitance values due to temperature, supply voltage and process variations. The errors introduced due to fluctuations in bias current and capacitance are thus minimized.

Abstract: A frequency shift detection circuit for detecting a frequency shift between a first signal and a second signal includes two or more delay circuits coupled to one another in series and two or more comparison logic circuits. The first delay circuit in the series receives one of the first and second signals and produces a delayed replica. Each of the other delay circuits receives the delayed replica produced by the previous delay circuit in the series and produces a further delayed replica. Thus, the signal produced by each delay circuit is delayed from the original signal by a different amount. Each comparison logic circuit receives one of the delayed replicas and receives the other one of the first and second signals, i.e., the one that is not received by the delay circuits. In response, the comparison logic circuit produces a frequency shift detection signal when it detects a phase difference between that other one of said first and second signals and the delayed replica.

Abstract: A phase-frequency detector (110) includes an output stage (300) and a control stage (200). The output stage includes a pump up switched current source (350), a pump down switched current sink (360), and a constant current source (325) that are coupled to a charge pump output node (111). The control stage generates, in response to a divided variable frequency signal (FV) (136) and a reference frequency signal (FR) (106), a pump up control signal (246) and a pump down control signal (216).

Abstract: A phase detector produces a pulsed tri-state output signal representing a phase difference between first and second input signals. The pulse width of the output signal indicates the magnitude of the phase difference while the sign of the output signal pulses indicates whether the first input signal leads or lags the second input signal. The first and second input signals drive D and clock inputs, respectively, of a type D flip-flop, and also drive separate inputs of an XOR gate. An output of the flip-flop provides a signal input to a tristate buffer while an output of the XOR gate drives a tri-state control input of the tristate buffer. The tristate buffer produces the phase detector output signal.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a phase frequency detector (PFD) including two clock input ports, an up signal output port, and a down signal output port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up signal and a down signal based, at least in part, upon the magnitude of an amount of phase delay between two clock signals respectively applied to the PFD input ports. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a phase frequency detector (PFD) including two clock input ports, an up signal output port, and a down signal output port.

Abstract: A phase error signal generator including a phase comparator for comparing phases of two input pulse signals, change over the output polarity according to phase lead and lag between said input pulse signals, and output an electric charge proportional to a time difference between said input pulse signals, an alternating front stage capacitor for charging an electric charge according to said time difference, a base-grounded transistor of which emitter is coupled to said front stage capacitor, a rear stage capacitor coupled to the collector of said transistor, and a switch controller for biasing said transistor until the next edges arrive after detecting the edges corresponding to said two input pulse signals, wherein an integrating voltages of phase error of said two input pulse signals is obtained from said rear stage capacitor by transferring the electric charge proportional to the time difference information of each edge of the input pulse signal generated in said front stage capacitor in order.

Abstract: A method of performing phase-frequency comparison comprising the steps of receiving first and second clock signals; comparing the signals by triggering flip-flop circuits controlled by AND gates, and providing a first output when first signal is in advance of the second signal, and a second output when second signal is advance of the first signal.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

Abstract: An asynchronous digital phase detector. The digital phase detector includes an asynchronous state machine which simulates an edge triggered J-K flip flop. Additionally, the digital phase detector includes a reset line. The asynchronous state machine is implemented with logic which provides for optimal phase detector sensitivity and minimal dead zone. The logic within the digital phase detector is implemented with pass-transistors. The channel widths of the pass-transistors are selectively widened or narrowed to further increase the sensitivity of the phase detector.

Abstract: The present invention is directed to providing a phase detector capable of establishing phase-locked-loop operation in a highly accurate and reliable manner. For example, exemplary embodiments detect a phase difference between at least two input signals to phase lock the input signals to one another. Exemplary embodiments include two phase detectors each of which receives the two input signals (e.g., three-state phase detectors), and each of which is forced to operate outside of its dead-band region by introducing predetermined phase delays for its inputs. Each of the two phase detectors detects a phase difference between its respective inputs. The two phase differences are then combined to produce a composite output signal formed as a net charge proportional to the net phase difference detected by the two phase detectors.

Abstract: A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Abstract: A low-cost microstrip phase detector that is photo-etched onto a circuit board is disclosed. The phase detector is used to detect the phase difference between two high-power radio frequency (RF) signals. One RF signal enters a delay line causing the signal to experience a 180.degree. phase shift. The other RF signal is not phase shifted. Both RF signals are then input into a Wilkinson combiner circuit. The structure of the Wilkinson combiner is such that there is no voltage output from the combiner when the two input signals are exactly 180.degree. out of phase. When the original signals (before the delay line) are in-phase, there is no voltage output from the combiner. However, when the original signals are out-of-phase to begin with, they do not enter the Wilkinson combiner with a 180.degree. phase difference. Instead, the phase difference is greater than or less than 180.degree., depending on whether one input signal leads or lags the other input signal.

Abstract: A phase detector provides a digital output having a linear relationship to the phase difference between a reference signal and an applied input signal. The phase detector counts the number of cycles of the reference signal within a time interval determined by the difference in arrival times of corresponding amplitude transitions of the reference signal and the input signal. A digital output representing the number of counted cycles is produced. A dither generator adds random time variation to the time interval over which the reference signal cycles are counted to introduce a corresponding random variation in the digital output.

Abstract: A method and an apparatus for detecting differential threshold levels of a differential signal being carried in first and second lines while compensating for baseline wander. In one embodiment, first and second single-ended signals and a common mode signal are generated in response to the first and second lines. First and second peak signals are then generated in response to the first and second single-ended signals and the common mode signal. Finally, first and second threshold signals are generated which are compared with the first and second single-ended signals to generate first and second output signals indicating first and second differential threshold levels.

Abstract: A symmetric capture range is produced in a two-quadrant phase detector phase locked loop that utilizes nonsymmetric pulse waves. The phase detector is enabled only during VCO pulses. A latch stores the relative relationship between the leading edge of the input pulse and the center of the VCO pulse in the previous cycle. If the phase angle .theta. form the VCO pulse center to the leading edge of the input pulse is0 deg<.theta.<180 deg,then the phase detector incrementally decreases the VCO frequency at the next VCO pulse. If the phase angle .theta. is180 deg<.theta.<360 deg,then the phase detector incrementally increases the VCO frequency at the next VCO pulse.

Abstract: A ring oscillator is an oscillator, which is composed of serially connected buffers, for outputting a plurality of phases, and a last buffer output is inverted and fed back to a first buffer. A decoder selects one of outputs from the ring oscillator according to externally supplied digital data indicating an amount of a delay time to be set. A counter counts an output from the decoder, and outputs a delay signal if a count value reaches a predetermined number. That is, the counter outputs a signal with an amount of delay time according to digital data.

Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A circuit for detecting the phase angle of a three-phase alternating current includes a plurality of low-pass filters installed at each input port for removing noise and high-frequency signals mixed in an alternating current input signal, a plurality of multipliers each for multiplying the signal output from each of the low-pass filter by a feedback signal, a subtracter for receiving the signals output from the plurality of multipliers and calculating an error between two signals, a loop filter for receiving the signal output from the subtracter and filtering the same, an integrator for receiving the signal output from the loop filter, time-integrating the same, and outputting an estimated digital phase angle signal, and a phase delay compensator installed between the subtracter and the loop filter, for compensating for phase delay of the input signal caused by the low-pass filters.

Abstract: A quadrature phase detector includes a first load and a current source circuit. A first differential circuit and a second differential circuit coupled to the first load. In response to a first input signal, a first switching circuit couples the current source to the first differential circuit to form a first differential amplifier. The first switching circuit also couples the current source to the second differential circuit to form a second differential amplifier. The second differential amplifier is cross-coupled to the first differential amplifier. The first and second differential amplifiers are coupled to receive a differential second input signal, wherein the first and second input signals have a substantially different signal swing. A second switching circuit couples the current source to a second load in response to the complement of the first input signal.

Abstract: A phase detection signal is generated with a phase detection logic pipeline and its associated tapped pipeline signal combinational logic circuit. The phase detection logic pipeline generates phase detection logic pipeline output signals from a first input clock signal and a second input clock signal. The first input clock signal is applied to a first flip-flop of a set of serially connected flip-flops to generate a pipeline signal. The pipeline signal is driven through the set of serially connected flip-flops by the second clock input signal. Logic pipeline output nodes connected between the serially connected flip-flops carry the phase detection logic pipeline output signals. The phase detection logic pipeline output signals are applied to the tapped pipeline signal combinational logic circuit, which logically combines the signals to generate the phase detection signal.

Abstract: A phase comparator has a first comparing circuit and a second comparing circuit. The first comparing circuit produces a first output pulse having a duration equal to a phase lead of a first input signal with respect to a phase of a second input signal. The first phase comparator also produces a second output pulse equal in duration to a phase lag of the first input signal with respect to the phase of the second input signal. The second comparing circuit produces a third pulse equal in duration to a phase lead of a third input signal with respect to a phase of a fourth input signal. The second comparator also produces a fourth output pulse equal in duration to a phase lag of the third input signal with respect to the phase of the fourth input signal.

Abstract: A phase detector biased in a manner to alleviate the mismatch between the biasing current sources and the phase detector core bias currents. The bias setting resistors are coupled together at a common node that forms the negative input of a differential feedback amplifier. The positive input to the amplifier is referenced to a reference voltage, and the output of the amplifier controls the biasing current sources. The feedback amplifier forces the average voltage at the current source outputs to approximately match the reference voltage applied to its positive input. Thus the average bias current from the bias current sources is forced to track the average bias currents of the phase detector core.

Abstract: Methods and apparatus for switching a load between first and second sources is shown to include first and second solid state switches connected to the load. First and second mechanical breakers are connected between the switches and the sources so that each source is connected to the load through a circuit breaker and solid state switch. A controller is connected to sense the voltage from the first and second sources. The controller is connected to the first and second switches and the first and second mechanical breakers. The controller senses the phase difference between the voltages from the first and second sources. The controller causes the first and second mechanical breakers to open and close in response to sensing the phase difference between the sources. The first and second mechanical breakers can include medium voltage vacuum breakers.

Abstract: The level shift circuit of this invention includes two reference voltage level generation devices, and a difference between two reference voltage levels generated by these reference voltage level generation devices is used as a level shift voltage to be analog-added to an input analog signal. At least one of the two reference voltage level generation devices has a function to change the reference voltage level thereof in accordance with a supplied offset voltage adjusting signal, thereby changing the level shift voltage to be analog-added to the analog signal in accordance with the offset voltage adjusting signal. Thus, the level shift circuit achieves a function to adjust an offset voltage. When this level shift circuit is applied to a signal waveform generator, there is no need to provide the offset voltage adjusting function to a D/A converter. As a result, the power consumption as well as the circuit area of the signal waveform generator can be decreased.

Abstract: Internal node timing on an integrated circuit which is supplied with a clock signal from a system clock, the cycle time of which can be varied is measured by connecting a sequential element such as a latch to the node to measured and clocking it with a delayed measurement clock while increasing the clock cycle time. The output of the sequential element is an output pin of said integrated circuit. The measurement clock has the same cycle time as the system clock but has a latching edge delayed, the delay being at least 1.5 times the nominal system clock cycle time when it is desired to make measurement over both the high phase and low phase. The output pin is observed and the clock cycle time at which the sequential element fails to latch the current value determined. In a further embodiment, two sequential elements are used to make two measurements of this type and the difference between the two measurements is used to compute the time delay between the two nodes being measured. One node may be a clock node.

Abstract: An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

Abstract: A circuit is described for detecting a difference in phase and frequency between two incoming signals. Digital output signals are produced whose widths vary according to a degree of phase lead or phase lag of one signal with respect to the other. First sub-circuits are connected, one to each of the input signals to produce an output pulse of short duration, compared with a period of the incoming signal, at rising transitions of the associated input signal. Two resettable pulse detection circuits each have an output set to a first stable state when an active signal is received on a reset input and which change to a second stable state when a short duration pulse is received from one of the subcircuits on a pulse input. Further circuitry is connected such that when both outputs of the resettable pulse detection circuits are in the second stable state, an active reset signal is supplied to both resettable pulse detection circuits, to return both of their outputs to the first stable state.

Abstract: A device for determining the phase difference between a first and a second digital input signal (S1, S2) is disclosed. In a first embodiment, a clock signal (CLOCK) is supplied as a first counting signal (18) to a first counter (16), which is reset by the appearance of a predetermined edge (31) of the first input signal (S1). This embodiment permits phase measurement values in the range between zero and 360.degree. to be generated at a high measurement rate. In second and third embodiments, which are preferably connected and, if desired, combined with the first embodiment, second and third switching signals (FORWARD, BACK) are generated from the digital input signals (S1, S2) and are supplied to a forward-backward counter (20). The second and third embodiments are suited for determining phase differences between the two digital input signals (S1, S2) which are multiples of 360.degree..

Abstract: A phase detection circuit detects a phase relationship between a first clock signal, characterized by transitions of a given polarity (e.g., rising edges) at a first frequency, and a second clock signal, characterized by transitions of the given polarity at a second frequency that is an integer multiple of the first frequency. Transition indication circuitry generates a transition indication signal responsive to transitions, of the given polarity, of the second clock signal. The transition indication signal includes a transition indication (e.g., a pulse) corresponding to each n.sup.th transition, of the given polarity, of the second clock signal and at a phase that is selectable relative to the first clock signal in response to a transition indication control signal. Sampling circuitry (e.g., one or more latches) samples the transition indication signal responsive to each transition, of the given polarity, of the first clock signal to generate a transition indication sample.

Abstract: A self-timed phase detector for detecting the phase of an input signal, such as a high speed serial data stream. The self-timed phase detector includes a precharged latch, a phase detector circuit and a data valid gate. The precharged latch has a latch input, a sample clock input and first and second complementary latch outputs. The first and second complementary latch outputs have an active state and a precharged state. The phase detector circuit is coupled to the first latch output and generates a phase signal on a phase output as a function of the phase of the input signal. The data valid gate is coupled to the phase output for passing the phase signal when the latch outputs are in the active state and for blocking the phase signal when the latch outputs are in the precharged state.

Abstract: A method of measuring a delay time in a semiconductor device which has a particular circuit subject to delay time measurement, a test circuit coupled to an input terminal of the particular circuit for bypassing the particular circuit, and a selector for selectively outputting either an output signal from the particular circuit or an output signal from the test circuit.

Abstract: A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.

Abstract: A programmable phase comparator comprises a switch circuit operable in response to first and second signals to provide an output signal representative of the phase relationship of the first and second signals. A reference signal is applied to the switch circuit to offset the output signal. A phase adjustment adjusts the phase relationship of the first and second signals so that the offset output signal is representative of a null condition. The switch circuit preferably is a Gilbert multiplier having a current source, an impedance means, and a transistor circuit connected between the current source and the impedance means. The transistor circuit has first and second inputs for receiving the first and second signals. The reference signal is input between the transistor circuit and the impedance means and is connected to an output. The output provides the output signal having a value based on the reference signal and the phase relationship of the first and second signals.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.

Abstract: A signal processing apparatus is provided for processing first and second periodic analog signals having the same period and having a fixed phase relationship therebetween. The apparatus includes an A/D converter for converting respective amplitudes of the first and second periodic analog signals into first and second digital signals. The apparatus also includes a phase digitizer for generating a signal from the first periodic analog signal, the generated signal having a period that is shorter than the period of the first periodic analog signal, and a high speed signal processing portion for generating from the generated signal a periodicity and first phase information of the first periodic analog signal. The apparatus further includes a another signal processor for producing second phase information of the first periodic analog signal from the first and second digital signals, and for correcting the periodicity on the basis of the first phase information and the second phase information.

Abstract: A novel method and apparatus providing an all digital phase comparator of two binary signals which employs a type of cross correlation of two binary signals and provides a 2bit binary word uniquely representative of phase alignment. The method can be carried out using a pair of flip-flop (FF) circuits, each FF having a docking input and a data input, and where each FF has a delay in series with its data input.

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the damping circuit is an digital circuit which generates adequate phase and frequency damping without a damping resistor. Damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: It is an object of the present invention to provide a phase comparator which can compare phase at high speed with simple structure. The phase is compared by a precharge type NAND gate including transistors (Q35-Q37). The result of comparison in the NAND gate is then outputted only in a period in which the input clock CLKref is at "1" by the NAND gate (NA 15), and thus the phase lag of the internal clock CLKint with respect to the input clock CLKref is detected. Phase lead of the internal clock CLKint with respect to the input clock CLKref is compared with interchanged relation of clocks inputted to a phase detecting portion (PD 2). Phase comparison can be made at high speed with a simple circuit including the precharge type NAND gate and the NAND gate (NA 15).

Abstract: An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A phase comparing circuit includes a first device for generating a detection signal in response to a multi-level signal. The detection signal represents whether or not the multi-level signal is in a given level. A second device connected to the first device is operative for generating a first control signal in response to the detection signal generated by the first device and a clock signal. The first control signal represents a time interval between a leading edge of a pulse in the detection signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal. A third device connected to the first device is operative for generating a second control signal in response to the detection signal generated by the first device and the clock signal. The second control signal represents a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal.

Abstract: A pulse phase difference encoding circuit provides a digital signal indicating a phase difference between a first input pulse and a second input pulse. The first input pulse is provided to and circulated in a ring signal delay circuit having a plurality of signal delay elements that are connected in series. Intermediate points between the delay elements provide delayed pulses having different delay times. Upon receiving the second input pulse, a selector selects one delay pulse provided by the delay element at which the first input pulse has arrived, and generates a digital positional signal indicating a position of the selected delay element. The number of rounds of circulation of the first input pulse in the ring signal delay circuit is separately counted. According to the number of rounds of circulation of the first pulse and the positional signal, the digital signal indicating the phase difference between the first and second input pulses is formed.

Abstract: A digital phase comparator supplies digital values corresponding to the phase shifts between a first signal having a duty cycle of approximately 0.5 and a second signal. The comparator includes a one-way counter initialized at the frequency of the first signal and clocked by a clock signal having a high frequency with respect to the frequency of the first and second signals. A logic gate enables the counter when the first and second signals are in respective predetermined states. A phase shift is considered to be zero when it corresponds approximately to one half of the counter's capacity.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers.

Abstract: Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers.

Abstract: A virtual amplifier comprises a typical switched source follower circuit plus an additional switch of minimum size to perform a virtual amplification function. A capacitor is connected between the gate, which comprises a detector node, and the source, which comprises a source node, of a source follower FET. The source node is connected to the output by a first FET switch. The source node is also connected to a voltage source by a second FET switch. The voltage on the detector node is manipulated by pumping a charge into or out of the capacitor. Charge pumping is accomplished by first accumulating charge on the detector node while the source node is connected to the voltage source, and then switching the first FET switch on and the second FET switch off so that the effective capacitance of the detector node is reduced.