Abstract: An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current.

Abstract: The invention relates to a method and to an apparatus for protecting transistors (S1, S3; S2, S4) arranged in at least one path, wherein transistors (S1, S3; S2, S4) connected in series to which an input voltage (Ue) is applied are arranged in a path (2), and the transistors (S1, S3; S2, S4) of a path are alternately switched between a conductive state and a blocking state in order to generate an output voltage (Ua) at the center of the path. In order to prevent both transistors (S1, S3; S2, S4) of a path from triggering, the blocking state of the second transistor (S3; S4) of the path is checked before switching a transistor (S1; S2) into the conductive state, and the switching is released by way of a signal generated during the check.

Abstract: Methods, systems, and devices are described for an adjustment module that interacts with a parameter detection module to provide a threshold value for initiating switching of a switching module in a cyclical electronic system. Aspects of the present disclosure provide a switching module used in conjunction with an inductor that is coupled with the switching module. The threshold voltage for switching the switching module may be adjusted to provide switching at substantially zero volts while maintaining sufficient energy in the inductor to drive the voltage at a switching element in the switching module to zero volts. Such auto-adjustment circuits may allow for enhanced efficiency in cyclical electronic systems. The output of an up/down counter may be used to set another parameter that effects the performance of the cyclical electronic system in order to enhance the performance of the cyclical electronic system.

Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Abstract: Optimal operating techniques are disclosed for using coreless printed-circuit-board (PCB) transformers under (1) minimum input power conditions and (2) maximum energy efficiency conditions. The coreless PCB transformers should be operated at or near the ‘maximum impedance frequency’ (MIF) in order to reduce input power requirement. For maximum energy efficiency, the transformers should be at or near the “maximum efficiency frequency” (MEF) which is below the MIF. The operating principle has been confirmed by measurement and simulation. The proposed operating techniques can be applied to coreless PCB transformers in many circuits that have to meet stringent height requirements, for example to isolate the gates of power MOSFET and IGBT devices from the input power supply.

Abstract: A power switching circuit designed for operating in a radiation environment using non-radiation hardened components is provided. The power switching circuit provides a high-voltage rated, non-radiation hardened N-channel FET (N-FET) controlled by a relatively small, low-voltage, non-radiation hardened P-channel FET (P-FET), while both devices are operating in a radiation environment. The P-FET device is drive by a sufficiently high drive voltage in order to overcome gate threshold shifts resulting from accumulated radiation damage.

Abstract: A disconnecting apparatus for direct current interruption between a direct current source and an electrical device, in particular between a photovoltaic generator and an inverter, has a current-conducting mechanical switching contact and semiconductor electronics connected in parallel with the switching contact. The semiconductor electronics are non-conducting when the switching contact is closed, wherein a control input of the semiconductor electronics is wired with the switching contact in such a way that, when the switching contact opens, an arc voltage generated as a result of an arc via the switching contact switches the semiconductor electronics to become conducting.

Abstract: The present disclosure relates to a high voltage switch which may comprise a chain of MOS field-effect transistors (MOSFETs). The current of the individual MOSFETS, and hence the chain, can be controlled by means of adding a current measuring resistance into the source path of the transistors and transmitting the voltage arising there via a capacitor to a gate connector of the transistors.

Abstract: A semiconductor device comprises a first sense amplifier, first to third transmission lines, and first to third switches. The first and second transmission lines are connected to the first sense amplifier. The first and third switches control connections of the first to third transmission lines, and the second switch controls a connection between a fixed potential and third transmission line. When the second transmission line is not accessed, the first and third switches are brought into a non-conductive state and the second switch is brought into a conductive state, and the fixed potential is supplied to the third transmission line, thereby suppressing influence of the coupling noise between the transmission lines.

Abstract: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches.

Abstract: A method and circuit for high-speed current switching includes altering the operating voltage of the Current Source using a resistor in non-transmission mode, turning parasitic capacitive coupling into an advantage for faster settling of CS gate bias voltage. The resistor is designed to compensate for the voltage coupling when the Current Source is switched to Transmit mode. This greatly improves the settling time of current and bias voltage of the Current Source transistor without adding any complex circuit and saves 100% of power consumed in non-transmit mode.

Abstract: A power switch circuit providing voltage to an output port is provided. The switch circuit includes a single power supply, a switch unit, a controlling unit, and a logic unit. The switch unit is connected between the single power supply and an output port and capable of being turned on and off alternatively for continuing or discontinuing power from the single power supply to the output port; the single power supply provides power to the output port. The controlling unit is configured for generating a voltage controlling signal and transmitting the voltage controlling signal to the logic unit. The logic unit receives and inverts the voltage controlling signal, and outputs the inverted voltage controlling signal to turn on or turn off the switch unit.

Abstract: Interfaces for coupling an electronic device to a power source control element and devices therefrom are provided. An interface includes a single node that is configured to receive a state signal and a serial communication signal from the electronic device. The interface also includes a switch circuit that is configured for providing a control signal for the power source control element based on the state signal, the switch signal capable of being influenced by the receipt of the state signal and the serial communication signal at the single node. The interface further includes a switch buffer circuit coupling the single node to the switch circuit, the switch buffer circuit comprising an impedance network configured to prevent the serial communication signal from activating the switch circuit.

Abstract: An input/output circuit has a first load having one end coupled to a first standard voltage line, a first MOS transistor having a drain electrode coupled to another end of the first load, a second load having one end coupled to the first standard voltage line, a second MOS transistor having a drain electrode coupled to another end of the second load, a third MOS transistor having a source electrode each of which is coupled to source electrodes of the first and second MOS transistors, a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line, and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line. The circuit size is reduced by transmitting a differential signal or a single-ended signal using a single input/output circuit.

Abstract: A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

Abstract: A complementary high voltage switched current source circuit has a complementary current source pair, wherein a first of the current source pair is coupled to a positive voltage rail and a second of the current source pair is coupled to a negative voltage rail. A digital logic-level control interface circuit is coupled to the complementary current source pair and to the positive voltage rail and the negative voltage rail. A pair of high voltage switches is coupled to the complementary current source pair and the digital logic-level control interface circuit and controlled by the digital control interface circuit.

Abstract: An electrically insulated switching element driver includes: a pulse transformer driving unit into which a switching element driving signal and a duty signal are input and which drives, in accordance with the duty signal, a first or second pulse transformer that is selected depending on a state of the switching element driving signal; a first edge detection unit that outputs an on-off signal according to an edge in a pre-rectification output of the first pulse transformer; a second edge detection unit that outputs an on-off signal according to an edge in a pre-rectification output of the second pulse transformer; and a control driving unit that drives a switching element to be driven, based on the output of the first and second edge detection units, wherein the first and second edge detection units and the control driving unit operate with power resulting from rectifying the output of the first and second pulse transformers.

Abstract: An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor.

Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.

Abstract: In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

Abstract: The various embodiments of the present disclosure relate generally to inverse-mode Radio-Frequency (“RF”) switching circuits and methods of using the same. An embodiment of the present invention provides an inverse-mode RF switching circuit. The inverse-mode RF switching circuit comprises a bipolar transistor, a shunt element, a first RF channel, and a second RF channel. The bipolar transistor comprises a base, a collector, and an emitter, wherein the base and emitter are in electrical communication first via a base-emitter junction and second via an electrical connection element. The shunt element is in electrical communication with the collector. The first RF channel is in electrical communication with the base and emitter. The second RF channel is in electrical communication with the collector and the shunt element. The base-collector junction operates as a switching diode between the first RF channel and the second RF channel.

Abstract: A system for event detection uses a resistive switching device to record a detected event. The resistive switching device has a resistance adjustable by means of an applied voltage. The operation of the resistive switching device is controlled by a controller, which is configured to apply a switching voltage to the resistive switching device at a start time, and turn off the switching voltage in response to an event signal indicative of occurrence of an event. The resistance value of the resistive switching device resulting from the application of the switching voltage is indicative of the detection of the event and also the time of the occurrence of the event.

Abstract: Provided is a reference voltage circuit having a soft start function, which is small in circuit size and is capable of providing a continuous voltage. The reference voltage circuit includes a reference voltage section and a soft start circuit. The reference voltage section includes a depletion mode MOS transistor and a first enhancement mode MOS transistor. The soft start circuit includes: a second enhancement mode MOS transistor having a gate connected to a gate and a drain of the first enhancement mode MOS transistor, and a drain connected to an output terminal of the reference voltage circuit; a MOS switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode MOS transistor; and a constant current source and a capacitor connected in series between a power supply and a ground.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: A switching device has a main IGFET having a Schottky barrier diode D3 for blocking an inverse current built therein, a protective switch means, and a protective switch control means. The protective switch means is connected in between a drain electrode D and a gate electrode G of the main IGFET. The protective switch control means turns on the protective switch means when an inverse voltage is impressed to the main IGFET. Thereby, the main IGFET is protected from the inverse voltage.

Abstract: A plurality of normally-open pushbutton switches are coupled to and cooperate with a pair of MOSFETs to provide each pushbutton switch of the plurality of pushbutton switches with a power on switch function for a personal audio device that does not require power to be drawn from a power source to monitor each of the pushbutton switches or to identify which of the pushbutton switches was manually operated to power on the personal audio device while awaiting operation of one of the pushbutton switches to cause the personal audio device to be powered on.

Abstract: A gate driving circuit for a voltage-driven power semiconductor switching device has (a) the voltage-driven power semiconductor switching device, (b) a driving circuit for supplying a drive signal to the gate electrode of the switching device, and (c) an inductance between the emitter control terminal or source control terminal of the switching device and the emitter main terminal or source main terminal of a semiconductor module. A voltage produced across the inductance is detected. The gate-driving voltage or gate drive resistance is made variable based on the detected value.

Abstract: Electrically isolating the gate terminals of a pair of semiconductor output devices increases the switching speed of a solid state relay. A time delay enables tuning of the isolated gate circuits facilitating simultaneous operation of the output devices.

Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a condition state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.

Abstract: An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: A MOSFET main switch transistor has a pull-down FET coupled between a drain thereof and the gate of the main switch transistor. A gate of the pull-down FET is coupled to the drain of the main switch transistor by a capacitor and is connected to a source thereof by a resistor. The pull-down FET is operated by capacitive coupling to the voltage drop across the main switch and can be used to hold the gate of the main switch transistor at or near its source potential to avoid or reduce unintentional turn-on of the main switch transistor by the Miller effect.

Abstract: A solid-state alternating current (AC) switch provides for the sequential turn-on of the associated solid-state switches to reduce the generation of electromagnetic interference (EMI). The solid-state AC switch includes at least first and second solid-state switches connected in series between an AC input and an AC load. A zero-cross detector circuit monitors the AC input to determine zero-crossings associated with the monitored AC input. A controller turns on the first solid-state switch and the second solid-state switch according to a turn-on sequence in which the first transistor is turned ON during a detected zero-crossing window associated with the first transistor and the second transistor is subsequently turned ON during a detected zero-crossing associated with the second transistor.

Abstract: An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.

Abstract: Provided is an SPDT switch having improved isolation characteristics in an RF band. The SPDT switch includes a serial switching unit, a current sink unit, a switching isolation unit, and a DC blocking unit. The serial switching unit includes first and second HBTs. The current sink unit sinks a current flowing from a common input terminal to each of first and second output terminals of the serial switching unit. The switching isolation unit causes an unselected output terminal of the first and second output terminals to be electrically isolated from the common input terminal when the serial switching unit operates. The DC blocking unit blocks a DC between the first HBT and the first output terminal and a DC between the second HBT and the second output terminal. Accordingly, it is possible to provide better insertion-loss and isolation characteristics in higher frequency bands than typical switches.

Abstract: A semiconductor switch circuit is provided that enables current consumption to be reduced even in a conduction state. A semiconductor switch circuit 100 has P-type MOS transistors Q101 and Q102 for conduction that share a source and are connected in series between an input/output terminal 101 and input/output terminal 102, a P-type MOS transistor Q103 and N-type MOS transistor Q105 having drains connected to the gate of Q101, a P-type MOS transistor Q104 and N-type MOS transistor Q106 having drains connected to the gate of Q102, and a control terminal 103 connected to the gates of the transistors. Further semiconductor switch circuit 100 is configured with the sources and back gates of Q103 and Q104 connected to the sources of Q101 and Q102. Therefore, it is possible to switch the path between input/output terminal 101 and input/output terminal 102 between a conduction state and non-conduction state by means of voltage control by voltage value Vcont of a control signal applied to control terminal 103.

Abstract: An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

Abstract: Semiconductor relays switch power supplied from a power source to drive loads, and further detect current values of electric currents flowing through the loads. A control section intermittently turns ON the semiconductor relays via driving circuits, thereby limiting electric power consumption of the loads. Further, the control section calculates, based on the current values detected by the semiconductor relays, load electric power consumption of the loads, and estimated electric power consumption of the loads when the semiconductor relays are continuously ON, and allows a display section to display, as a value indicative of an energy-saving effect, an electric power amount difference i.e. a saved electric energy that is based on an electric power difference obtained by subtracting the load electric power consumption from the estimated electric power consumption.

Abstract: A bootstrapped switch circuit can include a switch transistor, having a drain configured as an input terminal to receive an input signal, and a voltage-controlled voltage source, configured to provide predetermined constant voltages between a gate and a source of the switch transistor in response to a control signal received at a control terminal. The predetermined constant voltages can include a first predetermined constant voltage to turn on the switch transistor and pass the input signal to the source and a second predetermined constant voltage to turn off the switch transistor. The first and second predetermined constant voltages can be independent of the magnitude of a signal passed to the source of the switch transistor based on the input signal at the drain.

Abstract: A current reference source circuit that is independent of power supply which is used for producing a current reference source that is independent of power supply, the circuit at least includes a resistor Rs and a mirror image circuit which is formed with four MOSs, M1, M2, M3, M4, there is another mirror circuit branch besides the mirror circuit, the current of the resistor Rs, the present invention modifies the traditional current reference source circuit that is independent of power supply, the derived current formula adds one adjustable parameter M, so as to make the design more flexible, so that when a very small reference current is required, it can be achieved by keeping the W/L of the NMOS and the resistor Rs, and simply increasing parameter M in the extra mirror circuit branch.

Abstract: A first terminal T1 is connected to the drain (or the source) of a MOS-FET (Q11), whose back gate is separated, through a capacitor C11. The MOS-FET (Q11) is connected at the source (or the drain) thereof to a second terminal T2. The back gate is connected to the source (or the drain). A control voltage VG is supplied to the gate of the MOS-FET (Q11), and a voltage having a polarity reversed from that of this control voltage VG is supplied to the drain through a resistance element R12.

Abstract: A low-side driver circuit includes a low-side driver integrated circuit and a controllable switch. The low-side driver integrated circuit is responsive to an on-off command input signal to selectively operate in an ON mode and an OFF mode. The controllable switch is responsive to the on-off command signal to selectively operate in a CLOSED mode and an OPEN mode. The low-side driver integrated circuit and the controllable switch are configured to simultaneously operate in the ON mode and the CLOSED mode, respectively, and in the OFF mode and the OPEN mode, respectively. During a voltage transient the potential will be realized across the controllable switch, thus protecting the lower voltage rated low-side integrated circuit.

Abstract: A power insulated gate field effect transistor has main cells (2) controlled by a main cell insulated gate and sense cells (4) controlled by a sense cell insulated gate. A sample and hold circuit (10, 50) is arranged to operate in a plurality of states including at least one sample state and a hold state to sense the current flowing through the sense cells (4) when in the at least one sample state but not in the hold state. The sample states may be used in a feedback loop to control a drive amplifier (20) driving the gates of the main and sense cells (2,4) and/or to mirror the current in the sense cells (4) on a measurement output terminal (58).

Abstract: A PV system may be used in case of emergencies. Each individual photovoltaic module receives a signal to determine if it is allowed to be operational or must shut down. Modules by default are shut off and safe to handle, absent the signal and in the presence of light.

Abstract: A load driving circuit and a multi-load feedback circuit is disclosed. The load driving circuit and the multi-load feedback circuit are adapted to drive a LED module that has a current balancing circuit for balancing the currents flowing through LEDs. The load driving circuit and the multi-load feedback circuit modules the electric power transmitted by the LED driving apparatus to a LED module according to voltage level(s) of current balancing terminals having insufficient voltage in the current balancing circuit, and so the voltage levels of the current balancing terminals are higher than or equal to a preset voltage level, further increasing the efficiency thereof.

Abstract: The invention concerns a method of determining the dissipated power of an electronic switch. According to the invention it is proposed that the instantaneous value of a physical quantity is detected, a value correlated with the instantaneous value is polled from a first memory, the two values are processed together in a predetermined manner and the result of the processing operation is outputted.

Abstract: A dynamically self-bootstrapping circuit for a switch features a resistor in series with the control node of the switch. A bypass switch connects a control node to ground. When the switch is in an off-state, the bypass switch is enabled.

Abstract: An exemplary power supply control circuit includes a first electric switch, a second electric switch, a third electric switch, a power supply, and an output terminal. The first electric switch has a first terminal connected to an SIO chip to receive a control signal. When the control signal is at a high level, the first electric switch is turned on, the second electric switch is turned off, the third electric switch is turned off, and the output terminal outputs no power supply. When the control signal is at a low level, the first electric switch is turned off, the second electric switch is turned on, the third electric switch is turned on, and the output terminal outputs the power supply.

Abstract: A high-frequency switch circuit includes: a switch section comprised of a field effect transistor having a plurality of bias circuits and a potential generating circuit for generating bias voltages from a control signal and supplying them to the bias circuits. The field effect transistor forms the passage route of a high-frequency signal by turning on and off in accordance with the control signal. The bias circuits are provided to produce a potential difference between the drain terminal and the source terminal of the field effect transistor and to apply bias voltages lower than the voltage of the control signal to the drain terminal, and the source terminal.

Abstract: The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.