Abstract: An analog switch including at least one first MOS transistor capable of transferring a signal from a first terminal to a second terminal; a connection circuit for bringing a substrate terminal of the first transistor to a voltage which is a function of the voltages of the first and second terminals; and a circuit for controlling a control voltage of the first transistor with the signal.

Abstract: A switch circuit for switching between a first storage and a second storage. The switch circuit includes a switch, a control circuit, a switch control chip, and a processing chip. The control circuit is connected to the switch, the first storage, and the second storage. The control circuit either transmits power from a power supply to the first or second storage according to the switch. The switch control chip is connected to the control circuit. The processing chip is connected to the switch control chip. The control circuit controls the switch control chip to either transmit data between the processing chip and the first storage in response to the power supply powering the first storage, or transmit data between the processing chip and the second storage in response to the power supply powering the second storage.

Abstract: A High Voltage switch configuration having an input terminal which receives an input signal and an output terminal which issues an output signal to a load. The High Voltage switch configuration comprises at least a first and a second diode, being placed in antiseries between said input and output terminals and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node.

Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.

Abstract: This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

Abstract: A load controller includes: an input circuit which detects that a drive instruction signal is less or equal to a first input threshold value; a constant current source activated in accordance with a detection by the input circuit; a PWM signal generating unit that is activated by the constant current source and generates a PWM signal; a comparator that is activated by the constant current source and compares the drive instruction signal with a second input threshold value set to be lower than the first input threshold value; a logic calculation unit that carries out a logic calculation of the PWM signal with a compared result of the comparator; a drive control unit that operates in accordance with an output from the logic calculation unit to generate a PWM drive control signal; and a load driving element that is driven by the PWM drive control signal to control a load.

Abstract: Provided is a semiconductor device which avoids an adverse effect of high temperatures due to a switching element and in which a circuit to prevent false firing is arranged on the same substrate as the switching element. An N-channel type MOSFET 10 and a JFET 30 of an N-channel type containing a semiconductor material of silicon carbide are individually arranged in proximity on conductive patterns 51, 52 on a substrate 5, and a gate electrode 13 of the MOSFET 10 and a drain electrode 31 of the JFET 30 are connected by a lead 61. When an external drive signal for on/off control of MOSFET 10 propagates between source electrode 32 and drain electrode 31 of JFET 30, the channel resistance of JFET 30 is changed to a large/small value according to a low/high level of gate voltage between source electrode 32 and gate electrode 33, whereby a leading edge of a switching waveform between drain electrode 11 and source electrode 12 of MOSFET 10 comes to have a gentler slope than a trailing edge thereof.

Abstract: The semiconductor circuit has a power supply voltage generation circuit; a first circuit having a transistor that is connected to the power supply voltage generation circuit, and that varies a drain current value by utilizing the degree of freedom of an electron spin to vary the spin states of the source and the drain; and a main function circuit that is connected to the first circuit, and has a main function. Operation/non-operation of the main function circuit is selected by the drain current value. The operating speed of the circuit can thereby be adjusted through a simple circuit structure.

Abstract: A power switch circuit providing voltage to an output port is provided. The switch circuit includes a single power supply, a switch unit, a controlling unit, and a logic unit. The switch unit is connected between the single power supply and an output port and capable of being turned on and off alternatively for continuing or discontinuing power from the single power supply to the output port; the single power supply provides power to the output port. The controlling unit is configured for generating a voltage controlling signal and transmitting the voltage controlling signal to the logic unit. The logic unit receives and inverts the voltage controlling signal, and outputs the inverted voltage controlling signal to turn on or turn off the switch unit.

Abstract: A power supply switch apparatus includes a main outlet, first and second load outlets, a manual switch, and first and second electronic switches. The positive terminal of the main outlet is connected to the positive terminal of the first load outlet and connected to the second terminal of the first electronic switch. The third terminal of the first electronic switch is connected to the positive terminal of the second load outlet. The first terminal of the first electronic switch is connected to the second terminal of the second electronic switch and connected to a voltage terminal through a first resistor. The third terminal of the second electronic switch is grounded. The first terminal of the second electronic switch is connected to the voltage terminal through the manual switch and a second resistor in that order, and grounded through a third resistor.

Abstract: A semiconductor device that makes isolation circuits unnecessary and that also resolves the problem of through-current flowing during power supply shutdown transitions and during power supply recovery and that even flows between the regions during power shutdown. A semiconductor device of the present invention including a first power supply line, and a second power supply line coupled to a first power supply line by way of a first switch, a macro cell containing a macro cell core coupled to the second power supply line, and a third power supply line coupled by way of a second switch to a first power supply line, and a circuit block coupled to the third power supply line and also coupled to at least either the macro cell core input or output; and the second power supply line is coupled to the third power supply line.

Abstract: Systems and methods in accordance with embodiments of the invention are disclosed that include MOSFET transistor operation by adjusting Vbs, or the voltage applied to the body terminal of the MOSFET transistor, to control the threshold voltage (Vth) in order to minimize leakage current and increase response time. One embodiment includes a n-channel metal-oxide-semiconductor field-effect transistor (NMOS), including: a gate terminal; a source terminal; a drain terminal; a body terminal; and control circuitry, where the control circuitry is configured to bias the body terminal at a first voltage when voltage applied to the gate terminal turns the transistor OFF and a second voltage when voltage applied to the gate terminal turns the transistor ON; and where the first voltage is of a lower value than the second voltage.

Abstract: An inverter is capable of improving the reliability of driving. The inverter includes a first transistor and a second transistor. The first transistor is coupled between a first power source and an output terminal of the inverter, and has a first gate electrode coupled to a first input terminal of the inverter and a second gate electrode coupled to a third power source. The second transistor is coupled between the output terminal and a second power source, and has a first gate electrode coupled to a second input terminal of the inverter and a second gate electrode coupled to the third power source.

Abstract: A power supply control circuit comprises an output transistor 32 which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor based on an external input signal. A first discharge path includes a first depletion-type N-channel MOS transistor provided between a gate and a source of the output transistor and discharges a gate charge of the output transistor based on the control signals, when turning off the output transistor. A second discharge path includes a first depletion-type N-channel MOS transistor discharges more slowly than the first discharge path. A diode is coupled to the first depletion-type N-channel MOS transistor in series and detects that a gate voltage of the output transistor has fallen to a prescribed voltage level, and cuts off a first discharge path.

Abstract: A polycrystalline diamond abrasive element, particularly a cutting element, comprises a table of polycrystalline diamond bonded to a substrate, particularly a cemented carbide substrate, along a non-planar interface. The polycrystalline diamond abrasive element is characterized by the nonplanar interface having a cruciform configuration, the polycrystalline diamond having a high wear-resistance, and the polycrystalline diamond having a region adjacent the working surface lean in catalysing material and a region rich in catalysing material. The polycrystalline diamond cutters have improved wear resistance, impact strength and cutter life than prior art cutters.

Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.

Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

Abstract: A driver chip for driving an inductive load and a module having a driver chip are provided. The driver chip contains a first transistor for coupling a first potential to a first output and a second transistor for coupling a second potential to the first output. A first protection circuit reduces an increased voltage between a control terminal and a load junction terminal of the first transistor. The driver chip has a first state in which the second transistor is turned off and the first transistor can switch a passive inductive load connected to the output. In a second state, the first transistor and the second transistor can switch an external power transistor connected to the first output. A second output is connected to a load junction terminal of the external power transistor. A second protection circuit reduces an increased voltage between the first and second outputs.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOT MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: An analog T switch is disclosed which has high isolation in the off state. The analog T switch can include series-connected NMOS transistors having separate gate control. The gates of the NMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog switch can include series-connected PMOS transistors having separate gate control. The gates of the PMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog T switch can include a substrate voltage control circuit that controls the voltage of the substrate regions in which the PMOS transistors are formed. The substrate voltage control circuit can isolate the substrate regions of the PMOS transistors from one another in the off state to improve off state isolation of the analog T switch.

Abstract: A transistor-based switch is coupled to a replica circuit that includes transistor circuitry similar to that of the switch. The replica circuit biases a switched transistor to promote linear operation of the switch.

Abstract: An analog switch includes a transistor having a current path between an input and an output, a gate coupled to a control terminal, and a bulk terminal, and a switched bulk control circuit coupled to the control terminal, the bulk terminal, and ground to reduce an equivalent capacitance seen from a source terminal or drain terminal of the transistor towards the bulk terminal of the transistor. The bulk control circuit includes an all-NMOS bulk control circuit if an NMOS transistor switch is used.

Abstract: A circuit is for generating a signal that indicates whether or not an input current exceeds a pre-established threshold current and, in the affirmative case, that is representative of the difference between the input current and the threshold current. The circuit includes a diode-connected transistor biased with a first constant current in a saturation functioning condition, a sense transistor mirrored to the diode-connected transistor and biased in a linear (triode) functioning condition, a load transistor connected in series to the sense transistor, biased with a second constant current and the control terminal of which is connected in common with the respective terminals of the diode-connected transistor and of the sense transistor. The input current to be compared is injected to a common current node of the load transistor and of the sense transistor, and the output voltage is available on the other current node of the load transistor.

Abstract: A power supply control circuit for a motherboard of a computer is provided. The power supply control circuit includes a south bridge chip and a voltage output control circuit connected to the south bridge chip. The south bridge chip includes a control pin and a detecting pin. The voltage output control circuit has a voltage input terminal and a voltage output terminal. The voltage output control circuit includes a transistor connected to the voltage input terminal and also connected to the voltage output terminal via a switch component. The voltage output terminal is connected to the detecting pin of the south bridge chip via a super I/O chip. The transistor is capable of controlling the switch component to transmit a high level voltage to the super I/O chip when the computer is shut down. A method is also provided.

Abstract: A power supply switch apparatus includes a main outlet, first and second load outlets, a manual switch, and first and second electronic switches. The positive terminal of the main outlet is connected to the positive terminal of the first load outlet and connected to the second terminal of the first electronic switch. The third terminal of the first electronic switch is connected to the positive terminal of the second load outlet. The first terminal of the first electronic switch is connected to the second terminal of the second electronic switch and connected to a voltage terminal through a first resistor. The third terminal of the second electronic switch is grounded. The first terminal of the second electronic switch is connected to the voltage terminal through the manual switch and a second resistor in that order, and grounded through a third resistor.

Abstract: There is provided a high frequency switching circuit having good characteristics of high-order harmonics that has little variation. A high frequency switching circuit according to an aspect of the invention may include: a high frequency switch having one end connected to an input terminal receiving a high frequency signal and the other end connected to an output terminal of the high frequency signal, the high frequency switch turned on or off by a control signal; and a capacitor having a predetermined capacitance, and having one end connected the output terminal and the other end connected to a ground by a bonding wire.

Abstract: Method for operating a converter circuit with voltage boosting with N half-bridges, which in each case can be connected by their center connection to a phase of an N-phase generator and at an end side are connected in parallel with a series circuit formed by two capacitances, wherein each half-bridge contains a Top switch and a Bot switch, in which, in a PWM method with a fixed period duration at the beginning of the period duration, all the TOP switches are simultaneously switched on for the duration of a TOP switched-on interval. After half the period duration all the BOT switches are simultaneously switched on for the duration of a BOT switched-on interval wherein the TOP switched-on interval, and the BOT switched-on interval amount at most to half the duration of the period.

Abstract: A power control module including a socket, a switch circuit and an interface control circuit is provided. A plug is adapted to be inserted into the socket, and the socket has a positive terminal, a first negative terminal and a second negative terminal. When the plug is inserted into the socket, a negative terminal of the plug sequentially contacts the first negative terminal and the second negative terminal. The switch circuit receives a power voltage through the positive terminal. The interface control circuit determines whether to generate a switching signal to the switch circuit according to a voltage level of the second negative terminal. When receiving the switching signal, the switch circuit outputs the power voltage.

Abstract: A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors.

Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.

Abstract: A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.

Abstract: A switching device for switching a current between a first terminal (1) and a second terminal (2) comprises a cascode circuit having a series connection of a first semiconductor switch (M) and a second semiconductor switch (J), wherein the two semiconductor switches (M, J) are connected to each other by a common point (13), and the first semiconductor switch (M) is controlled by way of a first control input in accordance with a voltage between the first control input and the first terminal (1), and the second semiconductor switch (J) is controlled by way of a second control input (4) in accordance with a voltage between the second control input (4) and the common point (13). To this end, a control circuit having a specifiable capacitance (C) is connected between the second terminal (2) and at least one of the control input.

Abstract: A low voltage drop unidirectional electronic valve constituted of: a first terminal; a second terminal; a first electronically controlled switch coupled between the first terminal and the second terminal; and a first charge pump arranged to close the first electronically controlled switch when the voltage potential at the first terminal is greater than the voltage potential at the second terminal by a first value. The first charge pump is arranged in a closed loop with the first electronically controlled switch so as to continuously maintain the voltage potential at the first terminal greater than the voltage potential at the second terminal by the first value.

Abstract: A power semiconductor device has: an output transistor connected between a power-supply terminal and an output terminal; a gate charge-discharge circuit configured to charge/discharge a first node connected to a gate of the output transistor to ON/OFF control the output transistor; a short switch circuit connected between the first node and the output terminal; and a short control circuit configured to control the short switch circuit. In the turn-ON period, the ON period and the turn-OFF period, the short control circuit cuts off electrical connection between the first node and the output terminal through the short switch circuit. In the OFF period, the short control circuit electrically connects the first node and the output terminal through the short switch circuit.

Abstract: A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor ‘off’ for all values of the input signal when the switch signal is ‘low.’ A programmable gain amplifier (PGA) is also provided. The PGA may include an input stage having an input node to couple an input signal, and an output node to provide a gate signal, at least a first gain stage including a resistor and a switch circuit as above. A differential gain amplifier may be included to provide an output signal from the gain signal.

Abstract: A semiconductor device includes a MOS transistor switch that controls passage and interruption of a signal by switching between an ON state and an OFF state, a first switch connected between a back gate terminal of the MOS transistor switch and a source terminal of the MOS transistor switch, and a second switch connected between the back gate terminal of the MOS transistor switch and a power supply voltage terminal If the MOS transistor switch is in the ON state, the first switch is in the ON state and the back gate terminal of the MOS transistor switch is connected to the source terminal of the MOS transistor switch. If the MOS transistor switch is in the OFF state, the second switch is in the ON state, and the back gate terminal of the MOS transistor switch is connected to the power supply voltage terminal.

Abstract: The present invention is directed to reduce increase in the level of a harmonic signal of an RF (transmission) Tx output signal at the time of supplying an RF Tx signal to a bias generation circuit of an antenna switch. A semiconductor integrated circuit includes an antenna switch having a bias generation circuit, a Tx switch, and an antenna switch having a bias generation circuit, a transmitter switch, and a receiver (Rx) switch. The on/off state of a transistor of a Tx switch coupled between a Tx port and an I/O port is controlled by a Tx control bias. The on/off state of the transistors of the Rx switch coupled between the I/O port and a receiver (Rx) port is controlled by an RX control bias. A radio frequency (RF) signal input port of the bias generation circuit is coupled to the Tx port, and a negative DC output bias generated from a DC output port can be supplied to a gate control port of transistors of the Rx switch.

Abstract: A high frequency switch circuit according to the present invention includes a control-voltage-generating circuit. The control-voltage-generating circuit includes a depletion type field-effect transistor, an external-control-signal-input terminal, an internal-control-voltage-output terminal, and a power-receiving terminal of the control-voltage-generating circuit. The field-effect transistor has a grounded gate, a source connected to the external-control-signal-input terminal, and a drain connected to the power-receiving terminal. The internal-control-voltage-output terminal is connected to an electrical connection path between the drain of the field-effect transistor and the power-receiving terminal.

Abstract: A bidirectional switch device includes a main pass field effect transistor (FET) connected to an input node and an output node. A body region of the first main pass transistor is tied to a voltage substantially halfway between the voltage at the input node side of the first main pass transistor and the voltage at the output node side of the transistor when the first main pass transistor is in an ON state.

Abstract: An analog signal is input to an input terminal. An analog signal is output via an output terminal. A first transistor is an N-channel MOSFET, and is provided between the input terminal and the output terminal. A first resistor is provided between the gate of the first transistor and a first fixed voltage terminal (power supply terminal), which sets the gate of the first transistor to a high-impedance state.

Abstract: A switch includes, a common terminal, a first terminal, a second terminal, a first FET having a first source, a first drain and a first gate, one of the first source and the first drain being coupled to the common terminal, the other of the first source and the first drain being coupled to the first terminal, and a second FET having a second source, a second drain and a second gate, one of the second source and the second drain being coupled to the common terminal, the other of the second source and the second drain being coupled to the second terminal. The first FET is controlled to a turn-off state by an absolute voltage of the first gate which is smaller than an absolute voltage of the second gate to control a turning-off state for the second transistor.

Abstract: A gate drive apparatus including a constant-current-pulse gate drive circuit which creates a gate signal for a switching device as a constant-current output, a constant-voltage-pulse gate drive circuit which creates the gate signal as a constant-voltage output, and a decision/switch circuit which switches the operation of the constant-current-pulse gate drive circuit and the operation of the constant-voltage-pulse gate drive circuit. The variance of switching speeds attributed to the variances of threshold voltages and mirror voltages in a plurality of switching devices which are driven by the gate drive apparatus can be suppressed, and the variance of losses can be minimized.

Abstract: A power supply circuit for protecting a battery from current leakage when the battery is not in use includes a control signal input circuit and a switch circuit. The control signal input circuit receives a first control signal from a chip and output a second control signal. The switch circuit receives the second control signal and turns on or off an electronic connection between the battery and the chip. Wherein when the battery is not in use and not being charged by the adaptor, there is a possibility of current leakage from the battery. In such case, the switch circuit turns off the electronic connection between the battery and the chip, and the battery does not provide power to the chip.

Abstract: An electromechanical device is disclosed. The device includes a variable capacitor, and a switch circuit configured to pre-charge an input node with a pulse charge at said selected voltage level. The switch circuit includes only a first switch coupled to the variable capacitor and the first switch is configured to respond to an enable signal having a duration shorter than a mechanical time constant of the variable capacitor and the first switch is configured to apply the selected voltage level across the variable capacitor to cause the pulse charge to accumulate on the variable capacitor.

Abstract: A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

Abstract: A signal line from a common terminal, which allows the insertion of a terminal of a cable for transmitting high-frequency signals or the insertion of a terminal of a cable dedicated to the transmission of audio signals, is branched into one line which is connected to one end of a high-frequency signal switch (USB switch) and the other line which is connected to one end of an audio signal switch (audio switch), respectively. A signal line from the other end of the high-frequency signal switch is connected to a target circuit. A signal line from the other end of the audio signal switch in a primary hierarchical position is branched into a plurality of lines, and the respective plurality of lines are connected to one end of audio signal switches (e.g., headphone switch and microphone switch) in a secondary hierarchical position. And the respective signal lines from the other end of the plurality of audio signal switches of secondary hierarchical position are connected to respective target circuits.

Abstract: In a bidirectional switch using a metal-oxide-semiconductor field-effect transistor (MOSFET), the source terminal and the backgate terminal of the MOSFET are connected to each other via a transfer gate. A switch may be used between the connection point of the backgate terminal and the transfer gate of the MOSFET and the ground potential (where the MOSFET is an n-channel type) or supply potential (where the MOSFET is a p-channel type).

Abstract: Apparatus and method for switching audio amplification. In an embodiment, an apparatus for switching audio amplification includes an output circuit. The output circuit is coupled to a plurality of different voltage potentials and a first voltage potential, and outputs an output signal to drive a load, wherein each of the different voltage potentials is greater than the first voltage potential. In an exemplary embodiment, a control circuit controls the output circuit to generate the output signal based on one of the different voltage potentials and first voltage potential selectively so as to enable the output signal to switch between any two adjacent corresponding voltage levels of the different voltage potentials and the first voltage potential.

Abstract: According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.