Having Particular Substrate Biasing Patents (Class 327/534)
  • Patent number: 7786793
    Abstract: Disclosed herein is a semiconductor integrated circuit including a stoppable circuit unit configured to be alternately switched between a stopped state and an operating state; a first voltage line configured to apply a first voltage to the stoppable circuit unit when the stoppable circuit unit is in the operating state; a second voltage line configured to apply the first voltage to the stoppable circuit unit when the stoppable circuit unit is in a transient state of switching from the stopped state to the operating state; and a third voltage line configured to apply a second voltage to the stoppable circuit unit.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: August 31, 2010
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Publication number: 20100214006
    Abstract: There is provided a circuit whose output is free from high impedance to improve wrong transmission and waveform overshoot, realizing a semiconductor integrated circuit device in which plural channels is integrated with transmitter circuit as unit channel, in the transmitter circuit used in a medical ultrasound system and drives a transducer by voltage pulses having plural positive and negative electric potentials including ground potential. The transmitter circuit includes a conventional pulse generating circuit supplied with positive and negative voltage largest in absolute value, a P-channel analog switching pulse generating circuit supplied with positive voltage being the second largest therein, an N-channel analog switching pulse generating circuit supplied with negative voltage being the second largest, and an N-channel analog switching ground level damping circuit supplied with ground potential. The circuits are connected to output terminal.
    Type: Application
    Filed: January 11, 2010
    Publication date: August 26, 2010
    Inventors: Satoshi HANAZAWA, Toshio Shinomiya, Hiroyasu Yoshizawa
  • Publication number: 20100214009
    Abstract: A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements.
    Type: Application
    Filed: February 23, 2009
    Publication date: August 26, 2010
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventor: Paul S. Fechner
  • Patent number: 7782110
    Abstract: Systems and methods for integrated circuits comprising multiple body bias domains. In accordance with a first embodiment of the present invention, an integrated circuit is constructed comprising active semiconductor devices in first and second body bias domains. A first body biasing voltage is coupled to the first body bias domain, and a second body biasing voltage is coupled to the second body bias domain. The first and the second body biasing voltages are adjusted to achieve a desirable relative performance between the active semiconductor devices in the first and the second body bias domains.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: August 24, 2010
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Patent number: 7782090
    Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: August 24, 2010
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Publication number: 20100207683
    Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 19, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
  • Publication number: 20100201434
    Abstract: A control circuit for substrate potential regulation for an integrated circuit device. The control circuit includes a current source configured to generate a reference current. A variable resistor is coupled to the current source. The variable resistor is configured to receive the reference current and generate a reference voltage at a node between the current source and the variable resistor. The reference voltage controls the operation of a substrate potential regulation circuit coupled to the node.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 12, 2010
    Inventor: Tien-Min Chen
  • Patent number: 7772917
    Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: August 10, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kiyoo Itoh, HIroyuki Mizuno
  • Patent number: 7772916
    Abstract: An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 10, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Hyuk Im
  • Publication number: 20100194451
    Abstract: A method is disclosed for controlling an IGBT component and a gate driver. An exemplary method includes producing, with two separate driver circuits, a gate voltage for controlling the IGBT component, the outputs of the driver circuits being connected to free ends of a series connection of resistive components. A location, such as a midpoint between the series connection, forms the gate voltage.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 5, 2010
    Applicant: ABB OY
    Inventor: Leo NUUTINEN
  • Patent number: 7768299
    Abstract: Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: August 3, 2010
    Assignee: QUALCOMM, Incorporated
    Inventors: Abheek Gupta, Vaishnav Srinivas, Vivek Mohan
  • Publication number: 20100188377
    Abstract: A light-emitting device includes a light-emitting element that emits light of an amount based on the size of a driving current; a driving transistor, the gate thereof being electrically connected to a first node, that outputs a current flowing between the drain-source as the driving current; and a control unit that supplies a first data potential to the first node and supplies a current to the driving transistor so as to set the voltage between the gate and source of the driving transistor to a compensated voltage based on the mobility of the driving transistor, and then supplies a second data potential determined in accordance with the first data potential to the first node.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 29, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hitoshi OTA, Satoshi YATABE, Hideto ISHIGURO
  • Patent number: 7760009
    Abstract: A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Lin Yang, Hsin-Hsin Ko, Chung-Cheng Chou
  • Patent number: 7760007
    Abstract: A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 20, 2010
    Assignee: Nuvoton Technology Corporation
    Inventor: Peter Holzmann
  • Publication number: 20100177232
    Abstract: A voltage biasing circuit includes a metal-oxide-semiconductor (MOS) transistor, a voltage control circuit controlling a voltage between a gate and a source of the MOS transistor to operate the MOS transistor in a sub-threshold range, and a capacitor connected to the MOS transistor. The voltage biasing circuit may further include a voltage buffer connected between the voltage control circuit and the MOS transistor.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 15, 2010
    Inventor: Jin Hyuck YU
  • Patent number: 7755395
    Abstract: An inverter circuit for generating an output signal at an output node obtained by inverting an input signal level at an input node includes a common-source MOS transistor having a gate node connected to the input node, a source connected to a predetermined voltage and a substrate gate, a load resistor connected in series with the MOS transistor, and a resistor connected between the gate node and the substrate gate of the MOS transistor.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: July 13, 2010
    Assignee: Ricoh Company, Ltd.
    Inventors: Kohji Yoshii, Yasutaka Shimizu
  • Patent number: 7750677
    Abstract: A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Andres Bryant, Wilfried Haensch
  • Patent number: 7750682
    Abstract: A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Andres Bryant, Wilfried Haensch
  • Patent number: 7750719
    Abstract: A driving circuit is provided by the invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between an operation voltage and a power supply terminal of the first buffer for controlling a power-supplying time of the first buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: July 6, 2010
    Assignee: Himax Technologies Limited
    Inventor: Yu-Wen Chiou
  • Patent number: 7746160
    Abstract: Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: June 29, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vijay Kumar Srinivasa Raghavan, Iulian Gradinariu
  • Patent number: 7746154
    Abstract: A multi-voltage multiplexer system includes multiple voltage inputs, each voltage input providing a different input voltage, and multiple control inputs operative to select one of the input voltages for output. Each of multiple transistors is connected to a different one of the voltage inputs and to a different one of the control inputs, and the transistors are connected to an output such that the selected input voltage is provided at the output. A bulk of each of the transistors is connected together to form a bulk network, and the bulk network is connected to the gate of each transistor such that the transistors connected to non-selected voltage inputs have gates set at approximately the maximum of the input voltages.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: June 29, 2010
    Assignee: Atmel Corporation
    Inventors: Marc Merandat, Jean-Blaise Pierres, Jerome Pratlong, Stephane Ricard
  • Publication number: 20100156510
    Abstract: First doped semiconductor regions having the same type doping as a bottom semiconductor layer and second doped semiconductor regions having an opposite type doping are formed directly underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. The first doped semiconductor regions and the second doped semiconductor regions are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6 V to 0.8V.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Edward J. Nowak, James A. Slinkman
  • Publication number: 20100142263
    Abstract: A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided that has a collector, a base and an emitter. The body region of the MOS transistor serves as the base of the bipolar transistor and the drain region of the MOS transistor serves as the collector of the bipolar transistor. Activation of the MOS transistor causes the bipolar transistor to turn on. The MOS transistor is activated to turn on the bipolar transistor and the bipolar transistor delivers current to the source region.
    Type: Application
    Filed: February 17, 2010
    Publication date: June 10, 2010
    Inventor: Hyun-Jin Cho
  • Publication number: 20100141330
    Abstract: A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 10, 2010
    Inventors: Ping-Lin Yang, Hsin-Hsin Ko, Chung-Cheng Chou
  • Patent number: 7733730
    Abstract: A negative voltage detection circuit including first and second MOS transistor circuits configured to change a dimension size of a transistor based on a control signal, a first comparator circuit, a gate electrode of the second MOS transistor circuit commonly coupled to the gate electrode of the first MOS transistor circuit forming a current mirror circuit, a resistive divider supplied with a negative voltage to be detected, and coupled to the end of the current path of the second MOS transistor circuit to generate a second voltage, a second voltage comparator circuit to compare the second voltage with a reference voltage and to generate a detection signal corresponding to the value of the negative voltage, and a detection circuit for detecting a temperature or power supply voltage, generate the control signal corresponding to the detection result, and supply the control signal to the first and second MOS transistor circuits.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: June 8, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Hashiba
  • Patent number: 7733159
    Abstract: Circuits, methods, and apparatus for limiting voltages received by devices in input/output cells to less than the device's breakdown voltage. An exemplary embodiment of the present invention provides an input/output cell having one or more clamp diodes and resistors configured to limit voltages seen by the gates of the devices in the input/output cell. In one embodiment, the clamp diodes are on-chip, while the resistors are off-chip. In a specific embodiment, the clamp diode is connected between an input pad for the input output cell and a supply voltage VCC, while a resistor is off-chip and in series with the input pad. In another specific embodiment, a series of clamp diodes are coupled between ground and an input pad, while a resistor is off-chip and in series with the input pad. In another embodiment, the clamp diode or diodes may be programmably or selectively disconnected. These clamp diodes may be disabled to protect against latch-up.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: June 8, 2010
    Assignee: Altera Corporation
    Inventors: Rafael Camarota, John Costello, Myron Wong
  • Patent number: 7728648
    Abstract: A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: June 1, 2010
    Assignee: Qimonda AG
    Inventors: Alessandro Minzoni, Thilo Schaffroth
  • Patent number: 7728649
    Abstract: An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 1, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Robert W. Webb, Gregg D. Croft
  • Publication number: 20100127759
    Abstract: Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 27, 2010
    Inventors: Sang-moo Choi, Won-joo Kim, Tae-hee Lee
  • Patent number: 7724069
    Abstract: A switch circuit, which selectively couples first and second switch nodes together and which enables the first and second switch nodes to operate in an extended voltage range, includes a secondary voltage rail, a switch device, a body driver, a rail control switch, and a switch control circuit. The rail control switch clamps the secondary voltage rail to a primary voltage rail during normal voltage range operation, but otherwise releases the secondary voltage rail to float. The body driver clamps the body of the switch to the secondary voltage rail when turned on, and when turned off, forward biases to allow voltage of said secondary voltage rail to follow voltage of the switch nodes into the extended voltage range through the switch. The switch control circuit includes a latch circuit which ensures that the switch remains either turned on or turned off during extended voltage operation.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: May 25, 2010
    Assignee: Intersil Americas Inc.
    Inventor: Robert W. Webb
  • Patent number: 7724039
    Abstract: A conversion circuit for converting a differential signal into a single-phase signal 1 has a source-follower amplifier 10 and a source-grounded amplifier 20. The source-follower amplifier 10 outputs a non-inverted signal IN of the differential signal the phase of which is not inverted. The source-grounded amplifier 20 inverts an inverted signal INX of the differential signal and adjusts its phase to that of the non-inverted signal IN. At point A, differential signals IN, INX are added and output as a single-phase signal OUT.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: May 25, 2010
    Assignee: Fujitsu Limited
    Inventor: Tomoyuki Arai
  • Publication number: 20100123121
    Abstract: An array of thyristor detector devices is provided having an epitaxial growth structure with complementary types of modulation doped quantum well interfaces located between a P+ layer and an N+ layer. The thyristor detector devices operate over successive cycles that each include a sequence of two distinct modes: a setup mode and a signal acquisition mode. During the setup mode, the n-type quantum well interface and/or the p-type quantum well interface is(are) substantially emptied of charge. During the signal acquisition mode, photocurrent is generated by the thyristor detector device in response to the absorption of incident electromagnetic radiation therein, which can induce the thyristor detector device to switch from an OFF state to an ON state. The OFF/ON state of the thyristor detector device produces an output digital electrical data that corresponds to the amount of incident radiation absorbed by the thyristor detector device during the signal acquisition mode of the current cycle.
    Type: Application
    Filed: March 18, 2008
    Publication date: May 20, 2010
    Inventor: Geoff W. Taylor
  • Patent number: 7719347
    Abstract: In related arts, a body voltage needs to be controlled by separately detecting external environment such as temperature. In the related art, variation such as a process parameter for each individual product has not been considered. A semiconductor integrated circuit according to the present invention includes a comparator comparing a leak current of a first conductive type transistor with a leak current of a second conductive type transistor to output a comparing result, and a conduction control signal generator outputting a signal determining a conduction state of the first conductive type transistor and a conduction state of the second conductive type transistor in a power saving control target circuit in a power saving mode based on the comparing result.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: May 18, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideki Sugimoto
  • Publication number: 20100117717
    Abstract: Provided is a semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation thereof. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.
    Type: Application
    Filed: January 12, 2010
    Publication date: May 13, 2010
    Applicant: Panasonic Corporation
    Inventors: Masaya Sumita, Shirou Sakiyama, Masayoshi Kinoshita
  • Publication number: 20100117718
    Abstract: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor.
    Type: Application
    Filed: January 15, 2010
    Publication date: May 13, 2010
    Applicant: POWER INTEGRATIONS, INC.
    Inventor: Donald R. Disney
  • Patent number: 7714652
    Abstract: A method and circuit for changing a threshold voltage of a transistor. The circuit includes a sense circuit coupled to a switching transistor, a circuit transistor and to one terminal of a resistor. The other terminal of the resistor is connected to a body contact. The switching transistor directs current along one of two different paths in response to an input voltage sensed by the sense circuit. When the switching transistor directs a first current along one path, the first current is steered towards the resistor and flows through the resistor in one direction and when the switching transistor directs a second current along the other path, the second current is directed towards the resistor and flows through the resistor in the opposite direction from the first current. Steering the currents varies the potential of a body with respect to the potential at the source of the circuit transistor.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: May 11, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Aravind Mangudi, Eric David Joseph, Mahbub Hasan
  • Patent number: 7714606
    Abstract: A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: May 11, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Osamu Ozawa, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu
  • Patent number: 7714638
    Abstract: An arrangement, to ease restriction upon gate voltage (Vgg) magnitudes for a dynamic threshold MOS (DTMOS) transistor, may include: an MOS transistor including a gate and a body; and a body-bias-voltage (Vbb) governor (Vbb-governor) circuit to provide a governed version of Vgg of the MOS transistor to the body of the MOS transistor as a dynamic body bias-voltage (Vbb).
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyukju Ryu, Heesung Kang, Kyungsoo Kim
  • Patent number: 7714642
    Abstract: The present invention provides an integrated virtual voltage circuit for use with a sub-circuit. In one embodiment, the integrated virtual voltage circuit includes a MOS transistor switch coupled to a supply voltage and configured to employ a drain to provide an operating voltage for the sub-circuit during switch activation. Additionally, the integrated virtual voltage circuit also includes a connection unit coupled to the MOS transistor switch and configured to provide a standby voltage for the sub-circuit during deactivation of the MOS transistor switch wherein the standby voltage is based on a static coupling of the drain to a body region of the MOS transistor switch. In an alternative embodiment, the connection unit is further configured to connect a voltage reference between the supply voltage and the drain of the MOS transistor switch to determine the standby voltage.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: May 11, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew Marshall, Theodore W. Houston
  • Publication number: 20100109756
    Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.
    Type: Application
    Filed: January 13, 2010
    Publication date: May 6, 2010
    Inventors: Hiroaki NAKAYA, Satoru AKIYAMA, Tomonori SEKIGUCHI, Riichiro TAKEMURA
  • Publication number: 20100109755
    Abstract: A semiconductor device capable of improving the breakdown voltage in the overall device is provided. The semiconductor device includes: a semiconductor substrate; a p-MOS formed on a surface layer portion of the semiconductor substrate; an n-MOS formed on the surface layer portion of the semiconductor substrate and serially connected with the p-MOS between a power source and a ground; and a substrate potential control circuit for controlling the potential of the back surface of the semiconductor substrate to an intermediate potential higher than the ground potential and lower than the potential of the power source.
    Type: Application
    Filed: April 11, 2008
    Publication date: May 6, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Hiroshi Kumano, Eiji Nakagawa
  • Patent number: 7710191
    Abstract: A semiconductor integrated circuit device 100A includes: an integrated circuit body 106A having a plurality of MOSFETs on a semiconductor substrate; a plurality of elements 102A to be measured placed on the same substrate as the plurality of MOSFETs; a monitor circuit 105A for selecting an element to be measured whose measured parameter value is in a predetermined rank among the plurality of elements 102A to be measured as an element 101A to be measured for monitoring; and an operation parameter adjustment circuit 107 for adjusting an operation parameter 108 supplied to the integrated circuit body 106A based on the measured parameter 104A of the element to be measured for monitoring.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: May 4, 2010
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Inada, Akio Hirata
  • Publication number: 20100102872
    Abstract: This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor.
    Type: Application
    Filed: October 29, 2008
    Publication date: April 29, 2010
    Inventors: Wei-Hao Wu, Anthony Oates
  • Publication number: 20100102871
    Abstract: An electronic circuit and a method for controlling a power field effect transistor. The electronic circuit comprises a power field effect transistor having a semiconductor body, which has a drain zone, a drift zone, a source zone and a bulk zone. The power field effect transistor further comprises a gate and a field plate. The field plate is placed adjacent to the drift zone and is isolated from the drift zone. A switch circuitry is provided for electrically connecting the field plate depending on the drain-source voltage such that the field plate is electrically connected to the drain zone, if |UDS|>UT, where UT is a predetermined voltage, and if |UDS|>UT, the field plate is connected to an electrode having an electrode-source voltage UES.
    Type: Application
    Filed: October 27, 2008
    Publication date: April 29, 2010
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Wolfgang Werner
  • Patent number: 7705660
    Abstract: A substrate bias voltage detection unit compares a level of a substrate bias voltage with a reference voltage in response to a self-refresh signal, an idle signal, and a refresh count signal so as to output an oscillating driving signal, enables the oscillating driving signal when the substrate bias voltage is equal to or higher than a first level in a normal mode, disables the oscillating driving signal when the substrate bias voltage is at a second level in a self-refresh mode, and disables the oscillating driving signal when the substrate bias voltage is at a third level in the self-refresh mode. An oscillation unit outputs an oscillating signal according to the oscillating driving signal. A voltage pumping unit controls pumping of the substrate bias voltage according to an output signal of the oscillation unit and then outputs a pumped substrate bias voltage.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: April 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Won Lee
  • Publication number: 20100097124
    Abstract: Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.
    Type: Application
    Filed: July 30, 2009
    Publication date: April 22, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-moo Choi, Won-joo Kim, Tae-hee Lee, Dae-kil Cha
  • Publication number: 20100097127
    Abstract: A voltage supply circuit includes a booster circuit and a ripple filter circuit. The ripple filter circuit has a first resistor connected to a first output terminal at one end thereof. The ripple filter circuit also has a first switch circuit connected between the other end of the first resistor and a second output terminal. In addition, the ripple filter circuit has a second switch circuit connected between the first output terminal of the booster circuit and the first switch circuit.
    Type: Application
    Filed: December 23, 2009
    Publication date: April 22, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi MAEJIMA
  • Patent number: 7701280
    Abstract: To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: April 20, 2010
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7696811
    Abstract: A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Corey Kenneth Barrows, Douglas W. Kemerer, Stephen Gerard Shuma, Douglas Willard Stout, Oscar Conrad Strohacker, Mark Steven Styduhar, Paul Steven Zuchowski
  • Publication number: 20100085109
    Abstract: A first terminal T1 is connected to the drain (or the source) of a MOS-FET (Q11), whose back gate is separated, through a capacitor C11. The MOS-FET (Q11) is connected at the source (or the drain) thereof to a second terminal T2. The back gate is connected to the source (or the drain). A control voltage VG is supplied to the gate of the MOS-FET (Q11), and a voltage having a polarity reversed from that of this control voltage VG is supplied to the drain through a resistance element R12.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 8, 2010
    Applicant: SONY CORPORATION
    Inventor: Taiwa Okanobu