Abstract: A voltage generating apparatus is provided. The voltage generating apparatus includes a reference voltage generator and an output voltage generator. The reference voltage generator is used for generating a reference voltage, and the reference voltage generator decides to generate the reference voltage or not according to a control signal. The output voltage generator includes a comparator, a variable resistor and a current source. The comparator compares the reference voltage and an output voltage to generator a calibrating signal. A resistance of the variable resistor is decided by the calibrating signal. The current source provides an output current to flow through the variable resistor for generating the output voltage. Wherein, the reference voltage is generated during an initial timing period, and the generator is turned off after the initial timing period. The initial timing period is determined according to the control signal.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: A boost converter for driving the gate of n-channel MOSFET power devices is described. The boost converter includes a monitoring circuit and a kick start circuit to quickly bring the boost converter online when required to drive the MOSFET on.

Abstract: The voltage generator provided by the present invention includes: a first current source, a second current source, a first resistor, a reference voltage generator, a first amplifier and a second amplifier. The first current source generates a first current and a second current with a first temperature coefficient according to a first bias voltage. The second current source generates a third current and a fourth current with a second temperature coefficient according to a second bias voltage. The reference voltage generator provides a first reference voltage and a second reference voltage according to the first and third currents. The first amplifier generates the first bias voltage according to the first and second reference voltages. The second amplifier generates the second bias voltage according to the second and third reference voltages. Wherein, the first temperature coefficient and the second temperature coefficient are complementary.

Abstract: The semiconductor device includes: a first transistor controlled by a control signal; a sense voltage generating circuit for sensing current flowing through the first transistor, mirroring current flowing through a reference current circuit, and summing the currents to generate voltage based on the summed currents; a reference voltage circuit for mirroring current flowing through the reference current circuit and generating reference voltage; an amplifier for comparing the voltage generated by the sense voltage generating circuit and the reference voltage; and a second transistor which has a gate connected to an output terminal of the amplifier and which can turn off the first transistor.

Abstract: A bias voltage generation circuit includes a first current source connected to a first power source; a first transistor which is diode connected and is connected to the first current source; a second transistor connected between the first transistor and a second power source; a second current source connected to the first power source; a third transistor connected to the second current source; a fourth transistor connected between the third transistor and the second power source; a first output point connected to the first transistor and the third transistor and outputs a first bias voltage; a second output point connected to the fourth transistor and the second current source and outputs a second bias voltage; and a bias voltage adjusting circuit which adjusts the first bias voltage in accordance with a control input.

Abstract: A semiconductor device includes; a first pad that receives an external voltage during a test, a second pad coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and generating a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, such that the level of the test current is defined by the level of the bias current.

Abstract: Aspects of the present disclosure relate to a current multiplier that can generate an output current with high linearity and/or high temperature compensation. Such current multipliers can be implemented by complementary metal oxide semiconductor (CMOS) circuit elements. In one embodiment, the current multiplier can include a current divider and a core current multiplier. The current divider can generate a divided current by dividing an input current by an adjustable division ratio. The division ratio can be adjusted, for example, based on a comparison of the input current with a reference current. The core current multiplier can generate the output current based on multiplying the divided current and a different current. According to certain embodiments, the output current can be maintained within a predetermined range as the input current to the current divider varies within a relatively wide range.

Abstract: A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1<VR1, the microcomputer turns off the first switch, and turns on/off the second switch to gradually increase a voltage V3 of the power supply node. Thus, the operation of a clock generation circuit driven by V3 can be stable even when V3 is changed from V1 to V2.

Abstract: In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.

Abstract: A control circuit for a power converter is disclosed, having a shared pin, a driving circuit, a current source, a sampling circuit, and a signal processing circuit. The shared pin is used for coupling with an output end of the power converter through a resistor. The driving circuit is used for conducting a switch of the power converter. The current source provides a current to the resistor through the shared pin. The sampling circuit samples the signal on the shared pin for generating a first sampling value and a second sampling value. When the difference between the first sampling value and the second sampling value is less than a predetermined value, the signal processing circuit configures the driving circuit to adjust at least one of the conduction time and the conduction frequency of the switch according to an output signal of the power converter received from the shared pin.

Abstract: Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.

Abstract: A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module and/or the integrated circuit. A third circuit module may, for example, determine power control information based at least in part on the monitored performance characteristic(s). The power control information may be communicated to power supply circuitry to control various characteristics of the electrical power. Various aspects of the present invention may also comprise an integrated circuit comprising a first module that monitors at least one performance characteristic of a first electrical device.

Abstract: A control circuit for a power converter includes a shared pin, a driving circuit, a current source, a sampling circuit, and a signal processing circuit. The shared pin is coupled with an output end of the power converter through a resistor. The driving circuit conducts a switch of the power converter. The current source provides a current to the resistor through the shared pin. The sampling circuit samples the signal on the shared pin for generating a first sampling value and a second sampling value. The signal processing circuit calculates a first difference between the first sampling value and a first reference value, and a second difference between the second sampling value and a second reference value. When the difference between the first difference and the second difference is less than a predetermined value, the signal processing circuit may therefore configure the conduction time or frequency of the switch.

Abstract: A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.

Abstract: An electronic device comprises a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter, and a second component having an on-state and an off-state. The electronic device further comprises a time estimator for updating an estimate of an accumulated time the second component was in the on-state; and a controller for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. The first component and the second component may be the same, or the first component may have an on-state correlated to the on-state of the second component. The operating parameter may, for example, be a level or amplitude or correction value of one of the following: a voltage applied at the first component, an electric current fed to the first component, and a power provided to the first component. A method of operating such an electronic device is also disclosed.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.

Abstract: A reference voltage generator includes a first transistor and a second transistor coupled in series between a current supply and ground. Gate insulating films of the first transistor and the second transistor are made of the same type of film with the same thickness. Impurities contained in gate electrodes of the first transistor and the second transistor have different conductivity types, or have the same conductivity type and different concentrations. The first transistor has a greater gate width than the second transistor. The first transistor and the second transistor operate in a subthreshold region when a reference voltage is output outside.

Abstract: Sharp fluctuations of an internal voltage when an internal voltage generating circuit is activated or inactivated are prevented. The internal voltage generating circuit to supply the internal voltage generated from an external voltage to an internal power supply line, a control circuit to control an operation of the internal voltage generating circuit, and a voltage detection circuit to detect a level of a first voltage are included. When, for example, the internal voltage generating circuit is activated, the control circuit stepwise increases supply ability of the internal voltage at a first speed and when the internal voltage generating circuit is inactivated, the control circuit stepwise reduces the supply ability of the internal voltage at a second speed that is different from the first speed. Accordingly, wild fluctuations of the internal voltage when the internal voltage generating circuit is activated/inactivated can optimally be prevented for each case.

Abstract: An integrated circuit includes a high voltage transistor having a first terminal coupled to sense a high voltage terminal and a control terminal coupled to a regulated voltage, which is regulated with respect to a ground terminal and is substantially less than a high voltage that the high voltage terminal is adapted to withstand. A logic gate is also included and is coupled to be powered from the regulated voltage. The logic gate has an input threshold that is less than the regulated voltage. An input terminal of the logic gate is coupled to a second terminal of the high voltage transistor. An output of the logic gate is coupled to indicate that a voltage sensed between the high voltage terminal and the ground terminal is less than the input threshold voltage of the logic gate.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22, TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Abstract: A controlled current source comprises a signal input to receive a control input bus signal (D0, . . . , D[n?1]), a mapping unit (MU) with an input coupled to the signal input and an output to provide an internal control bus signal (d0, . . . , dn, Hc), a reference generator (RG) with an input coupled to the output of the mapping unit (MU) and with a low reference output to provide a low reference potential (Vgl) and with a high reference output to provide a high reference potential (Vgh), a current generating unit (CG) with a first input coupled to the output of the mapping unit (MU), a second input coupled to the output of the reference generator (RG) and an output to provide an output current (Iout) controlled by the control input bus signal (D0, . . . , D[n?1]) and the low and high reference potentials (Vgh, Vgl). Furthermore, a method for sourcing a current is provided.

Abstract: Offset calibration technique to improve performance of band gap voltage reference. An example of a bandgap reference source includes an output resistor, a first and second transistors and a differential amplifier. A positive-input calibration phase switch is in communication with a positive amplifier input, a emitter of the first and second transistor and a negative-input calibration phase switch in communication with the negative amplifier input, the emitter of the first and second transistor. A positive-output calibration phase switch is in communication with the positive amplifier output, the first and second terminal of the output resistor and a negative-output calibration phase switch is in communication with the negative amplifier output, the first and second terminal of the output resistor. An adjustable resistance is in communication with the emitter of the first transistor, the emitter of the second transistor, and the second terminal of the output resistor.

Abstract: System and method system for regulating voltage in a portion of an integrated circuit. An integrated circuit has a voltage input and at least a portion that is less than all of the integrated circuit, which requires a local voltage level. A voltage selector establishes a target voltage for the portion. A first comparator compares the target voltage to the local voltage and generates a pull up control signal when the local voltage is below the target voltage. A second comparator compares the target voltage to the local voltage and generates a pull down control signal when the local voltage is above the target voltage. A pull up device, responsive to the pull up control signal, increases the local voltage according to the pull up control signal. A pull down device, responsive to the pull down control signal, decreases the local voltage level according to the pull down control signal.

Abstract: A method for generating a reference voltage in an integrated circuit device that is powered by a low voltage power includes generating a coarse first reference voltage using a coarse reference generator, routing the coarse first reference voltage to a boost regulator as an input reference voltage by a hand-off switch circuit, the boost regulator generating an initial-state stepped-up supply based on the first reference voltage, and generating at least two outputs of a second, more accurate, reference voltage from the stepped-up supply voltage using a fine-resolution reference generator. The second reference can be then looped back to the boost regulator, thus, generating a more accurate steady-state stepped-up supply voltage.

Abstract: Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted.

Abstract: An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a variable resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a variable resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can be used, such as changes in temperature.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: Some embodiments of the present disclosure relate to a sensor interface module having a linearization module that increase a size of a linear region of a current output from a high-side current source. The disclosed sensor interface module has a reference voltage source configured to generate a reference signal. An output driver stage having a high-side current source and a low-side current source is connected in series at an output node of the sensor interface module. A closed control loop configured to receive the reference signal and to generate a digital control signal that drives the high-side current source. A linearization module configured to operate the low-side current source to approximate a nonlinearity of the high-side current source and to use the approximated nonlinearity to generate a compensation function that mitigates nonlinearities in the high side current source.

Abstract: An integrated circuit includes a first internal voltage generation unit configured to generate a first voltage and output the first voltage through an internal voltage terminal in an active operation period, a second internal voltage generation unit configured to generate a second voltage and output the second voltage through the internal voltage terminal in an initial section of a standby operation period, and a third internal voltage generation unit configured to generate a third voltage and output the third voltage through the internal voltage terminal in the remaining section of the standby operation period.

Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

Abstract: A reference circuit for an oscillator module is provided. The reference circuit includes a reference voltage generation unit and a reference current generation unit. The reference voltage generation unit includes an electric element having a voltage proportional to absolute temperature (PTAT voltage) and provides a reference voltage based on the PTAT voltage. The reference current generation unit is coupled to the reference voltage generation unit and provides a reference current to the oscillator circuit to serve as an input current based on the PTAT voltage. The oscillator circuit generates a clock signal based on the reference voltage and the input current. The reference voltage and the input current are proportional to absolute temperature and have the same change trend relative to absolute temperature, such that the clock signal is a temperature insensitive signal. An oscillator module including an oscillator circuit and the foregoing reference circuit is also provided.

Abstract: A current mirror comprises first and second sets of transistors. each of the first and second sets is a matched set comprising a first transistor and a second transistor. For each set, the base of the first transistor is directly coupled to the base of the second transistor. For one of the first and second transistors of each set the base is directly coupled to the collector. The collectors of the first and second transistors of the first set are coupled, respectively, to the emitters of the first and second transistors of the second set in series. A current output of the current mirror is coupled between the collector of the second transistor of the first set and the emitter of the second transistor of the second set.

Abstract: A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1<VR1, the microcomputer turns off the first switch, and turns on/off the second switch to gradually increase a voltage V3 of the power supply node. Thus, the operation of a clock generation circuit driven by V3 can be stable even when V3 is changed from V1 to V2.

Abstract: A voltage-stabilizing circuit for stabilizing an output voltage of a power integrated circuit (IC) includes an electronic switch and an RC circuit. The RC circuit includes a resistor and a capacitor. A first terminal of the resistor receives an enable signal and is connected to a control terminal of the electronic switch. A second terminal of the resistor is grounded through the capacitor, and is further connected to an enable pin of the power IC. A first terminal of the electronic switch is connected to a node between the resistor and the capacitor. A second terminal of the electronic switch is grounded.

Abstract: Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be programmed to transition among more than two states representing multiple bits of information.

Abstract: A multi-hysteresis voltage controlled current source system having a variety of multi-hysteresis characteristics is provided. In the multi-hysteresis voltage controlled current source system, single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N as fundamental components are connected in parallel, and a differential input voltage vid is applied to the single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N, so that a plurality of discrete values of current can be output based on the single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N.

Abstract: Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.

Abstract: An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry.

Abstract: A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage.

Abstract: A internal voltage generator includes a plurality of voltage level detection units, each configured to detect a voltage level of a corresponding internal voltage terminal, based on a predetermined target voltage level assigned to the corresponding internal voltage terminal, and generate a detection signal, a common internal voltage generation unit configured to generate an internal voltage through a pumping operation in response to the detection signal outputted from the voltage level detection units, and a path multiplexing unit configured to selectively output the internal voltage to one of the internal voltage terminals.

Abstract: A current mirror comprises first and second sets of transistors. each of the first and second sets is a matched set comprising a first transistor and a second transistor. For each set, the base of the first transistor is directly coupled to the base of the second transistor. For one of the first and second transistors of each set the base is directly coupled to the collector. The collectors of the first and second transistors of the first set are coupled, respectively, to the emitters of the first and second transistors of the second set in series. A current output of the current mirror is coupled between the collector of the second transistor of the first set and the emitter of the second transistor of the second set.

Abstract: The invention provides a device for stabilizing an effective value of an output current of a converter. The device comprises the following: an input to receive an input voltage x of the converter, a memory in which a first set of polynomial coefficients a, b, c; kj is stored, a processor that is coupled to the input and the memory and is set up so as to determine a current correction y as a polynomial function with the stored first set of polynomial coefficients a, b, c; kj as a function of the received input voltage x, and a power stage that is coupled to the processor to receive the current correction y and set up to modify the effective value of the output current as a function of the current correction y.

Abstract: Power control is facilitated. In accordance with one or more embodiments, power is supplied to power rails of an integrated circuit using a power control circuit including a power regulator and a reset circuit that is responsive to a supply voltage. The power regulator provides power to the power rails, based upon a control signal. The reset circuit controls the power regulator to provide power to the power rails independently of the control signal when the supply voltage is below an operational voltage level, and controls the power regulator to provide power to the power rails in response to the control signal when the supply voltage reaches the operational voltage level.

Abstract: A semiconductor element layer has a pixel region in which a plurality of photodiodes are provided and a peripheral circuit region in which a peripheral circuit for processing the device is provided, a power supply line to supply an electric power to the peripheral circuit, provided at a first side of the semiconductor element layer in the peripheral circuit region, a first wiring layer to supply the electric power to the power supply line, provided at a second side of the semiconductor element layer in the peripheral circuit region, and a plurality of first through-electrodes, provided in the peripheral circuit region and passing through the semiconductor element layer between the first side and the second side. At least a part of the first through-electrodes electrically connect between the power supply line and the first wiring layer.

Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Abstract: Aspects of the present disclosure relate to a current multiplier that can generate an output current with high linearity and/or high temperature compensation. Such current multipliers can be implemented by complementary metal oxide semiconductor (CMOS) circuit elements. In one embodiment, the current multiplier can include a current divider and a core current multiplier. The current divider can generate a divided current by dividing an input current by an adjustable division ratio. The division ratio can be adjusted, for example, based on a comparison of the input current with a reference current. The core current multiplier can generate the output current based on multiplying the divided current and a different current. According to certain embodiments, the output current can be maintained within a predetermined range as the input current to the current divider varies within a relatively wide range.

Abstract: A voltage booster system of a charge pump type includes a regulator for outputting a constant voltage and a charge pump circuit for boosting a voltage of an output terminal of the regulator. The regulator includes a differential amplifier unit for inputting a reference voltage and a feedback voltage according to the voltage of the output terminal, and an output stage portion including an PN connection element having one end portion connected to an application terminal of a power source voltage and another end portion connected to the output terminal. The PN connection element is configured to be controlled according to an output signal of the differential amplifier unit. The charge pump circuit includes a first capacitor to which the voltage of the output terminal is applied to be charged; a second capacitor; a third capacitor; a first switching section; and a second switching section.