Abstract: The invention provides a device for stabilizing an effective value of an output current of a converter. The device comprises the following: an input to receive an input voltage x of the converter, a memory in which a first set of polynomial coefficients a, b, c; kj is stored, a processor that is coupled to the input and the memory and is set up so as to determine a current correction y as a polynomial function with the stored first set of polynomial coefficients a, b, c; kj as a function of the received input voltage x, and a power stage that is coupled to the processor to receive the current correction y and set up to modify the effective value of the output current as a function of the current correction y.

Abstract: The invention provides a bipolar transistor circuit and a method of controlling a bipolar transistor, in which the bipolar transistor has a gate terminal for controlling the electric field in a collector region of the transistor. The bias voltage applied to the gate terminal is controlled to achieve different transistor characteristics.

Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Abstract: A device determines a first voltage measurement of an output of a first brick. The device further determines a second voltage measurement associated with a second brick. The first brick is larger in size than the second brick. The device ramps up an output voltage of the second brick when the second voltage measurement is less than the first voltage measurement.

Abstract: An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after to the active enable signal is enabled.

Abstract: A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit.

Abstract: An internal voltage generation circuit includes a flag signal generator suitable for generating a first flag signal which is enabled after a first predetermined time from a moment that a deep power-down mode terminates and suitable for generating a second flag signal which is enabled after a second predetermined time from a moment that the first flag signal is enabled, a drive signal generator suitable for receiving the first and second flag signals to generate a first drive signal and a second drive signal and suitable for receiving a pre-oscillation signal in response to the first and second flag signals to generate a third drive signal and a fourth drive signal, and an internal voltage generator suitable for driving a first internal voltage signal in response to the first and second drive signals and suitable for pumping a second internal voltage signal in response to the third and fourth drive signals.

Abstract: A semiconductor integrated circuit according to an embodiment includes an oscillator that generates and outputs an oscillation signal in an active state and generates no oscillation signal in an inactive state. The semiconductor integrated circuit includes a negative charge pump that generates an output voltage that is a negative voltage in response to the oscillation signal and outputs the output voltage to an output pad. The semiconductor integrated circuit includes a negative voltage detecting circuit that detects the output voltage and controls the oscillator to be in the active state or inactive state so as to bring the output voltage close to a target voltage.

Abstract: Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors.

Abstract: A self adjusting reference for an input buffer including an adjustable voltage shifter, a comparator, and a comparator and adjust circuit. The voltage shifter provides adjustable reference voltages based on a primary reference voltage, including upper, midway, and lower reference voltages. The comparator compares the midway reference voltage with the input voltage to provide an input sense signal indicative of a voltage state of the input voltage. The comparator and adjust circuit increases voltage levels of the reference voltages when the input voltage is in a low voltage state and has a voltage level that is greater than the lower reference voltage, and decreases the voltage levels of the reference voltages when the input voltage is in a high voltage state and has a voltage level that is less than the upper reference voltage.

Abstract: Systems and methods are provided for power control. In some implementations, a power control system includes a first transistor having a drain coupled to a first conductor (e.g., first pair of wires of an Ethernet cable), a second transistor having a drain coupled to a second conductor (e.g., second pair of wires of the Ethernet cable), a current sensor coupled to sources of the first and second transistors, and a current management circuit. The current management circuit may detect drain voltages of the first transistor and the second transistor, and adjust gate voltages of the first transistor and the second transistor to keep the drain voltages of the first transistor and the second transistor approximately equal. The current management circuit may detect a current through the current sensor, and adjust the gate voltages of the first transistor and the second transistor to limit the detected current to a current limit.

Abstract: The present inventive concept is a hyuntak transistor that can prevent a thermal runaway phenomenon and a low heat high efficiency constant current circuit using an auxiliary transistor capable of a high amplification and a constant current. The circuit may be applied to drive a LED and a motor.

Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. The code signal generator generates input code signals having a logic level combination corresponding to a difference between a frequency of an external clock signal and a frequency of an internal clock signal. The internal voltage generator is selectively activated according to the logic level combination of the input code signals to drive an internal voltage signal.

Abstract: A device includes a digital to analog converter (DAC) configured to generate a voltage output or a current output. The device also includes an integrated circuit configured to receive at least one of the voltage output or the current output and transmit the at least one of the voltage output or the current output to a load, wherein the integrated circuit is configured to measure a voltage level or a current level related to the transmission of the at least one of the voltage output or the current output. In one embodiment, a current limiter is included for voltage outputs as a form of power limiting and circuit protection. Additionally, the device includes a controller configured to receive an indication of the measurement from the integrated circuit and determine if the indication of the measurement exceeds a predetermined threshold.

Abstract: A semiconductor device comprises a plurality of circuit blocks, a plurality of local wirings which supply power to the plurality of circuit blocks, respectively, a global wiring which supplies the power to the plurality of local wirings, a plurality of first switches which are disposed between the plurality of local wirings, respectively, and the global wiring, and a second switch which is disposed between two local wirings. A power control unit controls open/close of the plurality of first switches and the second switch based on the potential difference between the two local wirings.

Abstract: Disclosed is a noise removing circuit including: a voltage booster which boosts an input signal; and a regulator which receives an output signal of the voltage booster and reduces the signal's voltage higher than a specific value to the signal's voltage having the specific value and then outputs the signal.

Abstract: The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.

Abstract: A voltage generator of a contactless integrated circuit (IC) card includes a regulator configured to generate a first internal voltage based on an input voltage and a first reference voltage, the input voltage being received through an antenna of the contactless IC card. The voltage generator includes an internal voltage generator configured to generate a second internal voltage, the second internal voltage being used to operate an internal circuit of the contactless IC card. The voltage generator includes a reference voltage generator configured to generate a second reference voltage based on the first internal voltage, the second reference voltage being generated without regard to a fluctuation component of the first internal voltage. The voltage generator includes a switching unit configured to provide one of the first and second internal voltages as the first reference voltage in response to first and second switching control signals.

Abstract: A device includes a digital to analog converter (DAC) configured to generate a voltage output or a current output. The device also includes an integrated circuit configured to receive at least one of the voltage output or the current output and transmit the at least one of the voltage output or the current output to a load, wherein the integrated circuit is configured to measure a voltage level or a current level related to the transmission of the at least one of the voltage output or the current output. In one embodiment, a current limiter is included for voltage outputs as a form of power limiting and circuit protection. Additionally, the device includes a controller configured to receive an indication of the measurement from the integrated circuit and determine if the indication of the measurement exceeds a predetermined threshold.

Abstract: A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison.

Abstract: An apparatus having one or more of a plurality of circuits in a first level of a hierarchy and two or more of the circuits in a second level of the hierarchy is disclosed. The circuits are configured to (i) allocate a profile from the first level down to the second level, (ii) manage from the second level a respective power consumed by each of a plurality of blocks based on the profile and (iii) maintain a sum of the powers approximately constant by increasing the power consumed by a first of the blocks while decreasing the power consumed by a second of the blocks.

Abstract: A reference current generation circuit is provided, in which a current generated according to a bandgap voltage is not directly used as a reference current, but the current generated according to the bandgap voltage is used to adjust an output reference current. In this way, the reference voltage is generated without using an external resistor, so as to effectively decrease the production cost.

Abstract: A system and method providing power supply rejection. One embodiment provides for power supply rejection in PLL or DLL circuitry. First subcircuitry provides second subcircuitry a supply voltage which is a filtered version of power from an external source. The first subcircuitry includes a first field effect transistor and a first low pass filter coupled to receive a signal from the external power source during operation of the second subcircuitry. The filter is coupled to provide a filtered version of the power source signal to the gate of the first transistor, so that when a first source/drain region of the first transistor is connected to receive power from the external source and the gate of the first transistor receives the filtered version of the power source signal, the second source/drain region of the first transistor provides a first modified version of the power received from the external source.

Abstract: Systems and methods are provided for regulating power in an integrated circuit system. A system includes a processing unit configured to monitor one or more operating parameters in the integrated circuit system. Based on the one or more monitored operating parameters, the processing unit is configured to predict an occurrence of an event that will cause an increased load on the integrated circuit system and further to assert a voltage adjustment command based on the predicted event. A power regulator is coupled to a power supply. The power regulator is configured to supply a regulated output voltage at a nominal voltage level. The power regulator is further configured to receive the voltage adjustment command and to supply the output voltage at an adjusted output level responsively to the voltage adjustment command.

Abstract: An approach is provided for a low-voltage, high-accuracy current mirror circuit. In one example, a current mirror circuit includes an input circuit configured to receive an input reference current. The input circuit includes a feedback channel for comparing and substantially matching the input reference current with an output current. The feedback channel is not configured for matching an input voltage with an output voltage. The input circuit does not include a comparator having an operational amplifier to compare the input reference current with the output current. The current mirror circuit also includes an output circuit coupled to the input circuit. The output circuit is configured to send the output current to one or more components of a circuit block.

Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.

Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.

Abstract: Disclosed is a current compensation circuit. During calibration of a compensation current, a digital control circuit delivers a digital signal with values varying over time to a current compensation array, the current compensation array outputs different amounts of compensation current based on the digital signal with values varying over time, the digital control circuit latches a value of the digital signal, which results in a best compensation current, based on influences of the different amounts of compensation current on a parameter to be calibrated, to complete the calibration. Upon and after completion of the calibration, the digital control circuit continuously delivers the digital signal with the latched value to the current compensation array, and the current compensation array outputs the best compensation current based on the digital signal with the latched value.

Abstract: An embodiment of a discharge circuit for evacuating electric charge accumulated in circuit nodes of a charge pump during a discharge phase consequent to a shutdown of the charge pump is proposed. The charge pump is configured to bias each circuit node with a corresponding pump voltage during an operational phase of the charge pump. The discharge circuit includes a generator circuit configured to generate a discharge current during the discharge phase. The discharge circuit further includes means for evacuating the electric charge stored in each circuit node of the charge pump during a corresponding portion of the discharge phase; such means for evacuating include a respective discharge stage for each circuit node of the charge pump. Each discharge stage includes a first discharge circuit branch and a second discharge circuit branch coupled to the corresponding circuit node.

Abstract: A semiconductor integrated circuit includes a first voltage supply unit, a second voltage supply unit configured to supply a voltage with a level different from that of the first voltage supply unit, and a voltage stabilizing unit connected between the first and second voltage supply units, and including at least one discharge path that includes a clamping section configured to temporarily drop a level of a voltage introduced from the first or second voltage supply unit, and a discharge section configured to discharge the voltage having passed through the clamping section to the second or first voltage supply unit.

Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.

Abstract: A linear voltage stabilizing circuit includes a main stabilizing unit, a first resistor, a second resistor, and a sub-stabilizing unit. The main stabilizing unit includes a first transistor connected between a signal input terminal and a signal output terminal, and a first comparator controlling the first transistor. The first and the second resistor are connected between the signal input terminal and ground. The voltage between the first resistor and the second resistor is equal to a first reference voltage. The sub-stabilizing unit includes a third resistor, a fourth resistor, a second transistor connected between the signal input terminal and the first transistor, and a second comparator. The third and fourth resistor are connected between the second comparator and ground. The node of the third and fourth resistor is connected to the node between the first and the second resistor. The second comparator controls the second transistor turn on or off.

Abstract: A semiconductor integrated circuit includes a logic circuit having a plurality of operation modes, a power source circuit that generates a power source voltage to be supplied to the logic circuit, a power source wiring that couples the power source circuit and the logic circuit, and a charge control block that holds charges for controlling the voltage of the power source wiring. The power source circuit generates a first power source voltage for causing the logic circuit to operate in a computing mode and a second power source voltage for causing the logic circuit to operate in a sleep mode. The charge control block includes a capacitor, a first switch, and a voltage supply unit that supplies the second power source voltage or a third power source voltage lower than the second power source voltage, to the capacitor.

Abstract: An intelligent voltage regulator circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Additionally, the intelligent voltage regulator circuit can include a processing element that is coupled to the variable voltage generator. The processing element can be coupled to receive programming for controlling a characteristic of the intelligent voltage regulator circuit. The processing element can be for dynamically changing the characteristic during operation of the intelligent voltage regulator circuit.

Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.

Abstract: A circuit for generating reference voltage and reference current includes a band-gap reference circuit and a voltage-to-current converting circuit. The band-gap reference circuit is configured to generate a temperature-independent reference voltage by generating a first current with a positive temperature coefficient. The voltage-to-current converting circuit is coupled to a node of the band-gap reference circuit and configured to convert a voltage with a negative temperature coefficient at the node into a second current with a negative temperature coefficient. The band-gap reference circuit and the voltage-to-current converting circuit share a common current source having a feedback transistor through which a reference current flows. The reference current is divided into the first current of the band-gap reference circuit and the second current of the voltage-to-current converting circuit, thus having a temperature coefficient substantially equal to zero by combining the first current and the second current.

Abstract: Embodiments relate to integrated circuits with protection. In one embodiment the protection is coupled between a first circuit provided to control a low power mode of the integrated circuit and a supply voltage. The protection comprises in an embodiment a transistor being one of a depletion transistor or a junction field effect transistor.

Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

Abstract: An offset-compensation circuit in a MEMS sensor device, provided with a micromechanical detection structure that transduces a quantity to be detected into an electrical detection quantity, and with an electronic reading circuit, coupled to the micromechanical detection structure for processing the electrical detection quantity and supplying an output signal, which is a function of the quantity to be detected. A compensation structure is electrically coupled to the input of the electronic reading circuit and can be controlled for generating an electrical compensation quantity, of a trimmable value, for compensating an offset on the output signal; the compensation circuit has a control unit, which reads the output signal during operation of the MEMS sensor device; obtains information on the offset present on the output signal itself; and controls the compensation structure as a function of the offset information.

Abstract: A regulating system for an insulated gate bipolar transistor (IGBT) includes a clamping circuit coupled to the IGBT. The IGBT is coupled to a gate driver circuit. The regulating system also includes a feedback channel coupled to the clamping circuit. The feedback channel is configured to transmit signals representative of a conduction state of said clamping circuit. The regulating system further includes at least one gate driver controller coupled to the feedback channel and the gate driver circuit. The gate drive controller is configured to regulate temporal periodicities of the IGBT in an on-condition and an off-condition.

Abstract: TASK: to provide an internal voltage trimming circuit having a simple configuration and operated by a consumption current smaller than that using a comparator. MEANS FOR SOLVING THE PROBLEM: An internal voltage trimming circuit comprises a trimming controller using a change in a counting value of a clock according to a current flowing through a transistor of a power supply current source for a clock generator to trim an internal voltage generated by an internal voltage generator. The trimming controller counts a first counting value of the clock when a predetermined reference voltage is applied to a control terminal of the transistor and a second counting value of the clock when the internal voltage is applied to the control terminal of the transistor and controls the internal voltage generated by the internal voltage generator to substantially coincide the second counting value with the first counting value.

Abstract: A slicer circuit including an input differential is configured to amplify an input reference voltage received at a pair of differential input nodes and provide a differential output voltage at a pair of differential output nodes, and a regeneration latch configured to amplify the differential output voltage. A differential offset compensation voltage is applied to the differential output voltage to provide DC-offset cancellation. A differential equalization voltage is applied to the differential output voltage to provide DFE equalization. A timing scheme employing multiple clocks provides reduced sampling-window width and increased output-signal width. Cross-coupled transistors are used to cancel kickback noise received at the differential output nodes.

Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Abstract: A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (Vin) line and a supply return line. A first switching capacitor is connected between first and second pairs of totem PN FETs pair of transistors. A second switching capacitor is connected between the second and a third pair of totem FETs. A configuration control selectively switches both third FETs off to float the connected end of the second capacitor, thereby switching voltage converter modes.

Abstract: Embodiments of the subject invention relate to a method and apparatus for providing a low-power AC/DC converter designed to operate with very low input voltage amplitudes. Specific embodiments can operate with input voltages less than or equal to 1 V, less than or equal to 200 mV, and as low as 20 mV, respectively. Embodiments of the subject low-power AC/DC converter can be utilized in magnetic induction energy harvester systems. With reference to a specific embodiment, a maximum efficiency of 92% was achieved for a 1 V input, and efficiencies exceeding 70% were achieved for a 200 mV input. A specific embodiment functioned properly when connected to a magnetic energy harvester device operating below 200 mV input.

Abstract: An internal voltage generation circuit includes a pumping voltage generation unit configured to generate a pumping voltage when a first internal voltage has a lower level than a first reference voltage or a second internal voltage has a lower level than a second reference voltage, and a select transmission unit configured to selectively transmit the pumping voltage as the first internal voltage or the second internal voltage.

Abstract: A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor.

Abstract: System and method system for regulating voltage in a portion of an integrated circuit. An integrated circuit has a voltage input and at least a portion that is less than all of the integrated circuit, which requires a local voltage level. A voltage selector establishes a target voltage for the portion. A first comparator compares the target voltage to the local voltage and generates a pull up control signal when the local voltage is below the target voltage. A second comparator compares the target voltage to the local voltage and generates a pull down control signal when the local voltage is above the target voltage. A pull up device, responsive to the pull up control signal, increases the local voltage according to the pull up control signal. A pull down device, responsive to the pull down control signal, decreases the local voltage level according to the pull down control signal.

Abstract: An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim variable resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim variable resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can be used, such as changes in temperature.