Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof.

Abstract: A XtalClkChip based on the application of hierarchical circuit and noise circuit design on the RF circuits of LC oscillation tank and the multi-phase fractional PLL are developed. The XtalClkChip combines both the XtalChip and multi-phase fractional PLL to provide the customer's clock to customer directly. This XtalChip will replace the crystal and the crystal circuit. The XtalClkChip will replace all the customer's clock circuit.

Abstract: In a portable dual mode receiver circuit, a dual modulus clock system is provided which can, by selective use of integer division on a multiplied master clock, select specific channels with two different channel spacings in several different bands, providing power and space savings and achieving simplicity of operation.

Abstract: A phase locked loop (PLL) frequency synthesizer to produce a local oscillator signal for a transmitter for operation at a plurality of RF frequency bands that are disparate. The transmitter has an intermediate frequency that is a sizable fraction of the bandwidth of one or more of the RF bands. The transmitter includes at least one RF upconverter, each having a local oscillator input coupled to the frequency synthesizer.

Abstract: Aspects of a method and system for signal generation via a PLL with undersampled feedback are provided. In this regard, the output of a VCO may clock a DDFS to generate a sampling frequency, and the output of the VCO may be undersampled at the sampling frequency to generate a feedback signal for controlling the VCO. Additionally, a control word for controlling the DDFS may be generated, and may be based on a phase difference between the feedback signal and a reference signal. The sampling frequency may be determined such that an aliasing product of the undersampling occurs at a frequency of the reference signal. Also, the feedback signal may be filtered to select a desired aliasing product from a plurality of aliasing products. The output of the VCO may be frequency divided before clocking the DDFS, and a divisor of the division may be programmatically controlled.

Abstract: An oscillator of the present invention includes a constant current circuit in which a constant current generated in the constant current circuit varies positively with an on threshold voltage of a transistor included in the constant circuit; and an oscillating circuit in which the oscillating frequency of a clock signal generated in the oscillating circuit varies positively with the constant current supplied from the constant current circuit, and the oscillating frequency of the clock signal generated in the oscillating circuit varies negatively with an on threshold voltage of a transistor included in the oscillating circuit.

Abstract: Aspects of a method and system for signal generation via a PLL with a DDFS feedback path are provided. In this regard, a phase difference between a reference signal and a feedback signal may be utilized to control a VCO, wherein the feedback signal is generated by a DDFS. Voltage, current and/or power levels of the generated feedback signal may be limited to a determined range of values. Moreover, the feedback signal may be based on an output of the VCO and a digital control word input to the DDFS. The digital control word may be programmatically controlled by, for example, a processor. Additionally, the control word may be determined based on a desired frequency of the generated feedback signal and a desired output frequency of the VCO. Accordingly, the DDFS may be clocked by the output of the VCO, or by a divided down version of the VCO output.

Abstract: Aspects of a method and system for signal generation via a PLL with a digital feedback path are provided. In this regard, an output of a VCO may clock an accumulator to generate a digital feedback signal for phase comparison with a digital reference signal, wherein a value of a digital control word is added to a value stored in said accumulator on each cycle of said VCO output. The phase comparison may be performed by multiplying the feedback signal and the reference signal. Accordingly, a control voltage of the VCO may be determined based on a product of the multiplication. The value of the control word may be programmatically controlled and may be determined based on a frequency of the VCO output and/or of the reference signal. In this regard, the value of the control word may be retrieved from a look-up table.

Abstract: A GPS RF Front End IC containing a Programmable Frequency Synthesizer is disclosed. The GPS RF front end IC having a programmable frequency synthesizer allows a relatively fixed internal frequency plan while able to use a number of different reference frequencies provided by the host platform, which can be a wireless phone, or other such device, which can provide an accurate reference frequency signal.

Abstract: The present invention relates to sigma-delta modulators, ?? modulators, and phase locked loops. Especially, it relates to jitter compensation in ??-controlled fractional-N frequency synthesizers. Jitter compensation is introduced by means of a variable delay line.

Abstract: A calibration circuit is configured to provide automatic feedback calibration during a tuning cycle. Automating the calibration process reduces the engineering evaluation time and mass production test time. The calibration settings vary as a function of frequency, and the calibration circuit automatically determines the proper calibration for any frequency application. The calibration circuit enhances communication performance by comparing and computing a time difference between a reference path and a feedback path. The calibration circuit is configured as part of a phase modulation path within a modulation circuit. The calibration circuit provides for calibration without prior knowledge of the system and reduced factory test time. The calibration circuit provides numerous advantages, including, but not limited to, accurate system results for time, frequency, temperature, and process variations with each calibration, or tuning.

Abstract: Techniques are provided for dynamically adjusting the frequency range of phase-locked loops (PLLs). Phase detection circuitry in a PLL generates a control signal in response to a periodic input signal and a feedback signal. When the control signal deviates outside a valid range, the input frequency range of the PLL is dynamically adjusted to include the periodic input signal frequency. The input frequency range of the PLL is adjusted by changing one or more frequency ratios in the PLL. The resistance and/or capacitance of a loop filter in the PLL can be dynamically adjusted to control the bandwidth of the PLL.

Abstract: A loop system capable of auto-calibrating an oscillating frequency range includes a frequency error detector, a voltage controlled oscillator (VCO), a voltage input unit, and a switch. The frequency error detector includes a rotational frequency detector, a state machine, and an up-down counter. The rotational frequency detector is used for comparing the reference frequency and the feedback frequency. The state machine is used for determining an auto-calibration state. The up-down counter is used for generating the second control signal or the coarse-lock-state signal. The VCO is used for selecting to operate at one of a plurality of frequency operating curves so as to generate an oscillating signal. The voltage input unit is used for providing a fixed voltage to the VCO. The switch is used for switching the VCO to couple to the voltage input unit or to couple to a fine frequency tuner.

Abstract: The invention relates to a frequency divider operated digitally and capable of satisfying the Zigbee standard, and a phase locked loop system using the same. The frequency divider includes a plurality of latches in a ring structure with an output of a latter end latch is connected to an input of a former end latch. The frequency divider also includes an input end connected in common to clock ends of the latches, receiving a signal to be divided, and a plurality of output ends connected to the output ends of the latches, outputting divided signals of different phases. The phase locked loop system of the invention has a dividing means dividing an output frequency by 1/P and 1/P+0.5 using the frequency divider, thereby generating the Zigbee channel frequencies at a 5 MHz spacing.

Abstract: A system, apparatus and method for providing phase lock conditions detection such as a quality of phase lock and loss of lock detection. A phase locked loop (PLL) circuit may comprise an oscillator for providing an output frequency, as well as a detector for detecting the output frequency of the oscillator, comparing the output frequency with a reference signal and outputting a first and second signals as a function of the comparison. The PLL circuit may further include an amplifying circuit for receiving the first and second signals, monitoring a deviation of the first and second signals from a predetermined threshold, and generating a third signal as a function of the deviation. The PLL circuit may further comprise a comparison circuit for receiving the third signal, comparing the third signal to a window threshold, and generating a fourth signal as a function of the comparison.

Abstract: An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal.

Abstract: A tuning circuit and a method for setting its tuning voltage. The tuning circuit has a phase frequency detector coupled to a loop filter which is coupled to a voltage controlled oscillator. An output terminal of the voltage controlled oscillator is coupled to an input terminal of the phase frequency detector to form a feedback loop. A state machine is coupled between the phase frequency detector and the voltage controlled oscillator. A switch is coupled between an output terminal of the state machine and the input terminal to the loop filter or between the output terminal of the state machine and the input terminal of the voltage controlled oscillator. Alternatively, a comparator is coupled between an input terminal of the state machine and the output terminal to the loop filter or between the input terminal of the state machine and the output terminal of the phase frequency detector.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof.

Abstract: A memory controller includes a ring oscillator to generate and to output at least one oscillation clock, an oscillation counter to count the output oscillation clocks, a sampler to receive the reference clock so as to sample a number of the counted oscillation clocks during a period of the reference clock, and a phase value output unit to output the sampled number of oscillation clocks as a phase value of the reference clock. Thereby, the memory controller can detect the phase value using only two periods of the reference clock, and reduce the initial operation time of a system.

Abstract: A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference between a reference oscillation and a feedback oscillation. The digital loop filter is coupled to process the difference signal to produce a control signal. The digitally controlled oscillation module is coupled to generate an output oscillation based on the control signal. The variable feedback divider is coupled to produce the feedback oscillation from the output oscillation based on a divider value and a controlled variable delay.

Abstract: A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverter stages coupled to form a loop, each differential inverter stage having including a switched capacitor circuit configured to control a signal delay through the differential inverter stage responsive to a control circuit, whereby an output frequency for the VCO is inherently compensated against changes in semiconductor process variations and thermal variations.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.

Abstract: The present invention provides a signal transmission device in which jitter occurring in a clock signal is eliminated. The signal transmission device has a construction in which a transmission end IC chip provided with a transmission part of a data signal and a reception end IC chip provided with a reception part of the data signal, the transmission part and the reception part are connected via a data signal transmission line, an oscillator that outputs a clock signal to the transmission part is connected with the transmission end IC chip, a clock signal transmission line is provided which leads the clock signal output from the oscillator to the reception part, and a SAW filter is arranged in the clock signal transmission line.

Abstract: A control loop (10) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference (11) and oscillator (25) output signals, a beat frequency generator (12) for producing a signal with a frequency that is the difference between the oscillator and reference signal frequencies, an ADC (14) to convert the beat frequency to a digital beat frequency signal, an estimator (17) for estimating the frequency or phase of the beat signal, an adder (18) for combining an offset and modulation signal and the estimated frequency or phase of the beat signal into an added signal, and a DAC (23) for generating an analogue control signal for controlling the oscillator output frequency.

Abstract: A frequency synthesizer, especially for use with a time-base generator of a fill-level meter employing the radar principle is designed to output a first frequency signal and a second frequency signal at mutually slightly different frequencies. The synthesizer incorporates a reference oscillator operating at a reference frequency and a control oscillator regulated at a control frequency. A first frequency divider with a division factor V1 is connected in line with the reference oscillator and a second frequency divider with the division factor V2 is connected in line with the control oscillator, which frequency dividers serve to output the first frequency signal and the second frequency signal, respectively. The result is a stable frequency synthesizer with a large phase-control bandwidth and consequently an extremely short transient response time as well as broad-band phase-noise suppression. A method for operating the synthesizer is also disclosed.

Abstract: A frequency synthesizer according to the present invention digitally controls an analog oscillator to generate an analog output signal at a desired frequency. A digitizing circuit converts a feedback signal derived from the oscillator output signal to a digitized multi-phase feedback signal. A comparator compares the digitized multi-phase feedback signal to a reference signal generated by the reference signal generator to generate an error signal indicative of the phase error in the output signal. A control circuit generates a control signal based on the error signal to control the frequency of the oscillator output signal.

Abstract: Disclosed is a system and method for providing an oscillating signal of relatively precise frequency without using a signal provided by a crystal as a reference. Disclosed is a feedback oscillator circuit configured to output an oscillating signal having a frequency defined by a reference signal. The oscillating signal can be sent to one or more circuits including at least one frequency sensitive element. The frequency sensitive element produces an output signal which depends on the frequency of the oscillating signal. A controller controls the reference signal in order to cause an attribute of the output signal to have a value within a desired range.

Abstract: An oscillator circuit that generates an oscillation signal is provided. The oscillator circuit includes an oscillator that generates the oscillation signal based on positive feedback of a signal, a synchronization signal generating section that generates a compulsory synchronization signal having an edge that (i) crosses a zero cross point at an ideal timing of an edge of the oscillation signal every predetermined number of cycles of the oscillation signal and (ii) has a gradient in the same direction as the edge of the oscillation signal, and a combining section that injects the compulsory synchronization signal into a positive feedback path of the oscillator.

Abstract: Provided are a PLL apparatus for an OFDM system having variable channel band and an operating method thereof. The PLL apparatus includes a frequency divider for dividing an oscillating signal; a phase detector for detecting a phase difference between a reference signal and the divided oscillating signal from the frequency divider and outputting the phase difference signal; a variable loop filter for filtering a phase difference signal outputted from the phase detector; a voltage control oscillator for outputting the oscillator signal to the frequency divider according to the voltage control signal filtered from the variable loop filter; and a variable loop filter controller for varying a filtering band of the variable loop filter according to each of the channel bands.

Abstract: An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscillator signal. For instance, the digital circuitry can provide a digital representation of the local oscillator signal. A DAC can convert the digital representation to an analog signal. Other circuitry can provide first and second quadrature components of the local oscillator signal, based on the analog signal.

Abstract: There provides a two-point modulation phase modulation apparatus capable of obtaining an RF phase modulation signal of superior modulation precision with low power consumption and a simple configuration even in the event of inputting a wide band baseband modulation signal. A differentiator (21) of the opposite characteristics to the attenuation characteristics of anti-alias filter (22) is provided at the front stage of a D/A converter (6). As a result, it is possible to sufficiently suppress an alias signal without raising the sampling frequency of the D/A converter (6) (i.e. low power consumption) using an anti-alias filter (22) of a simple configuration (i.e. low cost) with a low order for a narrower bandwidth than a PLL modulation frequency bandwidth, and it is possible to obtain an RF phase modulation signal where the entire frequency band of input digital baseband modulation signal (S1) is reflected in a superior manner.

Abstract: A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.

Abstract: An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that cause the oscillator to lock or falsely lock to the timing of an input data stream are determined at least in part according to a bit error rate. The bit error rate is based on transitions of the input data stream occurring in an error zone, the error zone being a predefined phase zone of a sample clock sampling the input data stream. When two control settings that cause the oscillator to lock or false lock are in a same locking region based on proximity of the control settings to each other, a preferred control setting is determined between the two according to respective values of the two control settings. True lock settings are distinguished from false lock settings based on an evaluation of bit errors that occur in an expanded error zone.

Abstract: A method for phase-locking a voltage controlled oscillator is disclosed. The method comprises receiving, at a phase detector, a phase input signal and a phase feedback signal from the voltage controlled oscillator; measuring a pulse width property of an error signal output from the phase detector to obtain a pulse width property measurement; storing the pulse width property measurement in a memory; and generating a new signal from the stored pulse width property measurement to phase-lock the voltage controlled oscillator. The method of the present invention may be used to calibrate a clock, in clock holdover and in qualification of clock sources.

Abstract: A Voltage Controlled Oscillator (VCO) includes a plurality of oscillation units connected in cascade to form a chain; and a plurality of current source sections operatively connected to the oscillation units, the current source sections each being configured to control current provided to the oscillation units, wherein each of the current source sections includes: at least one fixed current source configured to perform a current control of a corresponding oscillation unit by using a fixed voltage; and at least one variable current source configured to perform a current control of the corresponding oscillation unit by using a variable voltage.

Abstract: A circuit having a frequency controllable oscillator and a variable time delay circuit. The time delay circuit is fed by a signal produced by the oscillator, such time delay circuit being coupled to the oscillator to control the frequency of the signal produced by the oscillator. The circuit allows frequency agility of a phase locked loop although locked to a common reference frequency.

Abstract: A wireless base station (11) includes a wireless communication unit (17) and a clock signal generation unit (20). The clock signal generation unit (20) includes a voltage-controlled oscillation unit (21) that outputs a clock signal of an oscillating frequency according to an inputted control voltage, a time information generation unit (22) that generates time information based on the clock signal, a time information comparison unit (23) that compares the time information with reference time information; and a control voltage instruction unit (24) that instructs a control voltage according to the comparison result to the voltage-controlled oscillation unit (21). Accordingly, the oscillating frequency of the clock signal can be kept easily and highly precisely.

Abstract: This invention adds a non-linear sweep accumulator to the conventional sigma-delta fractional-N divider to produce a N.F value that is a polynomial function of time. This allows any non-linear sweep profiles to be approximated.

Abstract: There is provided a sigma delta modulator that outputs an output signal obtained by performing sigma delta modulation on an input signal, including: a plurality of accumulators that are serially connected; and an output signal generating section that generates the output signal on the basis of comparison result signals respectively output from the accumulators, in which each of the accumulators integrates values of signals being input and when an integration value is not less than a reference value, outputs the comparison result signal with a predetermined value and subtracts the value of the comparison result signal from the integration value, the value of the input signal is input into a first-stage accumulator, the integration value of the preceding-stage accumulator is input into the other accumulator, and at least one of the accumulators includes a low-pass filter that removes a predetermined high-frequency component in a waveform of the integration value.

Abstract: In an oscillating apparatus or a frequency detecting apparatus in which a center frequency and a variable frequency range are freely or optionally established with a high stability and a high accuracy, a first frequency component of a signal from a first crystal oscillator and a second frequency component of another signal from a second crystal oscillator are subjected to a synthesizing operation in a synthesizer and to other operations to obtain a desired center frequency and a desired variable frequency range.

Abstract: A current controlled, phase locked loop device includes a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto.

Abstract: During testing frequency divider PS, test control voltage signal TC and RF test signal TS are supplied via balun Ti to input terminals IN1 and IN2. Test control voltage signal TC flows through resistors R1, R2 to turn on NPN transistor Q0. A current from current source I1 then ceases to be supplied through voltage-controlled oscillator V1 and buffer B10 to voltage-controlled oscillator V1 and buffer B10 to halt their operation. Output impedance of buffer B10 is increased. Since potential of input terminals is that of test control voltage signal TC, varactor diodes VD1, VD2 are forward-biased, increasing capacitance values of the varactor diodes further. RF test signal TS may be supplied to frequency divider PS, through varactor diodes VD1, VD2, without being affected by buffer B10 exhibiting high output impedance. Chip area of test circuit for PLL circuit is reduced.

Abstract: An ensemble clock comprises: an input for receiving a reference signal; multiple free-running oscillators each configured to generate a corresponding free-running frequency; an output oscillator configured to generate a controlled frequency having a frequency responsive to a control signal; a differencer unit configured to derive difference measurements indicative of time and frequency-based errors associated with each of (i) the controlled frequency, and (ii) the free-running frequency, relative to the reference signal; and a controller configured to generate the control signal responsive to the difference measurements.

Abstract: A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.

Abstract: A communication system and an oscillation signal provision method based thereon are provided. In the communication system, a high frequency oscillator generates a first high frequency signal upon receipt of an enable signal. The first high frequency signal is commonly shared by a first module and a second module. The first module is coupled to the high frequency oscillator, operating in either busy or idle mode, wherein the first module operates at the first high frequency signal when in busy mode. The second module converts the first high frequency signal to a second high frequency signal and operates at the second high frequency signal when in busy mode.

Abstract: A method and apparatus for frequency synthesis in a transceiver are based on providing a primary frequency synthesizer configured to synthesize a receiver frequency signal from a receiver reference frequency signal, and providing an offset frequency synthesizer configured to synthesize a transmitter frequency signal from the receiver frequency signal using fractional-N division, which allows it to operate at an intermediate frequency that is a non-integer multiple of the receiver frequency signal. That arrangement enables non-integer duplex frequency distances between desired receive and transmit frequencies. The primary frequency synthesizer also may be operated as a fractional-N frequency synthesizer, meaning that the receiver frequency signal may have a non-integer relationship to the receiver reference frequency signal.

Abstract: A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.

Abstract: A phase-locked loop system configured to cause an output signal to tend toward a desired output frequency. The phase-locked loop system includes a charge pump system configured to produce a charge pump output based on differences detected between the output signal and the desired output frequency. The phase-locked loop system also includes an oscillator operatively coupled with the charge pump system and configured to produce the output signal based on the charge pump output. The charge pump system is configured to selectively effect proportional control over the output signal by applying correcting pulses along a proportional control path of the phase-locked loop system.