Abstract: A method and system for scaling a phase lock loop (PLL) based clock, includes: selecting a clock frequency; selecting a reference frequency, multipliers, and an output divider for an output frequency of a PLL, where the output frequency is higher than the clock frequency; applying the multipliers and the output divider to the reference frequency to generate the output frequency, outputted to a programmable logic chip; and applying a counter factor to the output frequency by the programmable logic chip to generate the clock frequency. By scaling the reference frequency in more than one step, the middle ranges of the multipliers are widened, allowing for a greater granularity of control over the increments by which the reference frequency can be adjusted. Smaller frequency errors result. The printer emulator utilizing the present invention has a set of more exactly generated clock frequencies that emulate a variety of printer speeds and resolutions.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signal. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. Ultimately, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In one particular aspect, the frequency plan provides a two-thirds relationship between the frequencies of the multiple signals.

Abstract: A phase locked loop (PLL) can include a test loop filter (100) that generates a control voltage (VCTRL) for input to a voltage controlled oscillator (VCO). In a test mode, a control voltage can be varied and resulting output frequencies recorded, from which an open loop bandwidth can be determined. A control voltage can be varied by enabling a switch element (104-1) that can provide a current path through load resistance (RL) of test loop filter (100). Current provided to the test loop filter can be varied according to test signals to provide a variable control voltage (VCTRL).

Abstract: A clock generator circuit is provided wherein a comparison clock signal is generated by comparing a standard clock signal and an operating clock signal. The comparison clock signal is converted into a current signal. The current signal is converted to multiple current signals and an operating clock signal having multiple varying frequencies is generated based on the multiple current signals.

Abstract: A method and device are provided for producing mobile radio signals, which utilize a direct conversion receiver, at least one first and one second local oscillator and one regenerative divider for processing signals according to different mobile radio standards. For generating the intermediate frequency for transmission according to at least one of the mobile radio standards, a division by four in addition to a division by three of the oscillator frequency is also possible.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof.

Abstract: In one embodiment, a phase-locked loop system in a receiver samples received incoming data using a first clock and a second clock that have the same frequency but are out of phase with each other. A first control signal generated by a phase detector is used to control a charge pump, whose output may be filtered to drive a VCO circuit generating the first and second clocks. A frequency detector generates a second control signal based at least on phase relationships between the incoming data and the first and second clocks. A qualifier circuit determines if the first control signal is valid or invalid based at least on the second control signal. If the first control signal is invalid, the qualifier circuit prevents the first control signal from being used to adjust the frequency of the first and second clocks.

Abstract: A frequency synthesizer and a method using a first seed word and a variable clock rate derived from a second seed word for synthesizing a signal frequency. An accumulator accumulates the first seed word at the variable clock rate with a remainder word for updating a reference word at the variable clock rate. The reference word has a most significant bit (MSB) and less significant bits (LSB)s. The remainder word corresponds to the LSBs at overflows of the MSB. A tracking filter filters the MSB for providing a filtered output signal having an output frequency derived from the first seed word and the variable clock rate. The variable clock rate is derived by direct synthesis from the second seed word and single sideband frequency upconversion. The tracking filter can be a phase lock loop with frequency upconversion.

Abstract: A clock signal outputting method in which either a clock signal based on a signal from the outside or an alternative clock signal from a fixed oscillator is selected and outputted, wherein, when the clock signal is selected to be outputted, the fixed oscillator is put into non-operating state, and when any error occurs in the clock signal, the fixed oscillator is operated to output the alternative clock signal.

Abstract: A frequency synthesizer and a method for synthesizing a microwave output signal frequency. The synthesizer uses a reference signal having a variable frequency and accumulation in feedback of a phase locked loop for synthesizing a microwave output frequency. The feedback accumulation rate is derived from a first seed word and the variable reference frequency is derived from a second seed word. A spur suppressor having arithmetic frequency conversions reduces the levels of in-band spurious signals of the variable reference frequency signal in order to reduce the spurious signal levels in the output signal.

Abstract: A phase locked loop (PLL) system for generating a reference clock to write recording data on an optical medium includes a clock generator generating the reference clock according to a phase difference between the reference signal and a first frequency-divided signal; a phase-shift detector generating a phase adjusting signal; and a phase-controllable frequency divider dividing the frequency of the reference clock to generate the first frequency-divided signal, and receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal. The phase-shift detector includes an ADIP sync detector generating an ADIP synchronization signal synchronous to the ADIP units of the optical medium; a frequency divider dividing the reference clock to generate a second frequency-divided signal; and a phase difference detector detecting a phase difference between the second frequency-divided signal and the ADIP synchronization signal to generate the phase adjusting signal.

Abstract: A range controller circuit has a master counter with a recovered clock input. A sampled counter has a reference clock input. A link fault indicator logic is coupled to an output of the master counter and an output the sampled counter.

Abstract: An impulse waveform generating apparatus comprises an oscillator for generating a reference signal having a center frequency in a frequency band of an impulse to generate, a timing matching circuit for shifting a phase of the reference signal by 90 degrees, a frequency demuultiplier for dividing a frequency of the phase shift signal and obtaining a timing signal having a frequency component having a frequency width of an impulse to generate, a memory storing a waveform shape table, a waveform forming section for forming a waveform in synchronism with the timing signal, according to information of a shape table having a predetermined waveform, a low-pass filter for obtaining an envelope signal from an output signal of the waveform forming section, and a waveform generating section for changing an amplitude of the reference signal according to a value of the envelope signal.

Abstract: A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.

Abstract: An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscillator signal. For instance, the digital circuitry can provide a digital representation of the local oscillator signal. A DAC can convert the digital representation to an analog signal. Other circuitry can provide first and second quadrature components of the local oscillator signal, based on the analog signal.

Abstract: Dispersing directions of oscillation frequency variable ranges of all voltage controlled oscillators provided in an integrated circuit are uniformed, and not only a range covering a frequency regardless of whether a dispersion occurs or not, but also a range covering the frequency only in a case where the dispersion occurs is used as the frequency variable range of the voltage controlled oscillator, and the frequency variable ranges of the voltage controlled oscillators are set so as to be successive with respect to each other, so that a small number of voltage controlled oscillators can cover a wide frequency variable range. Thus, the integrated circuit having voltage controlled oscillators therein is miniaturized.

Abstract: Method for stabilizing the frequency of a frequency synthesizer by means of a reference oscillator unit coupled to a voltage controlled oscillator (VCO) and a frequency synthesizer, wherein the synthesizer is provided with a phase locked loop (PLL) to stabilize the operation of the voltage controlled oscillator, wherein the reference oscillator unit is a MEMS (MicroElectromechanicalSystems) reference oscillator unit, the temperature of the MEMS reference oscillator unit is measured, and the output frequency is corrected according to the measured temperature by using a frequency/temperature function.

Abstract: A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

Abstract: A method and system for pulling a crystal frequency are provided, thereby allowing wireless stations to use less accurate crystal oscillators and dramatically reduce cost. A first frequency offset can be determined using a temperature-based method. This temperature-base method can include detecting a temperature substantially that of the crystal oscillator and then using that temperature to determine the first frequency offset. A second frequency offset using a closed loop frequency estimate-based method can also be determined. This frequency estimate-based method can include synchronizing the crystal frequency to a presumed, accurate frequency of a controlling device to determine the second frequency offset. Both the first and second frequency offsets can be used to pull the crystal frequency. A synthesizer can also be pulled to fine tune a carrier frequency derived from the crystal frequency.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

Abstract: A receiver uses an adaptive algorithm to tune a low-cost crystal oscillator according to a temperature compensation profile so as to produce a precision master reference frequency despite temperature, initial tolerance, and aging effects. An automatic frequency control system also tunes the crystal oscillator. The adaptive algorithm adjusts the temperature compensation profile for the crystal oscillator according to the adjustments made by the automatic frequency control should a received signal's quality factor exceed that associated with the temperature compensation profile.

Abstract: A single chip direct conversion transceiver that includes a substrate on which a mixer unit and a local oscillator are provided as a circuit, and a positive hole formed between the mixer unit and the local oscillator and filled with a conductive plug to block signal leakage. A shield ground surface is formed above the substrate and blocks signal leakage occurring when the signals received through the antenna are input into the mixer and signal leakage occurring when the reference signal is input into the mixer from the local oscillator. A first interconnection is formed above the shield ground surface and connects the mixer unit and the local oscillator. Dielectric layers are formed between the substrate and the shield ground surface and on the shield ground surface to cover the first interconnection.

Abstract: A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable both to clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. Ramp slope dithering is used to increase resolution. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.

Abstract: A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Abstract: A system and method for accurately detecting an asynchronous frequency within a synchronous digital system. The improved system and method preconditions the asynchronous frequency so that it does not introduce additional phase noise at low frequencies within a digital PLL. The system comprises a digitally controlled oscillator, having a preconditioner and a digital phase locked loop. The preconditioner receives an input clock signal and outputs a modified clock signal that is synchronized to a master clock signal. The digital phase locked loop receives the modified clock signal output from the preconditioner and outputs an output clock signal that is a version of the input clock signal synchronized to the master clock signal. The preconditioner preferably has a higher bandwidth than the digital PLL, and the preconditioner operates to noise shape phase noise of the synchronization to higher frequencies. The digital phase locked loop may then operate to remove the phase noise at the higher frequencies.

Abstract: An apparatus and method of controlling an optical signal includes superimposing at least one optical reference signal and the optical signal to obtain at least one interference signal having an actual beat frequency, and pre-selecting one or more of the at least one interference signals using a predetermined bandwidth and a filter characteristic that is asymmetric with respect to an actual frequency of the optical signal, to determine a position of the optical signal relative to the at least one optical reference signal.

Abstract: A PLL system for generating an output signal according to a first reference signal is disclosed. The output signal is used as a reference clock to write recording data on an optical medium. The PLL system includes a clock generator for receiving the first reference signal and a first frequency-divided signal to generate the output signal according to a phase difference between the first reference signal and the first frequency-divided signal; a phase-shift detector for generating a phase adjusting signal; and a phase-controllable frequency divider for dividing the frequency of the output signal by a frequency dividing ratio to generate the first frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal.

Abstract: Method and system are disclosed for automated calibration of the VCO gain in phase modulators. The method and system of the invention comprises synthesizing, in a phase modulator, a signal having a given output frequency using a controlled oscillator having a frequency control input, a modulation input, and a feedback loop. A frequency control signal is applied to the frequency control input, and gain variation of the controlled oscillator is compensated for outside of the feedback loop via the modulation input. The method and system of the invention may be employed in any telecommunication system that uses phase and amplitude modulation, including EDGE and WCDMA systems.

Abstract: A reference timing signal apparatus with a phase-locked loop (PLL) has a computer algorithm which adaptively models the multiple frequencies of an oscillator following a training period. The oscillator is part of a PLL and the oscillation frequency thereof is controlled in response to the phase detector output. The computer algorithm processes the control signal applied to the oscillator. The computer algorithm updates the characteristics of the model relating to the aging and temperature of the oscillator, using for example, a Kalman filter as an adaptive filter, in accordance with a cumulative phase error in the PLL calculated during a given time interval. By the algorithm, the subsequent model predicts the future frequency state of the oscillator on which it was trained. The predicted frequency of the model functions as a reference to correct the frequency of the oscillator in the event that no input reference timing signal is available.

Abstract: Disclosed is a quadrature signal generator for generating an in-phase signal and a quadrature-phase signal, which is capable of generating a quadrature signal having the same frequency as a differential oscillating frequency, using a feedback control system.

Abstract: A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable to both clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.

Abstract: Disclosed is apparatus for operating with an RC filter (26, 26A), and a corresponding method. The apparatus includes circuitry (32) for use in measuring an actual value of at least one filter component and a controller (34), coupled to the measurement circuitry, for determining at least one adaptive filter (36, 46) coefficient using the measured actual value to so as to compensate for a deviation of at least one filter component value from an ideal value. Where the filter is embodied as an RC network, the circuitry measures an actual value of both a resistor and a capacitor, and the controller uses the measured actual value of the capacitor when determining the value of a resistor.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signal. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. Ultimately, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In one particular aspect, the frequency plan provides a two-thirds relationship between the frequencies of the multiple signals.

Abstract: A signal synthesizer includes a high frequency offset stage having a high frequency offset source and frequency translation element in the feedback path of a dual-oscillator offset loop synthesizer. The signal synthesizer achieves low phase noise via noise cancellation when used to provide the first local oscillator of a spectrum analyzer and when the second local oscillator of the spectrum analyzer provides the high frequency offset source to the signal synthesizer.

Abstract: A single loop PLL frequency synthesizer for operation in the MHz to GHz range, suitable for integration in integrated circuits, operates at high comparison frequencies thus achieving superior phase noise performance, having wide loop bandwidths while able to tune in small frequency steps. It is based on the fact that the output frequency and the reference clock frequency always have a rational relationship, and so can always be represented as a ratio of two integer numbers. This ratio is expanded into various expressions of equivalent fraction expansions taking the form of a series of divided, added or subtracted terms, each being a rational number in itself. This ratio is realized in hardware through stages of frequency conversions using single sideband mixers (either the upper or lower sideband, and frequency dividers. This process of frequency translation thus generates the comparison frequency to which the PLL phase-locks the VCO.

Abstract: In one embodiment, the present invention provides a system including a varactor and a voltage generator. The varactor includes a set of substantially equal voltage-tunable capacitor cells, each having a capacitive range that varies with a first plurality of operating parameters and each providing a capacitance within the range based on a voltage level of a reference voltage. The voltage generator is configured to provide the reference voltage, wherein the voltage level of the reference voltage corresponds to a desired capacitance within the capacitive range and varies based on a second plurality of operating parameters which are substantially the same as the first plurality of operating parameters, and wherein the voltage level of the reference voltage causes each capacitor cell to provide the desired capacitance.

Abstract: An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.

Abstract: A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency.

Abstract: A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that, would utilize this square wave clock signal.

Abstract: An electrical circuit generates an oscillating signal that produces reduced electromagnetic interference by way of modulation of the frequency of the oscillating signal within a specified frequency range. A randomized signal generator creates a randomized signal, which is then used to drive a frequency range converter that is employed to produce a frequency modulation signal. The current state of the frequency modulation signal is based on the current state of the randomized signal, with the converter limiting the current state of the frequency modulation signal so that the oscillating signal will only operate within the specified frequency range. A variable frequency oscillator then generates the oscillating signal whose frequency is based on the current state of the frequency modulation signal.

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract: A PLL circuit for generating a clock signal synchronized with a first reference signal generated by superimposing a wobble signal on a land pre-pit signal or a second reference signal generated from a wobble signal. The PLL circuit enables reduction in circuit scale. When a DVD-R/RW is used as an optical disc, a first loop synchronizes the frequency of a wobble signal with the frequency of a divisional clock signal, which is generated from a recording clock signal of a voltage-controlled oscillator. Further, a second loop synchronizes the phase of the divisional clock signal with the phase of the LPP signal. When a DVD+R/RW is used as an optical disc, the first loop synchronizes the frequency of the divisional clock signal with the frequency of the wobble signal. Further, the second loop applies constant voltage to a control voltage input terminal of the voltage-controlled oscillator.

Abstract: A receiver uses an adaptive algorithm to tune a low-cost crystal oscillator according to a temperature compensation profile so as to produce a precision master reference frequency despite temperature, initial tolerance, and aging effects. An automatic frequency control system also tunes the crystal oscillator. The adaptive algorithm adjusts the temperature compensation profile for the crystal oscillator according to the adjustments made by the automatic frequency control should a received signal's quality factor exceed that associated with the temperature compensation profile.

Abstract: An oscillation control circuit comprising a PLL circuit and a phase-locked state discrimination circuit is adapted to an oscillation circuit that performs oscillation to produce an oscillation signal (CKX) when supply voltage is applied thereto. The PLL circuit produces a clock signal (CKP) whose frequency is a multiple of the frequency of the oscillation signal, wherein it controls the clock signal to be synchronized with the oscillation signal in phase. The phase-locked state discrimination circuit discriminates whether or not the PLL circuit is placed in a phase-locked state on the basis of a phase relationship between the oscillation signal and clock signal. Based on a discrimination result, a damping resistance adapted to the oscillation circuit is switched over. That is, the damping resistance (Rd) is reduced to cope with an unstable state of oscillation; then, it is restored to an original resistance thereof when oscillation is certainly stabilized.

Abstract: A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

Abstract: Systems and methods are disclosed for recovering a clock or time reference for A/V systems. One method comprises receiving at least one input time reference generated using a first clock and generating, using a second clock asynchronous to the first clock, at least one time reference value representative of the at least one input time reference. The method further comprises outputting the generated time reference value used by the A/V system.

Abstract: A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.