Abstract: A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.

Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract: In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

Abstract: A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.

Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

Abstract: In an integrating A/D converter, first and second reference voltage inputs (18, 20) alternatingly connect through a reference voltage switch (16, 16?) via a first reference resistor (Rref) to an inverting input (122) of an integrator (12). A comparator (22) connected downstream of the integrator (12) compares a test voltage applied to its test voltage input (221) with a comparator reference voltage applied to its reference voltage input (222). This input (221) is connected to the output (126) of the integrator (12). A control device (40) actuates the first reference voltage switch (16, 16?) in a pulsed manner and measures the time intervals between the individual switching processes. An inverter (24) inverting a measuring voltage (UM) and a first heating resistor (RMH) coupled thermally with a measuring resistor (RM), are connected in series between the measuring voltage input (14) and the output of the first reference voltage switch (16, 16?).

Abstract: A semiconductor device using analog-to digital (AD) conversion realizes reliable control so that, at the time of AD converting reference voltage, a low-voltage transistor in a reference voltage generating circuit is not destroyed by voltage held in a sample and hold circuit. In a semiconductor device, when an instruction of detecting a reference voltage value is received, a switch control unit controlling switching of an input signal of an internal AD converter temporarily automatically couples an input node of a sample and hold circuit and a ground node and, after that, couples the input node of the sample and hold circuit and an output node of a reference voltage generating circuit.

Abstract: A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.

Abstract: The present invention relates to an analog-to-digital converting circuit with temperature sensing and the electronic device thereof. The present invention uses a first impedance device to receive a reference voltage and produces an input current according to a temperature. An analog-to-digital converting unit is coupled to the first impedance device and produces a digital output signal according to the input current. Thereby, according to the present invention, by integrating the first impedance device into the analog-to-digital converting circuit, the circuit area and the power consumption can be lowered, which further reduces the cost and improves the accuracy of temperature sensing.

Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.

Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.

Abstract: A system includes an array of comparators configured to convert an analog input to a digital output, a switch configured to adjust output bits of the digital output, and a control logic; the control logic is configured to initialize the switch and a direct-current source coupled to the analog input; the control logic is configured to increase the direct-current source in incremental steps of a minimal voltage value corresponding to the least significant bit of the digital output; and the control input is also configured to cause the switch to adjust one or more output bits of the digital output based at least in part on a value of the output bit corresponding to the current incremental step.

Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.

Abstract: A quantizer includes a voltage reference network and a set of comparators coupled with the voltage reference network. The voltage reference network generates a plurality of reference voltages. Each of the comparators receives an input signal and produces a sequence of digital samples. The set of comparators includes first, second, and third subsets of comparators. Each comparator of the first subset includes a switched capacitor stage, each comparator of the second subset includes a preamplifier stage, and each comparator of the third subset includes a switched capacitor stage. The first and third subsets of comparators compares the input signal with reference voltages corresponding to the upper and lower voltage ranges of the input signal, and the second subset of comparators compares the input signal with reference voltages corresponding to the middle voltage range of the input signal.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.

Abstract: According to example configurations as described herein, a power supply system includes a unique circuit including an analog summer circuit, an analog-to-digital converter, and a digital controller. An output voltage feedback control loop of the power supply system feeds back the output voltage to the analog summer circuit. The analog summer circuit generates an analog error voltage signal based on: i) the output voltage received from the output voltage feedback loop, ii) an analog reference voltage signal, and iii) an analog reference voltage adjustment signal. The analog reference voltage adjustment signal varies depending on a magnitude of current provided by the output voltage to the dynamic load. Accordingly, the analog summer circuit can be configured to support adaptive voltage positioning. The analog-to-digital converter converts the analog error voltage signal into a digital error voltage signal. A controller generates output voltage control signal(s) based on the digital error voltage signal.

Abstract: An analog-to-digital converter (ADC) for a multi-channel signal acquisition system, a signal acquisition system, a method of generating a digital output code from an analog input signal, and a method of converting a plurality of analog signals to a digital signal are provided. The ADC comprises a sample-and-hold (S/H) circuit operable to receive an analog input signal for each input channel; a digital-to-analog converter (DAC) common to all input channels; a comparator for each input channel configured to receive an output signal from the S/H circuit of the respective input channel, and an output signal from the DAC, for generating a comparison result of the two signals at each conversion cycle of the comparator; and a successive approximation register (SAR) common to all input channels and configured to generate, for each input channel, a digital output code based on the comparison results received from the respective comparator.

Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.

Abstract: An analog to digital detector circuit includes a comparator circuit and a counter that generates a digital counter value. A digital to analog converter receives an inverse of the digital counter value of the counter and generates a first voltage. A variable current source receives the digital counter value of the counter and generates a first current.

Abstract: A battery charger includes a battery cell, a reference voltage generating section, an A/D converting section including an A/D converter and a control section. The reference voltage generating section includes a first reference voltage circuit generating a first reference voltage and a second reference voltage circuit generating a second reference voltage equal to the first reference voltage. To diagnose the A/D converter, the first reference voltage circuit is used. To diagnose the first reference voltage circuit, a second A/D conversion value obtained by A/D converting a second divided voltage of the second reference voltage via the A/D converter using the first reference voltage is compared with a first reference value obtained by A/D converting a first divided voltage of the first reference voltage via the A/D converter using the first reference voltage when the first reference voltage circuit is normal.

Abstract: A comparator includes: a differential amplifier circuit to operate based on a clock signal and output a first intermediate output and a second intermediate output corresponding to a first input signal and a second input signal respectively; and a differential latch circuit to operate based on the clock signal and vary a state based on the first intermediate output and the second intermediate output, the differential latch circuit having a controllable sensitivity with respect to a state variation of the first intermediate output and the second intermediate output.

Abstract: A mobile device having first and second modes of operation is operated responsive to detection of a predefined localized movement of a housing of the mobile device using a sensor associated therewith. The detected predefined localized movement is associated with first and second functions of the mobile device responsive to a user input assigning the detected predefined localized movement thereto. A first device function is performed responsive to detection of the predefined localized movement in the first mode of operation, and a second device function is performed responsive to detection of the predefined localized movement in the second mode of operation. A predetermined delay time may also be associated with the predefined localized movement, and the first and/or second functions may be performed at the predetermined delay time after detecting the predefined localized movement.

Abstract: An A/D converter includes: plural comparators to which reference voltages as ramp waves different from each other are supplied, which are configured to compare the supplied reference voltages with an analog input signal; and plural latches arranged so as to correspond to the plural comparators, which are configured to count comparison time of the corresponding comparators, to stop counting when an outputs of the comparator is inverted and to store the count value, wherein the plural reference voltages are off set by an arbitrary voltage at the same time point.

Abstract: An analog-digital converter includes: a first comparator configured to make a comparison between a pixel voltage and a first reference voltage, the pixel voltage being a signal voltage outputted from a pixel including an photoelectric conversion element, the pixel voltage corresponding to electric charge generated by the photoelectric conversion element; a second comparator configured to make a comparison between the pixel voltage and a second reference voltage; and a voltage follower configured to connect an input terminal for the first reference voltage of the first comparator and an input terminal for the second reference voltage of the second comparator through a switch.

Abstract: An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

Abstract: A semiconductor integrated circuit includes: a plurality of current sources including a first transistor individually connected to a power source line and a bias line; and a plurality of bias blocks including a second transistor configured to constitute a current mirror circuit together with the first transistor, and to divide a reference current to be a reference of the current sources so that the reference current flows through the bias line.

Abstract: A main microcomputer abnormality determination section checks whether or not a voltage value of Vcc based on digital data output from a main microcomputer analog-to-digital converter is equal to or higher than a threshold value to thereby perform abnormality determination for the main microcomputer analog-to-digital converter and Vref. A sub microcomputer abnormality determination section checks whether or not the voltage value of Vcc is equal to or higher than a threshold value based on digital data output from a sub microcomputer analog-to-digital converter to thereby perform abnormality determination for the sub microcomputer analog-to-digital converter and Vref. An abnormality identifying section identifies an abnormality occurring site by using both results of the abnormality determination performed by the main microcomputer abnormality determination section and the sub microcomputer abnormality determination section.

Abstract: A regular expression pattern matching circuit based on a pipeline architecture is proposed, which is designed for integration to a data processing system, such as a computer platform, a firewall, or a network intrusion detention system (NIDS), for checking whether an input code sequence (such as a network data packet) is matched to specific patterns predefined by regular expressions. The proposed circuit architecture includes an incremental improvement on an old combination of a comparator circuit module and an NDFA (non-deterministic finite-state automata) circuit module, where the incremental improvement comprises a data signal delay circuit module installed to the comparator circuit module and an enable signal delay circuit module installed to the NDFA circuit module to thereby constitute a multi-sage pipeline architecture that allows a faster processing speed than the prior art.

Abstract: A method and apparatus for detecting an event and sampling first value from a pin in response to the event. For example, the event is identified by a signal object of a plurality of signal objects stored in a memory. Each signal object of the plurality of signal objects identifies a single analog input pin and a trigger.

Abstract: The present invention provides an analog-to-digital converter, which comprises an integration circuit, a threshold signal generating circuit, a main comparison circuit, a sub comparison circuit, a counter, and a decoder. The integration circuit integrates an input signal and produces an integration signal. The threshold signal generating circuit generates a main threshold signal and a plurality of sub threshold signals. The main comparison circuit produces a plurality of main comparison signals according the integration signal and the main threshold signal. The sub comparison circuit produces a plurality of sub comparison signals according to the integration signal and the plurality of sub threshold signals. The counter counts the plurality of main comparison signals and produces a first counting signal. The decoder decodes the plurality of sub comparison signals and produces a second count signal. The first count signal and the second count signal are used for producing a digital signal.

Abstract: A reference voltage generator generates a reference voltage at the time of sampling a received input signal. A sampling time controller detects a change in the reference voltage. When the reference voltage rises to a determined threshold, the sampling time controller determines that sampling is completed, and generates a sampling clock in which sampling time is controlled on the basis of an external clock.

Abstract: A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

Abstract: Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.

Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.

Abstract: An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.

Abstract: An arrangement for reading out an analog voltage input signal includes an input applying the input signal thereto, and a reference unit generating an analog reference voltage. To perform online self-calibration, the arrangement includes a superposition unit generating a combined analog signal by superimposing the analog reference voltage onto the input signal, a converting unit converting the combined analog signal into a one-bit serial data stream at a conversion sampling rate, and a decomposition unit, which includes at least two digital filters configured to generate from the serial data stream two corresponding digital signals at different data rates, which can be less than the conversion sampling rate.

Abstract: In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output.

Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.

Abstract: Various embodiments of an analog-to-digital (A/D) device are described herein, with the A/D device using at least a comparison unit, a comparative operation control circuit, a delay circuit, and a successive operation control circuit arranged so as, it may, among other things, mitigate conversion errors that may be due to differences in properties of circuit elements therein. And the A/D device may be implemented in, among other things, a signal processing device.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.