Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Abstract: A screen calibration method includes acquiring a full screen image displayed on a screen by a camera, acquiring first optical data of a first region of the screen by a sensor, adjusting the first optical data of the first region of the screen according to first calibration parameters for calibrating colors of the first region to approach target optical data, generating second optical data of a second region of the screen according to the full screen image and the first optical data of the first region, generating second calibration parameters according to the target optical data and the second optical data, and adjusting the second optical data of the second region of the screen according to the second calibration parameters for calibrating colors of the second region to approach the target optical data.

Abstract: Approaches to robust encoding and decoding of escape-coded pixels in a palette mode are described. For example, sample values of escape-coded pixels in palette mode are encoded/decoded using a binarization process that depends on a constant value of quantization parameter (“QP”) for the sample values. Or, as another example, sample values of escape-coded pixels in palette mode are encoded/decoded using a binarization process that depends on sample depth for the sample values. Or, as still another example, sample values of escape-coded pixels in palette mode are encoded/decoding using a binarization process that depends on some other fixed rule. In example implementations, these approaches avoid dependencies on unit-level QP values when parsing the sample values of escape-coded pixels, which can make encoding/decoding more robust to data loss.

Abstract: An electronic apparatus includes a locking unit to selectively lock a physical connection with an external apparatus and a control unit to control an operation mode of the electronic apparatus, according to a connection state with the external apparatus, in which the control unit controls the locking unit to lock the connection with the external apparatus, when the electronic apparatus is in an operation mode of using a graphic processing unit of the external apparatus.

Abstract: Methods, systems, and computer-readable media for dynamic and application-specific virtualized graphics processing are disclosed. Execution of an application is initiated on a virtual compute instance. The virtual compute instance is implemented using a server. One or more graphics processing unit (GPU) requirements associated with the execution of the application are determined. A physical GPU resource is selected from a pool of available physical GPU resources based at least in part on the one or more GPU requirements. A virtual GPU is attached to the virtual compute instance based at least in part on initiation of the execution of the application. The virtual GPU is implemented using the physical GPU resource selected from the pool and accessible to the server over a network.

Abstract: An image generation-output control apparatus for controlling an image generation and output operation based on an instruction received from a server in an image processing system. The server includes a first memory to store first image processing data applicable to an image processing for outputting a target image, first circuitry to generate first image drawing information based on output target image information and the first image processing data when performing an image forming operation. The image generation-output control apparatus includes second circuitry, having one or more capabilities compatible with one or more capabilities of the first circuitry of the server. The second circuitry generates second image drawing information based on the output target image information and the first image processing data acquired from the server, and instructs an image forming apparatus to perform an image forming operation based on the generated second image drawing information.

Abstract: Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.

Abstract: Techniques are described for distributing, to a distributed network of central stations, alarm events detected in monitoring system data collected by sensors included in monitoring systems located at monitored properties. A system receives monitoring system data collected by sensors included in monitoring systems located at monitored properties, tracks alarm events detected within the monitoring system data, and generates, for central station servers in a distributed network of central stations, load profiles that reflect a volume of alarm events being handled at each of the central station servers at a particular period of time. The system determines capacities to handle additional alarm events for the central station servers, determines relative priorities for the central station remote servers based on the determined capacities, and directs subsequent alarm events to the central station servers based on the relative priorities.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.

Abstract: A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP) including a profiling unit used to provide performance statistics data for the GPU to determine a rendering mode of the GPU, wherein the rendering mode includes a first rendering mode and a second rendering mode for performing a graphics rendering pipeline for graphics processing. The profiling unit calculates drawing time of frames and the number of objects in the frames when the GPU operates in the first rendering mode, and determines whether the operation of the GPU is switched to the second rendering mode according to the calculated drawing time and the number of objects; when determining that the calculated drawing time and the number of objects are less than their respective thresholds, the CSP causes the operation of the GPU to switch from the first rendering mode to the second rendering mode.

Abstract: Systems, apparatuses, and methods may provide for technology to process multi-resolution images by identifying pixels at a boundary between pixels of different resolutions, and selectively smoothing the identified pixels.

Abstract: A texture filtering unit includes a datapath block and a control block. The datapath block includes one or more parallel computation pipelines, each containing at least one hardware logic component configured to receive a plurality of inputs and generate an output value as part of a texture filtering operation. The control block includes a plurality of sequencers and an arbiter. Each sequencer executes a micro-program that defines a sequence of operations to be performed by the one or more pipelines in the datapath block as part of a texture filtering operation and the arbiter controls access, by the sequencers, to the one or more pipelines in the datapath based on predefined prioritization rules.

Abstract: To achieve prompt display of image data to be displayed as well as seamless display of consecutive image data, a host (10) of a display device (1) includes an image generation section (11) configured to generate image data and an image transferring section (12) configured to transfer the image data to a display control section. The image generation section is configured to: start generating, in a case where generation of image data was completed within less than a single unit period, image data for a subsequent frame after the single unit period has passed since the generation of the image data; and start generating, in a case where the generation of the image data was not completed within less than the single unit period, image data for a subsequent frame any time after completion of the generation of the image data.

Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.

Abstract: In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images via a shading program. In operation, the parallel processor causes a first set of execution threads to execute the shading program on a first portion of the input mesh to generate first geometry stored in an on-chip memory. The parallel processor also causes a second set of execution threads to execute the mesh shading program on a second portion of the input mesh to generate second geometry stored in the on-chip memory. Subsequently, the parallel processor reads the first geometry and the second geometry from the on-chip memory, and performs operations on the first geometry and the second geometry to generate a rendered image derived from the input mesh. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.

Abstract: An information processing apparatus, connectable with an image output apparatus, includes circuitry to receive image data of an image from a memory, acquire information of an image placement region of the image output apparatus, the image placement region being variable depending on a type of the image output apparatus, and the image is to be output on the image placement region of the image output apparatus, generate an output image by placing the image within the image placement region based on the image data of the image to be output, and the image placement region of the image output apparatus, and transmit the generated output image to the image output apparatus.

Abstract: Technologies related to intermediary graphics rendition are generally described. In some examples, an intermediary computing device may store graphics models in a model store. A server computing device may generate and send a compositing flow to the intermediary computing device. The compositing flow may comprise model identifiers and model rendering information. The intermediary computing device may retrieve models identified in the compositing flow from the model store, and provide the identified models and model rendering information to a Graphics Processing Unit (GPU) for rendering. The GPU may render graphics for delivery via a network to a client device.

Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.

Abstract: The present invention discloses a head-mounted display and a video data processing method thereof. The head-mounted display comprises: a video input module, a distortion processing module and a video output module. The head-mounted display divides each image frame in a video into a plurality of image blocks of symmetry according to a graphic correspondence of a distorted image after a distortion processing, performs a distortion processing of any one of the image blocks, and obtains data of the current image frame after the distortion processing according to the graphic correspondence.

Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving image information for a current frame, determining an amount of change between the current frame and a previous based on the image information for the current frame and image information for a previous frame and determining an adjustment of a frame time based on the amount of change between the current frame and the previous frame.

Abstract: Imaging systems and methods are disclosed for generating enhanced visual representations of captured data such as infrared image data. For example, the perceived color distance or contrast between colors representing adjacent output levels (e.g., temperature or infrared intensity levels) are enhanced in visual representations of infrared images. According to embodiments, infrared image data values representing a scene may be mapped according to a color palette implemented using complementary colors as adjacent (e.g., successive) base colors or a sequence of colors, that repeats a predetermine set of hues with varying saturation and/or intensity, thereby increasing the color contrast between pixels representing subtle temperature differences in the scene. The color palette can be enlarged by mapping a larger number of distinct output levels to a larger sequence of colors, for example by increasing the bit-depth of the color palette, such that color transitions look smoother and more natural.

Abstract: Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically.

Abstract: A microcontroller unit includes: a first arithmetic processing unit, which is able to access a data bus; a second arithmetic processing unit, which includes a processor capable of accessing the data bus, and a memory. The microcontroller unit performs a data transmitting process between peripheral circuits connected to the data bus; a first arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the data bus; and a second arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the memory. The memory stores arithmetic processing sequences in association with event signals transmitted from the peripheral circuits, and in response to input of the event signals, the processor executes the arithmetic processing sequences corresponding to the event signals.

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes designating a hardware shading unit of a graphics processing unit (GPU) to perform first shading operations associated with a first shader stage of a rendering pipeline. The process also includes switching operational modes of the hardware shading unit upon completion of the first shading operations. The process also includes performing, with the hardware shading unit of the GPU designated to perform the first shading operations, second shading operations associated with a second, different shader stage of the rendering pipeline.

Abstract: A graphics server and method for streaming rendered content via a remote graphics rendering service is provided. In one embodiment, the server includes a memory, a graphics renderer, a frame capturer, an encoder, and a processor. The memory is configured to store a pre-computed skip-frame message indicative to a client to re-use a previously transmitted frame of the video stream. The graphics renderer is configured to identify when rendered content has not changed. When the graphics renderer identifies that the rendered content has not changed, the processor is configured to cause: (1) the frame capturer to not capture the frames of the rendered content; (2) the encoder to not encode the frames of the rendered content; and (3) the pre-encoded skip-frame message to be transmitted without requiring any pixel processing.

Abstract: A method and a system for pipelining read transactions of a host computer from a storage module, including: transferring from a host computer to an accelerator a read list, including at least one pointer to a data block stored on the storage module, and a respective data block size; sending an acknowledgement to the host; fetching at least one data block by the accelerator from the storage module, and writing it to a staging buffer in a sequential order; sending at least one read request from the host computer to the accelerator, relating to at least one requested data block. If the data block is available on the staging buffer, then sending the corresponding data to the host from the staging buffer. Otherwise the read response is delayed until the requested data is fetched from the storage module.

Abstract: A data processing device which processes electronic data used by a board working machine is disclosed. The data processing device includes a status information processing section which performs at least one of writing processing, editing processing, and reading processing of status information, with respect to the electronic data. The status information at least illustrates whether or not the electronic data has not been completed. Preferably, the status information illustrates any of (1) the electronic data has not been completed, (2) the electronic data has been completed, and is waiting for a test by the board working machine, (3) the electronic data has been tested by the board working machine, and is waiting for authorization, and (4) the electronic data has been authorized.

Abstract: Disclosed is a method for testing touch screen displays during manufacture. A touch screen controller (TSC) is packaged, and the analog channels of the TSC are characterized, with resulting data being stored for later use. The TSC is programmed, and the touch screen display and TSC are packaged together. The touch screen display is tested using firmware in the TSC, enabling calculation of the inherent capacitances between force and sense lines of the touch screen display when connected to the TSC during operation. The testing involves, for each force and sense line pair, measuring an output signal generated by a receive channel of the TSC coupled to the sense line of that pair. Based upon the data gathered during characterization, and the signals measured during testing, the capacity of the touch screen display is then calculated.

Abstract: A data processing apparatus (100) executes threads and includes a general program counter (PC) (120) identifying an instruction to be executed for at least a subset of the threads. Each thread has a thread PC (184). The subset of threads has at least one lock parameter (188, 500-504) for tracking exclusive access to shared resources. In response to a first instruction executed for a thread, the processor (160) modifies the at least one lock parameter (188), (500-504) to indicate that the thread has gained exclusive access to the shared resource. In response to a second instruction, the processor modifies the at least one lock parameter (188, 500-504) to indicate that the thread no longer has exclusive access. A selector (110) selects one of the subset of threads based on the at least one lock parameter (188, 500-504) and sets the general PC (120) to the thread PC (184) of the selected thread.

Abstract: A method of managing graphics data in a graphics processing device may include: receiving a first draw call having a first identifier, generating a first lookup table having the first identifier mapped in association with a first handle value by allocating the first handle value to the first identifier, generating a second lookup table having the first handle value mapped in association with a first graphics state setting value by allocating the first handle value to the first graphics state setting value, wherein the first graphics state setting value corresponds to the first identifier, and performing at least one graphics pipeline operation to process the first draw call by using the first graphics state setting value obtained from the second lookup table.

Abstract: A display controller 10 comprises a first display processing core 20 comprising a first input stage operable to read at least one input surface, a first processing stage operable to generate an output surface, a first output stage operable to provide an output surface for display to a first display 3, and a first write-out stage 27 operable to write data of an output surface to external memory 1, and a second display processing core 40 comprising a second input stage operable to read at least one input surface, a second processing stage operable to generate an output surface, and a second output stage operable to provide an output surface for display to a second display 5. The display controller 10 also comprises an internal data path 30 for passing data of an output surface from the first display core 20 to the second display core 40.

Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.

Abstract: Methods and apparatuses relating to memory compression and decompression are described, including a memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match. When indices for multiple sections are the same, an entry in the dictionary may be updated with the value of the section that is most recent, in the same order as in the block of data.

Abstract: A first non-deterministic read command from a command queue is selected to be issued. The command queue includes non-deterministic read commands including the first non-deterministic read command that are outstanding and placed in the wait state simultaneously. A first intermediate response from a non-volatile memory component is received that indicates that data associated with one of the outstanding non-deterministic read commands is available. A first send command is inserted into a send queue when the first intermediate response is received. The first send command is selected from the send queue to be issued and removed from the send queue. A response to a corresponding non-deterministic read command is received. The corresponding non-deterministic read command is one of the outstanding non-deterministic read commands. The response indicates the corresponding non-deterministic read command and includes data associated with corresponding non-deterministic read command.

Abstract: An object of the present invention is to further reduce the power consumption of a display device adopting pause driving. In a display device that includes a display driving unit (30) that drives a display unit (400); and a power supply circuit (20) that generates a plurality of operation voltages to be supplied to the display driving unit (30), and performs pause driving that repeats a scanning period during which gate bus lines (GL) are scanned and a pause period during which the scanning of the gate bus lines (GL) is stopped, the display driving unit (30) provides a control signal (SM) indicating whether the current point in time is the scanning period or the pause period, to the power supply circuit (20), and the power supply circuit (20) makes the voltage value of at least one of the plurality of operation voltages supplied to the display driving unit (30) smaller during the pause period than during the scanning period, based on the control signal (SM).

Abstract: A macro cell video compression system and related method, the system including a first raster device and a second raster device that is cross-linked to the first raster device to move macro cells between the linked first and second raster devices, each of the first and second raster devices comprising a video raster circuit having a raster phase locking circuit to perform frame locking and pixel locking between the first and second raster devices and to generate macro cells by one of the first and second raster devices, each of the first and second raster devices has two or more raster heads that generate the macro cells by pixel clock stalling.

Abstract: Methods and apparatus to convert a non-series-parallel control flow graph to data flow. An example apparatus includes a node analyzer to detect a non-series-parallel node in sequential code, and an instruction generator to: generate instructions for prior nodes associated with the detected non-series-parallel node including a consumption operand, generate a combination instruction to combine results of the instructions generated for the prior nodes, and output the combination instructions and the instructions generated for the prior nodes to generate data flow code.

Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

Abstract: A method of compressing image data involves determining an active area of an image to be displayed, at least part of which changes from frame to frame to provide a moving image. Color values for each pixel in at least part of the active area that has changed are determined (S73) and a resolution of a blue component of the color values is dynamically reduced (S75) relative to resolutions of green and red components of the color values. The image data is then transmitted, together with error correction information indicating how to correct the blue component when the image data is displayed. The active area may be a particularly fast changing part of the image or an area on which a user is focused.

Abstract: A graphics processing unit (GPU) service platform includes a control server, and a cluster of GPU servers each having one or more GPU devices. The control server receives a service request from a client system for GPU processing services, allocates multiple GPU servers within the cluster to handle GPU processing tasks specified by the service request by logically binding the allocated GPU servers, and designating one of the at least two GPU servers as a master server, and send connection information to the client system to enable the client system to connect to the master server. The master GPU server receives a block of GPU program code transmitted from the client system, which is associated with the GPU processing tasks specified by the service request, processes the block of GPU program code using the GPU devices of the logically bound GPU servers, and returns processing results to the client system.

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.

Abstract: Flexible, dynamic, and efficient compression and de-compression mechanisms are described. An example compression mechanism includes reading a plurality of groups of indices, identifying a smallest index in each of the plurality of groups, rotating indices in each of the plurality of groups such that the smallest index is a first value, calculating unsigned delta encoded values relative to the smallest index in each of the plurality of groups for remaining indices, converting the plurality of groups of indices into a plurality of compressed groups of indices, and storing the plurality of compressed groups of indices. An example de-compression mechanism include reading a plurality of compressed groups of indices, identifying a first index as an absolute value in each of the plurality of groups, calculating remaining indices of each of the plurality of groups, and converting the plurality of compressed groups of indices into a plurality of decompressed groups of indices.

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

Abstract: This disclosure pertains to the operation of graphics systems and to a variety of architectures for design and/or operation of a graphics system spanning from the output of an application program and extending to the presentation of visual content in the form of pixels or otherwise. In general, many embodiments of the invention contemplate a high level graphics framework to receive graphic requests from an application. The graphics request is analyzed by the high-level framework and sorted into groups of command statements for execution. The command statements are sorted to cause the most efficient processing by the underlying hardware and the groups are submitted separately to a GPU using a low-level standard library that facilitates close control of the hardware functionality.

Abstract: Technologies for offloading an application for processing a network packet to a graphics processing unit (GPU) of a network device. The network device is configured to determine resource criteria of the application and available resources of the GPU. The network device is further configured to determine whether the available GPU resources are sufficient to process the application based on the resource criteria of the application and the available GPU resources. Additionally, the network device is configured to determine one or more estimated GPU performance metrics based on the resource criteria of the application and the available GPU resources to determine whether to offload the application to the GPU. Other embodiments are described and claimed.

Abstract: A method for color index coding of blocks in a picture is disclosed. In one embodiment for the decoder side, a current coding mode is parsed from the input coded bitstream for one or more first currently decoded pixels in a current block starting from a first starting position. If the current coding mode corresponds to a generalized copy-previous-row mode, one or more first reference pixels starting from a first starting reference position located at T-th row above the first currently decoded pixels are identified, where T is an integer equal to or greater than one. The first reference pixels starting from the first starting reference position are then used to decode the first currently decoded pixels starting from a first starting position by copying the first reference pixels starting from the first starting reference position respectively. The system may also include a copy-left mode or escape mode.

Abstract: An electronic apparatus includes a locking unit to selectively lock a physical connection with an external apparatus and a control unit to control an operation mode of the electronic apparatus, according to a connection state with the external apparatus, in which the control unit controls the locking unit to lock the connection with the external apparatus, when the electronic apparatus is in an operation mode of using a graphic processing unit of the external apparatus.

Abstract: A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.