Abstract: The present invention relates to a multi-layer ceramic capacitor printed simultaneously with internal electrode and external electrode by employing an inkjet printing. A method for manufacturing the multi-layer ceramic capacitor comprising first external electrode, dielectric, internal electrode and second external electrode prints simultaneously the first external electrode; the internal electrode which is connected with the first external electrode and formed at an invaginated portion of the dielectric invaginated to allow one side to be opened at one portion; and the second external electrode which is formed integrally with the internal electrode by employing an inkjet printing. According to the present invention, a method for manufacturing the multi-layer ceramic capacitor resolves contact problems by printing integrally the internal electrode and the external electrode and reduces the manufacturing process.

Abstract: A multilayer capacitor includes a capacitor body having rectangular first and second main faces opposing each other, first and second end faces extending in a shorter side direction of the first and second main faces so as to connect the first and second main faces to each other, and first and second side faces extending in a longer side direction of the first and second main faces so as to connect the first and second main faces to each other. First and second terminal electrodes are arranged on the first and second side faces of the capacitor body, respectively. A first inner electrode connected to the first terminal electrode, a second inner electrode connected to the second terminal electrode, and first and second intermediate electrodes connected to none of the first and second terminal electrodes are arranged within the capacitor body.

Abstract: A chip-type electronic component has: a ceramic element body; a plurality of first and second internal electrodes arranged in the ceramic element body so as to be opposed at least in part to each other; a first external connection conductor to which the plurality of first internal electrodes are connected; a second external connection conductor to which the plurality of second internal electrodes are connected; first and second terminal electrodes; a first internal connection conductor arranged in the ceramic element body and connecting the first external connection conductor and the first terminal electrode; and a second internal connection conductor arranged in the ceramic element body and connecting the second external connection conductor and the second terminal electrode.

Abstract: A switch module consists of a build-up multi-layer structure and some passive devices. The build-up multi-layer structure has multitudes of conductive layers and dielectric layers laminated upon each another. At least one dielectric layer is interfered between any two conductive layers. Any one passive device is a portion of at least one conductive layer and electrically connects multitudes of conductive pads on the surface of the build-up multi-layer structure.

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract: An apparatus includes a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits. Such capacitor may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit (IC) such as a microprocessor. The capacitor supplying and moderating power to the microprocessor needs to be closely coupled in order to respond to instantaneous power demands that may be found in high clock rate microprocessors, and the space inside a microprocessor package is very restricted.

Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

Abstract: A three-dimensional capacitor is formed from a multilayer of superposed electrodes. The electrodes are formed within respective metallization levels of an integrated circuit. At least two additional superposed electrodes are formed on top of the multilayer. Each additional electrode is formed from a branched rectilinear structure including at least one bar aligned in a first direction and a plurality of branches extending from that at least one bar in a second direction.

Abstract: Disclosed is multilayer ceramic capacitor. The multilayer ceramic capacitor includes a capacitive part including dielectric layers and first and second internal electrodes alternately laminated therein, wherein the dielectric layers include first ceramic particles having an average particle size of 0.1 ?m to 0.3 ?m, and one set of ends of the first internal electrodes and one set of ends of the second internal electrodes are exposed in a lamination direction of the dielectric layers, a protective layer formed on at least one of top and bottom surfaces of the capacitive part, including second ceramic particles and having a porosity of 2% to 4%, wherein an average particle size ratio of the second ceramic particles to the first ceramic particles ranges from 1.1 to 1.3; and first and second external electrodes electrically connected to the first and second internal electrodes exposed in the lamination direction of the dielectric layers.

Abstract: A multilayer chip capacitor including: a capacitor body formed of a lamination of a plurality of dielectric layers and having a bottom surface that is a mounting area; a plurality of internal electrodes disposed to be opposite to each other, interposing a dielectric layer there between in the capacitor body and having one lead extended to the bottom surface, respectively; and three or more external electrodes formed on the bottom surface and connected to corresponding internal electrodes via the leads, wherein the internal electrodes are vertically disposed on the bottom surface, and the leads of the internal electrodes having a different polarity from each other, adjacent to each other in a lamination direction, are disposed to be always adjacent to each other in a horizontal direction.

Abstract: At least one of a plurality of first internal electrodes and a second internal electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth internal electrodes are arranged as opposed with at least one of the dielectric layers in between. The first internal electrodes are electrically connected to a first external connecting conductor through lead conductors. The second, third, and fourth internal electrodes are electrically connected to second, third, and fourth terminal conductors, respectively, through lead conductors. At last one but not all of the first internal electrodes are electrically connected to the first terminal conductor through a lead conductor.

Abstract: A multilayer capacitor 1 comprises a capacitor element body 2 constituted by a plurality of dielectric layers 10; inner electrodes 3, 4, disposed within the capacitor element body 2, having main electrode parts 31, 41 separated by a distance Wg from third and fourth side faces 2c, 2d; and terminal electrodes 5, 6 disposed on respective end faces 2e, 2f and a part of first to fourth side faces 2a to 2d. The inner electrodes 3, 4 are alternately laminated with the dielectric layer 10. The distance Cv between the inner electrode 3, 4 at the outermost layer on each of the first and second side face 2a, 2b sides and the first or second side face 2a, 2b adjacent to the inner electrode 3, 4 is shorter than the distance Wg between the main electrode part 31, 41 and the third or fourth side face 2c, 2d.

Abstract: In a monolithic ceramic capacitor, the size of end surfaces of a capacitor body in a two-dimensional surface in which ceramic layers extend is greater than the size of side surfaces in the two-dimensional surface in which the ceramic layers extend. External terminal electrodes include a resistive component. In each of first to fourth internal electrodes, a width-direction size of a lead-out portion is less than a width-direction size of a capacitance portion. The lead-out portions of the first and third internal electrodes and the lead-out portions of the second and fourth internal electrodes are arranged so as to partially overlap each other or not to overlap each other.

Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.

Abstract: Disclosed is a multilayer capacitor capable of improving adhesiveness of layers of an element body and improving reliability. Outer edge 12a, 12c, and 12d of a second principal-surface electrode portion 12 are respectively separated from an end surface 1a and lateral surfaces 1e and 1f, and are respectively arranged so as to surround the forefront portion of a third principal-surface electrode portion 21 at one end 1A side when viewed from a lamination direction. Outer edges 22a, 22c, and 22d of a fourth principal-surface electrode portion 22 are respectively separated from an end surface 1b and lateral surfaces 1e and 1f, and are arranged so as to surround the forefront portion of a first principal-surface electrode portion 11 in the width direction at the other end 1B side when viewed from the lamination direction.

Abstract: Disclosed is a multilayer capacitor capable of improving reliability and further reducing ESL. In a width direction, a second principal-surface electrode portion is greater than a first principal-surface electrode portion, and a fifth principal-surface electrode portion is greater than a fourth principal-surface electrode portion. When viewed from a lamination direction, an outer edge of the second principal-surface electrode portion at the other end side is arranged near the other end side more than outer edge of the fifth principal-surface electrode portion at one end side. First lead portions are connected to the second principal-surface electrode portion, and second lead portions are connected to the fifth principal-surface electrode portion.

Abstract: A method for manufacturing a laminated ceramic capacitor includes a step of preparing a laminate which has a first principal surface, a second principal surface, a first end surface, a second end surface, a first side surface, and a second side surface and which includes insulating layers and internal electrodes having end portions exposed at the first or second end surface; a step of forming external electrodes on the first and second end surfaces such that plating deposits are formed on the exposed end portions of the internal electrodes so as to be connected to each other; and a step of forming thick end electrodes electrically connected to the external electrodes such that a conductive paste is applied onto edge portions of the first and second principal surfaces and first and second side surfaces of the laminate and then baked.

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract: A method of manufacturing a chip capacitor according to an aspect may include: preparing a capacitor lamination including a dielectric sheet formed of a composite having ceramic powder and a polymer mixed with each other, and first and second internal electrodes formed on both surfaces of the dielectric sheet at predetermined intervals; forming covering layers formed of an insulating material on both surfaces of the capacitor lamination; forming a first opening and a second opening in the capacitor lamination having the covering layers formed thereon to expose the first and second internal electrodes, respectively; forming plating layers in the first and second openings, the plating layers connected to the first and second internal electrodes; and dicing the capacitor lamination into chips on the basis of the first and second openings so that the plating layers formed in the first and second openings are provided as first and second external terminals.

Abstract: Systems and apparatus are provided for capacitor segments for use in a vehicle. A capacitor segment comprises an inner conductor configured to receive a first potential and having a generally L-shaped longitudinal cross-section. An outer conductor is configured to receive a second potential, and is electrically insulated from the inner conductor. The outer conductor comprises a first section having a generally L-shaped longitudinal cross-section aligned with the inner conductor, and a second section coupled to the first section and having a generally L-shaped lateral cross-section. The second section and the inner conductor define an inner region. A capacitor is located in the inner region and coupled to the inner conductor and the second section. The capacitor segment is configured such that current flows through the capacitor in a first direction, and current flows through the second section in a second direction that generally opposes the first direction.

Abstract: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.

Abstract: In a multilayer capacitor, widths of lead conductors of internal electrode and widths of lead conductors of internal electrode in an ESR control section are smaller than any one of widths of internal electrode and widths of internal electrode in a capacitance section. This narrows cross sections of the conductor portions connecting between the internal electrodes and the external electrodes, so as to her increase ESR. The widths of the respective lead conductors in the ESR control section are wider than widths of respective lead conductors in the capacitance section. This effectively prevents open failure and improves a yield of products.

Abstract: A capacitor element includes a pair of conductor layers, a plurality of generally tube-shaped dielectric substances, a first electrode outside the dielectric substances and second electrodes in the insides thereof, and insulation caps for insulating the first electrode from the conductor layer, wherein an electrode material is filled in gaps of a structure of an oxide base material resulting from anodic oxidation of a metal, and then, the structure is removed and replaced by a high permittivity material.

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

Abstract: A multilayer capacitor includes a laminate of ceramic layers, and a capacitor unit provided in the laminate. In the multilayer capacitor, the relationships P?Ra and P?W are established, wherein P represents the average projection height of first and second via conductors from the upper surface, Ra represents the surface roughness of the upper surface, and W represents an amount of curvature of the laminate. Further, the projecting portions of the first and second via conductors projecting from the upper surface are buried in first and second external electrodes, respectively.

Abstract: A capacitance element includes a first electrode, a second electrode, a third electrode, a fourth electrode, a first dielectric portion, a second dielectric portion, and a third dielectric portion. To the first electrode, a signal having a first polarity is applied. To the second electrode, a signal having a second polarity is applied. The second polarity is opposite to the first polarity. To the third electrode, the signal having the second polarity is applied. The third electrode is disposed on a position opposed to the second electrode. To the fourth electrode, the signal having the first polarity is applied. The first dielectric portion is provided between the first electrode and the second electrode. The second dielectric portion is provided between the second electrode and the third electrode. The third dielectric portion is provided between the third electrode and the fourth electrode.

Abstract: An integrated multilayer chip capacitor module including: plurality of multilayer chip capacitors arranged close to one another and co-planar with one another; and a capacitor support accommodating the multilayer chip capacitors, wherein each of the multilayer chip capacitors includes a rectangular parallelepiped capacitor body and a plurality of first and second external electrodes formed on at least two sides of the capacitor body, and the external electrodes on adjacent sides of adjacent ones of the multilayer chip capacitor in the capacitor support are electrically connected to each other by a conductive adhesive material.

Abstract: The formation of electronic assemblies is described. One embodiment includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first metal pad layer, the second metal pad layer having a denser pitch than the first metal pad layer. A dielectric layer is formed between the metal pads in the first and second metal pad layers. Vias extending through the body from a second surface thereof are formed, the vias exposing the first metal pad layer. An insulating layer is formed on via sidewalls and on the second surface, and an electrically conductive layer formed on the insulating layer and on the exposed surface of the first metal layer. Elements are coupled to the second metal pad layer and the electrically conductive layer coupled to a substrate. Other embodiments are described and claimed.

Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes M×N capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

Abstract: A feedthrough capacitor having a pair of first terminal electrodes and a second terminal electrode is mounted on a mounting surface of a substrate. The substrate is an insulating substrate internally having first and second conductor portions isolated from each other, and has a plurality of first via holes, a plurality of second via holes, a plurality of first land electrodes, and a second land electrode. The first via holes and the second via holes, when viewed from the mounting surface side, are arranged in a matrix pattern and alternately arranged in a row direction and in a column direction. The feedthrough capacitor, when viewed from the mounting surface side, is located between a pair of said first via holes adjacent to each other in a direction intersecting with the row direction and also adjacent to each other in a direction intersecting with the column direction.

Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Abstract: A method of fabricating an integrated circuit device includes forming a plurality of lower capacitor electrodes vertically extending from a substrate. The plurality of lower capacitor electrodes respectively include an inner sidewall and an outer sidewall. At least one support pattern is formed vertically extending between ones of the plurality of lower capacitor electrodes from top portions thereof opposite the substrate and along the outer sidewalls thereof towards the substrate to a depth that is greater than a lateral distance between adjacent ones of the plurality of lower capacitor electrodes. A dielectric layer is formed on the support pattern and on outer sidewalls of the plurality of lower capacitor electrodes, and an upper capacitor electrode is formed on the dielectric layer. Related devices are also discussed.

Abstract: Disclosed are embodiments of a method of forming a capacitor with inter-digitated vertical plates such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

Abstract: New designs for multilayer ceramic capacitors are described with high voltage capability without the need of coating the part to resist surface arc-over. One design combines a high overlap area for higher capacitance whilst retaining a high voltage capability. A variation of this design has increased voltage capability over this design as well as another described in the prior art although overlap area and subsequently capacitance is lowered in this case. These designs are compared to the prior art in examples below.

Abstract: A multilayer ceramic capacitor includes first internal electrodes extending to a first end surface of a ceramic element assembly, a plurality of second internal electrodes extending to a second end surface, floating internal electrodes arranged so as to overlap the first and second internal electrodes with ceramic layers disposed therebetween to define first and second effective regions, inner conductors that are elongated from the first end surface beyond a region that overlaps the first effective region in the direction of layering, and a relationship X1<Y1<(L?E) is satisfied where L is the dimension in the longitudinal direction extending from the first end surface to the second end surface, X1 is the longitudinal-direction dimension of each of the first internal electrodes, Y1 is the distance between the first end surface and an end of each of the first internal electrodes, and E is the distance between the second end surface and an end of the second extended section.

Abstract: A metal alloy powder containing at least two alloying elements selected from the group of Ni, Cu, Cr, Sn, Mn, Co and W containing 1 to 99% by weight Ni, 1 to 99% by weight Cu, 6 to 60% by weight Cr, 6 to 15% by weight Sn, 6 to 15% by weight Mn, 6 to 15% by weight Co, and/or 6 to 15% by weight W for use in laminated ceramic capacitors with an internal electrode wherein said electrode comprises a sintered body of said alloy powder. A metal alloy powder containing at least two alloying elements selected from the group of Ni, Cu, Cr, Sn, Mn, Co and W wherein the onset of oxidation of the alloy powder occurs above about 250° C.

Abstract: A multilayer capacitor has a capacitor element body, first and second terminal electrodes, and a connection conductor. The capacitor element body has a plurality of insulator layers laminated, and a plurality of first and second internal electrodes arranged with at least one of the insulator layers in between. The first and second terminal electrodes are disposed on one external surface extending parallel to a laminating direction of the insulator layers. The connection conductor is disposed on an exterior surface extending parallel to the laminating direction of the insulator layers. The first internal electrodes include two types of internal electrodes, a type of internal electrode connected to the first terminal electrode and the connection conductor and a type of internal electrode connected to the connection conductor only. The second internal electrodes are connected to the second terminal electrode.

Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.

Abstract: An MOM capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one oxide layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: A method for manufacturing a laminated electronic component includes the steps of preparing a component main body having a laminated structure, the component main body including a plurality of internal electrodes formed therein, and each of the internal electrodes being partially exposed on an external surface of the component main body, and forming an external terminal electrode on the external surface of the component main body such that the external terminal electrode is electrically connected to the internal electrodes. The step of forming the external terminal electrode includes the steps of forming a metal layer on exposed surfaces of the internal electrodes of the component main body, applying a water repellant on at least a surface of the metal layer and on a section of the external surface of the component main body at which an end edge of the metal layer is located, and then forming a conductive resin layer on the metal layer having the water repellant applied thereon.

Abstract: A multilayer capacitor has a capacitor element body in which a plurality of insulator layers are laminated, first and second terminal electrodes, a first internal electrode group, and a second internal electrode group. The first and second terminal electrodes are disposed on an external surface extending in a direction parallel to a laminating direction of the insulator layers, among external surfaces of the capacitor element body. The first internal electrode group has a first internal electrode connected to the first terminal electrode, and a second internal electrode connected to the second terminal electrode. The second internal electrode group has a third internal electrode connected to the first terminal electrode, a fourth internal electrode connected to the second terminal electrode, and at least one intermediate internal electrode not connected to the first and second terminal electrodes.

Abstract: An electronic component and an electronic-component production method in which the magnitude of a stray capacitance produced between adjacent outer electrodes is controllable. The electronic component includes a chip body and first to fourth outer electrodes. In the chip body, first and second coil block are sandwiched between magnetic substrates. Dielectric layers are interposed between the outer electrodes and the chip body such as to be away from exposed portions of coil patterns in the coil blocks. The dielectric layers have a width larger than a width of the outer electrodes, and a dielectric constant of the dielectric layers is set to be lower than the dielectric constant of the magnetic substrates.

Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed on a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).

Abstract: A method of manufacturing a multilayer capacitor comprises a first layer forming step, a first electrode forming step, a second layer forming step, a second electrode forming step, a separation step, an element forming step and a terminal forming step. In the first layer forming step, a first ceramic green layer is formed on a supporting body. In the first electrode forming step, a first electrode pattern is formed on the first ceramic green layer. In the second layer forming step, a second ceramic green layer is formed laminated on the first ceramic green layer. In the second electrode forming step, a second electrode pattern is formed at the second ceramic green layer. In the separation step, the support body is separated from the laminated body. In the element forming step, elements are formed by laminating a plurality of the laminated bodies.

Abstract: In a laminated ceramic electronic component including a ceramic element body including a plurality of effective sections, each of which constitutes a circuit element such as a laminated capacitor unit, bumps generated between the effective portions and a gap interposed between the effective portions can be made minimized. Specifically, the ceramic element body includes a first effective section including a first circuit element and a second effective section including a second circuit element. A gap is provided between the first and second effective section. Floating internal conductors are arranged in the gap at least in one of first and second external layer sections, the first external section being interposed between a first main surface and the first and second effective sections, and the second external layer section being interposed between a second main surface and the first and second effective sections.

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract: In an LW-reverse-type monolithic ceramic capacitor including external terminal electrodes each including a resistance component, internal electrodes include nickel or a nickel alloy, and the external terminal electrodes each include a first layer, a second layer provided on the first layer, and a third layer provided on the second layer. The first layer has a wrap-around portion extending from an end surface to principal surfaces and side surfaces of a capacitor main body, and contains a glass component and a compound oxide that reacts with Ni or the Ni alloy. The second layer covers the first layer such that the edge of the wrap-around portion of the first layer remains exposed, and contains a metal. The third layer covers the edge of the wrap-around portion of the first layer and the second layer, and is formed by plating.

Abstract: A multi-layered ceramic capacitor with at least one chip and with first base metal plates in a parallel spaced apart relationship and second base metal plates in a parallel spaced apart relationship wherein the first plates and second plates are interleaved. A dielectric is between the first base metal plates and said second base metal plates and the dielectric has a first coefficient of thermal expansion. A first termination is in electrical contact with the first plates and a second termination is in electrical contact with the second plates. Lead frames are attached to, and in electrical contact with, the terminations wherein the lead frames have a second coefficient of thermal expansion and the second coefficient of thermal expansion is higher than said first coefficient of thermal expansion. The lead frame is a non-ferrous material.