Abstract: In order to avoid the capacitors in a stacked capacitor structure suiting a miniaturization process from collapsing to cause a short-circuit, separated reinforced structures are used and disposed at the outer-sidewalls of the capacitor, which not only reduces the space occupied by the reinforced structure to increase the surface areas of the upper electrode and the lower electrode of the capacitor, but also allows the capacitor to be deflected but collapse-proof and there are more spaces between the capacitors, so as to solve the filling difficulty problem due to a too small filling space in a successive process of depositing conductive material into the filling space.

Abstract: A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor. The decoupling capacitor is formed of an NFET transistor and a PFET transistor, the PFET transistor being substantially formed in the n-type portion and the NFET transistor being substantially formed in the p-type portion, a boundary between the n-type portion and the p-type portion being substantially straight. The transistors are arranged such that a source and drain of the PFET transistor are connected to a high voltage rail and a source and drain of the NFET transistor are connected to a low voltage rail.

Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.

Abstract: An electronic component includes a substantially rectangular parallelepiped electronic component body and first to fourth external electrodes. The first to fourth external electrodes are arranged such that a shaped defined by joining the centers of portions of the first to fourth external electrodes on a first main surface with a substantially straight line is substantially square. The first main surface is provided with a substantially linear orientation identifying mark disposed thereon. The orientation identifying mark passes through an intersection of two diagonals of the substantially square shape and extends along the longitudinal direction or the width direction.

Abstract: There are a plurality of types of first internal electrodes and each type of first internal electrode includes a first main electrode portion and a first lead portion. A second internal electrode includes a plurality of second main electrode portions forming respective capacitance components with the respective types of first internal electrodes, an interconnection portion connecting between each pair of second main electrode portions, and a second lead portion. Positions of the first lead portions of the respective types of first internal electrodes are different from each other and distances from the first lead portions of the respective types of first internal electrodes to the second lead portion are different from each other. The width of the interconnection portion is smaller than the width of at least one second main electrode portion out of the plurality of second main electrode portions.

Abstract: A multilayer ceramic electronic component includes external terminal electrodes that are formed by depositing metal plating films on exposed portions of internal conductors embedded in a ceramic body, depositing a copper plating films that cover the metal plating films and make contact with the ceramic body around the metal plating films, and heat-treating the ceramic body to generate a copper liquid phase, an oxygen liquid phase, and a copper solid phase between the copper plating films and the ceramic body. The mixed phase including these phases forms a region at which a copper oxide is present in a discontinuous manner inside the copper plating film at least at the interfaces between the ceramic body and the copper plating films. The copper oxide securely attaches the copper plating films to the ceramic body and enhances the bonding force of the external terminal electrodes.

Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via.

Abstract: A multilayer ceramic capacitor component includes a ceramic capacitor body having opposite ends and comprised of a plurality of electrode layers and dielectric layers, first and second external terminals attached to the ceramic capacitor body. The plurality of electrode layers include a plurality of alternating layers of active electrodes extending inwardly from alternating ends of the ceramic capacitor body. The capacitor may include a plurality of side shields disposed within the plurality of alternating layers of active electrodes to provide shielding with the alternating layers of active electrodes having a pattern to increase overlap area to provide higher capacitance without decreasing separation between the alternative layers of active electrodes. The capacitor may have a voltage breakdown of 3500 volts DC or more in air. The capacitor may have a coating. The capacitor provides improved resistance to arc-over, high voltage breakdown in air, and allows for small case size.

Abstract: A ceramic electronic component has a ceramic element assembly, external electrodes, and metal terminals. The external electrodes are arranged on the surface of the ceramic element assembly. The external electrodes contain a sintered metal. The metal terminals are electrically connected to the external electrodes, respectively. The external electrode and the metal terminal are directly diffusion-bonded by diffusion of metal in the metal terminals into the external electrodes. The above arrangement provides a ceramic electronic component having highly reliable metal particle bonding and a method for manufacturing the same.

Abstract: In a capacitor body of a multilayer capacitor, one second capacitor portion is sandwiched between two first capacitor portions. An ESR is controlled by setting a width of lead portions of third and fourth internal electrodes disposed in the second capacitor portion to be less than that of lead portions of first and second internal electrodes disposed in the first capacitor portions and by changing ratios between the first and second capacitor portions in the width of the lead portions and in the number of stacked internal electrodes. In the first capacitor portions, current paths from the internal electrodes to an external terminal electrode are widely distributed so that the first capacitor portions have a relatively low ESL, and accordingly, the ESL of the entire multilayer capacitor is reduced.

Abstract: Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.

Abstract: An element body has a major capacitance forming portion to form a first capacitance, and a minor capacitance forming portion to form a plurality of second capacitances smaller than the first capacitance. The major capacitance forming portion includes a first internal electrode connected to a first terminal electrode, and a second internal electrode opposed to the first internal electrode and connected to a second terminal electrode.

Abstract: A multilayer capacitor array achieves a high ESR because terminal conductors to which internal electrodes in capacitance sections are connected in parallel are connected in series through internal electrodes in ESR control sections to external electrodes. Since in the multilayer capacitor array the internal electrodes extend as far as a boundary between capacitor element portions, electrostriction occurs in an entire laminate including a region near the boundary between the capacitor element portions, with application of a voltage from the outside. Therefore, concentration of stress due to electrostriction is avoided, so as to suppress occurrence of cracking or the like.

Abstract: A laminated ceramic capacitor capable of achieving both a high dielectric constant and high electrical insulation property even when the thickness of the dielectric ceramic layer is less than 1 ?m, contains a plurality of laminated dielectric ceramic layers and a plurality of internal electrodes at interfaces between the dielectric ceramic layers, where dielectric ceramic layers are made of dielectric ceramic containing a perovskite-type compound represented by ABO3 as a main ingredient, and R (R is La or the like), M (M is Mn or the like) and Si as accessory ingredients.

Abstract: A multilayer capacitor comprises a capacitor element body constituted by a plurality of laminated dielectric layers; first and second signal terminal electrodes and a ground terminal electrode which are arranged on an outer surface of the capacitor element body; and a ground electrode, first and second signal electrodes, and an intermediate internal electrode which are arranged within the capacitor element body. The first signal electrode is connected to the first signal terminal electrode, while the second signal electrode is connected to the second signal terminal electrode. The ground electrode is connected to the ground terminal electrode and has a first region overlapping the first signal electrode in a first direction in which the plurality of dielectric layers are laminated and a second region overlapping the second signal electrode in the first direction.

Abstract: Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a continuous concentration gradient of a second component relative to a first component. The continuous concentration gradient may correspond to a decreasing concentration of the second component as a distance from the first capacitor electrode increases. The first component may be selected from the group consisting of zirconium oxide, hafnium oxide and mixtures thereof; and the second component may be selected from the group consisting of niobium oxide, titanium oxide, strontium oxide and mixtures thereof. A second capacitor electrode may be formed over the first capacitor electrode. Some embodiments include capacitors that contain at least one metal oxide mixture having a continuous concentration gradient of the above-described second component relative to the above-described first component.

Abstract: A capacitor includes a first terminal having a first polarity, a second terminal having a second polarity opposed to the first polarity, and a plurality of columnar portions for connecting the first terminal to the second terminal. Each of the plurality of columnar portions includes a first conductor bar electrically connected to the first terminal, a second conductor bar electrically connected to the second terminal, and a dielectric layer between the first and second conductor bars.

Abstract: A monolithic ceramic electronic component includes a laminate including a plurality of stacked ceramic layers and a plurality of internal electrodes extending between the ceramic layers and also includes external electrodes disposed on the laminate. The internal electrodes are partly exposed at surfaces of the laminate and are electrically connected to each other with the external electrodes. The external electrodes include first plating layers and second plating layers. The first plating layers are in direct contact with the internal electrodes. The second plating layers are located outside the first plating layers and contain glass particles dispersed therein.

Abstract: A ceramic electronic component that is hardly influenced by a stress generated when an external electrode containing a metal sintered compact is formed at the end of the ceramic component body, and a method for manufacturing the same are provided. A laminated ceramic capacitor includes a ceramic component body and first electrodes to be connected to internal electrodes that are led to the end surfaces are formed. The first external electrodes are arranged so that the ends are spaced apart from the side surfaces of the ceramic component body. Second external electrodes containing a conductive resin are arranged so as to entirely cover the first electrodes and first and second metal layers and are formed thereon. The first external electrodes are formed by supplying a conductive paste containing conductive metal powder and glass frit having a softening point higher than the sintering starting temperature of the conductive metal powder, and heating the same.

Abstract: Capacitors are provided comprising a first plate, a second plate spaced from the first plate and a dielectric between the first and second plates. In certain embodiments the plates are arranged generally opposite each other and each is shaped in a periodically repeating pattern that is spatially out of phase with the other so that misregistration of the plates is compensated. In certain embodiments, a floating equipotential conductor is positioned between the plates and has a larger dimension than a corresponding dimension of the plates so that misregistration of the plates is compensated. Methods of manufacturing the capacitors are also provided.

Abstract: A method for manufacturing a multilayer ceramic electronic component includes a first substep of depositing precipitates primarily made of a specific metal on an end of each of internal electrodes exposed at a predetermined surface of a laminate and growing the precipitates to coalesce into a continuous plated sublayer, and a second substep of heat-treating the laminate including the plated sublayer at a temperature of at least about 800° C., wherein a plated layer including a plurality of plated sublayers is formed by continuously performing at least two cycles of the first substep and the second substep.

Abstract: A capacitor device may include a first electrode, a second electrode, a third electrode, a first dielectric layer, and a second dielectric layer. The first electrode may be coupled with a first terminal of the capacitor device. The second electrode is under the first electrode and may be coupled with a second terminal of the capacitor device. The second electrode may be electrically isolated from the first electrode. The third electrode is under the first electrode and the second electrode and may be electrically isolated from the second electrode and electrically coupled with the first electrode. The first dielectric layer has a first dielectric constant and may be sandwiched between the first electrode and the second electrode. The second dielectric layer may have a second dielectric constant and may be sandwiched between the second electrode and the third electrode. In one embodiment, the second dielectric constant is at least five times larger than the first dielectric constant.

Abstract: A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.

Abstract: A multilayer electronic component includes a ceramic body including ceramic layers that are laminated to one another and internal conductors having exposed portions at side surfaces of the ceramic body. Substantially linear connection portions extend in the lamination direction of the ceramic layers so as to connect the exposed portions to one another. External terminal electrodes cover the exposed portions of the internal conductors and the connection portions and include base plating films directly disposed on the side surfaces by plating. The connection portions are formed by polishing the side surfaces in which the internal conductors are exposed using, for example, a brush so as to elongate the exposed portions of the internal conductors.

Abstract: This invention relates to a capacitor electrode which includes porous layers made of a fiber and/or a whisker containing crystal tungsten oxides. The tungsten oxide fiber and/or whisker contain W18O49 as a main ingredient. The tungsten oxide fiber and/or whisker are made on a substrate. When manufacturing the capacitor electrode the substrate or its precursor is heated in vacuo or in an inactive containing a minute amount of oxygen, thereby completing the fiber and/or whisker.

Abstract: A multilayer capacitor comprises a capacitor element body; a first signal terminal electrode, a second signal terminal electrode, and a ground terminal electrode which are arranged on an outer surface of the capacitor element body; and a ground internal electrode and first to third signal internal electrodes which are arranged within the capacitor element body. The ground internal electrode is connected to the ground terminal electrode. The first signal internal electrode is connected to the first signal terminal electrode and opposes the ground internal electrode so as to construct a first capacitor. The second signal internal electrode is connected to the first signal terminal electrode and opposes the ground internal electrode so as to construct a second capacitor. The third signal internal electrode is connected to the second signal terminal electrode and opposes the ground internal electrode so as to construct a third capacitor.

Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: A monolithic ceramic electronic component includes a dummy electrode having a dummy body portion and an internal electrode having an extended portion, in which the conductor density of the dummy body portion is less than the conductor density of the extended portion of an internal electrode. With this configuration, the fixing strength of an external terminal electrode to a ceramic element assembly is improved, and undesirable deformation caused by a dummy conductor provided in a monolithic ceramic electronic component is prevented.

Abstract: A method of producing a multilayer capacitor has steps of preparing a plurality of first and second ceramic green sheets, a step of laminating the plurality of first and second ceramic green sheets, and a step of cutting a ceramic green sheet laminate body along predetermined intended cutting lines to obtain laminate chips of individual multilayer capacitor units. When preparing the first ceramic green sheets, first and second internal electrode patterns are formed so that the first and second internal electrode patterns are alternately arranged in a perpendicular configuration, with the first and second internal electrode patterns being continuous across intended cutting lines.

Abstract: The invention relates to a multilayer ceramic capacitor having dielectric layers and internal electrode layers disposed alternately. The dielectric layers include a dielectric ceramic containing barium titanate as a main component, and also calcium, magnesium, vanadium, manganese, and a rare-earth element. Crystals constituting the dielectric ceramic are constituted by grains containing barium titanate as their main component and containing calcium in a concentration of 0.2 atomic % or less or containing the calcium in a concentration of 0.4 atomic % or more. The crystals grains are also distinct in their relative distributions of magnesium and rare-earth elements between the center of the grain and the surface of the grain. Finally, the relative areas of the two kinds of crystals observed in the plane of a polished surface of the dielectric ceramic are described by a ratio b/(a+b), which is 0.5 to 0.8.

Abstract: Provided are a high voltage multi-layer ceramic capacitor (MLCC) that may enable a surface mounting, and may form a guide electrode between inner electrodes or between sealing electrodes to thereby prevent a decrease in an inner voltage, caused by a parasitic capacitance, and a director current (DC)-link capacitor module using the MLCC.

Abstract: In an electronic component, a first capacitor conductor includes a first exposed portion exposed between insulating layers at a surface of a laminate including a first shorter side and two longer sides. A second capacitor conductor includes a second exposed portion exposed between the insulating layers at a surface of the laminate including a second shorter side and the two longer sides. First and second external electrodes are arranged on the laminate so as to cover the first and the second exposed portions, respectively. A first width of the first capacitor conductor in a region located between the second shorter side and a first straight line obtained by connecting two edges of the second external electrode is greater than a width of the first capacitor conductor in a region located between the first straight line and a straight line obtained by connecting two edges of the first external electrode.

Abstract: Provided is a MLCC module used as a direct current (DC) link capacitor that is included in an inverter of a hybrid vehicle.

Abstract: There are provided a multilayer chip capacitor and a circuit board device. The multilayer chip capacitor includes a capacitor body including a plurality of dielectric layers that are stacked, first and second outer electrodes formed on an outer surface of the capacitor body and having opposite polarity, first and second inner electrodes opposing each other, interleaved with the dielectric layers in the capacitor body, and each including an electrode plate forming capacitance and a lead extending from the electrode plate, the lead of the first inner electrode and the lead of the second electrode being respectively connected to the first and second outer electrodes, and third inner electrodes interposed between the first and second inner electrodes. At least one of the third inner electrodes adjacent to the first inner electrode includes a conductive pattern having the same shape as the lead of the first inner electrode and is connected to the first outer electrode.

Abstract: There are provided a multilayer ceramic capacitor, a printed circuit board including the same, a method of manufacturing the multilayer ceramic capacitor, and a method of manufacturing the printed circuit board. The method of manufacturing a multilayer ceramic capacitor includes: preparing a capacitor body on which external electrode material layers are formed, dry polishing the capacitor body such that surfaces of the external electrode material layers are smooth and compact, and forming plating layers on the surfaces of the external electrode material layers in order to form external electrodes. Therefore, the surface smoothness, compactness, and uniformity of an external electrode plating layer can be improved.

Abstract: The invention relates to a surface mount type electronic component mounted on a printed circuit board or hybrid IC (HIC) and a method of manufacturing the same and provides an electronic component which can be formed with a small size and a low height at a low cost and a method of manufacturing the same. A common mode choke coil as the electronic component has an overall shape in the form of rectangular parallelepiped that is provided by forming an insulation layer, a coil layer (not shown) formed with a coil conductor, and external electrodes electrically connected to the coil conductor in the order listed on a silicon substrate using thin film forming techniques. The external electrodes are formed to spread on a top surface (mounting surface) of the insulation layer.

Abstract: A multilayer chip capacitor including: a capacitor body having a lamination structure where a plurality of dielectric layers are laminated and including a first capacitor part and a second capacitor part arranged according to a lamination direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, the first and third outer electrodes having the same polarity and the second and fourth outer electrodes having the same polarity opposite to that of the first outer electrode; and one or more connection conductor lines formed on an outer surface of the capacitor body and connecting the first outer electrode to the third outer electrode or connecting the second outer electrode to the fourth outer electrode.

Abstract: Disclosed are apparatus and methodology for providing controlled equivalent series resistance (ESR) decoupling capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Controlled equivalent series resistance (ESR) is provided by providing extended length tab connections to active electrode layers within the device.

Abstract: A SrTiO3-based grain boundary insulation type semiconductor ceramic contains a donor element in solid solution in crystal grains, an acceptor element at least in crystal grain boundaries, an integral width of (222) face of the crystal face of 0.500° or less, and an average powder grain size of crystal grains of 1.0 ?m or less. A semiconductor ceramic is obtained by firing this ceramic, and a monolithic semiconductor ceramic capacitor is obtained by using the semiconductor ceramic. The SrTiO3-based grain boundary insulation type semiconductor ceramic powder has a large apparent relative dielectric constant ?rAPP of 5,000 or more even when the average ceramic grain size of crystal grains is 1.0 ?m or less and which has an excellent insulating property. The monolithic semiconductor ceramic capacitor is capable of having a large capacity through reduction in thickness and multilayering.

Abstract: The formation of a resistive electrode layer as a portion of an external electrode of a monolithic ceramic capacitor by baking a resistive paste, which contains ITO, a glass frit, and an organic vehicle, to impart the function of a resistance element to the external electrode may lead to the occurrence of blisters or reduced denseness. This is modulated when the resistive paste further contains a densification promoting metal or oxide, which promotes densification of a sintered compact of the resistive paste, and a densification preventing metal oxide, which prevents the densification.

Abstract: A first internal conductor has a first portion. A second internal conductor has a lead portion and a main electrode portion. The second internal conductor is arranged in the same layer as the first internal conductor. A third internal conductor has a lead portion and a main electrode portion. The third internal conductor is arranged so as to be adjacent to the second internal conductor in a laminate direction. A fourth internal conductor has a lead portion and a main electrode portion. The fourth internal conductor is arranged so as to be adjacent to the third internal conductor in the laminate direction. When the laminate body is viewed from the laminate direction, the main electrode portion of the third internal conductor overlaps with the main electrode portions of the second and fourth internal conductors.

Abstract: Disclosed are energy conditioner structures, method of making and using them wherein the structure comprises a sequence of conductive layers including a first A layer, a G layer, and a first B layer; wherein said first A layer, said G layer, and said first B layer are each conductive, and are conductively isolated from one another in said energy conditioner structure; wherein said first A layer includes a first A layer main body and a first A layer tab, said first B layer includes a first B layer main body and a first B layer tab, and said G layer includes a G layer main body and a G layer first tab; wherein said G layer is in a plane between a plane containing said first A layer and a plane containing said first B layer; where the main body of at least one of said first A layer and said first B layer opposes a portion of said G layer main body; wherein two of said first A layer tab, said first B layer tab, and said G layer first tab are on a first side of said energy conditioner, and the remaining one of sai

Abstract: A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes.

Abstract: A feedthrough capacitor has: a capacitor element body of a substantially rectangular parallelepiped shape in which a plurality of insulator layers are laminated together; a signal internal electrode arranged in the capacitor element body; a ground internal electrode arranged in the capacitor element body and opposed to the signal internal electrode; signal terminal electrodes connected to the signal internal electrode; and a ground terminal electrode connected to the ground internal electrode. The signal terminal electrodes are provided on first and second end faces, respectively, in a longitudinal direction of the capacitor element body. The ground terminal electrode is provided on at least one side face out of first to fourth side faces extending along the longitudinal direction of the capacitor element body. Furthermore, the ground terminal electrode is located nearer at least one end face out of the first end face and the second end face.

Abstract: Circuitry includes a voltage-controlled switch having a transmitter input, a receiver input, and an output that connects to one of the transmitter input and the receiver input. Passive components form a low-pass filter that is electrically connected to the transmitter input. The passive components are part of a multilayer ceramic passive module that includes a base body made of superimposed dielectric layers and electrically conductive layers. The voltage-controlled switch is on an upper portion or a lower portion of the base body.

Abstract: An MOM capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one oxide layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a plurality of ceramic layers, the ceramic body having a first main surface and a second main surface and a plurality of side surfaces that connect the first main surface to the second main surface, an internal conductor including nickel, the internal conductor being disposed in the ceramic body and having an exposed portion exposed at least one of the side surfaces, and an external terminal electrode disposed on at least one of the side surfaces of the ceramic body, the external terminal electrode being electrically connected to the internal conductor. The external terminal electrode includes a first conductive layer including a Sn—Cu—Ni intermetallic compound, the first conductive layer covering the exposed portion of the internal conductor at least one of the side surfaces of the ceramic body.

Abstract: A collective component has a first region that intersects a conductive paste film for external terminal electrodes in a break line in which break leading holes are arranged and a second region that does not intersect a conductive paste film for external terminal electrodes in the break line. The first break leading holes are formed in the first region so as not to reach the second region. The second break leading holes are formed only in the second region or from the second region to a portion of the first region. The pitch of the first break leading holes is wider than the pitch of the second break leading holes.

Abstract: The present invention relates to a multi-layer ceramic capacitor printed simultaneously with internal electrode and external electrode by employing an inkjet printing. A method for manufacturing the multi-layer ceramic capacitor comprising first external electrode, dielectric, internal electrode and second external electrode prints simultaneously the first external electrode; the internal electrode which is connected with the first external electrode and formed at an invaginated portion of the dielectric invaginated to allow one side to be opened at one portion; and the second external electrode which is formed integrally with the internal electrode by employing an inkjet printing. According to the present invention, a method for manufacturing the multi-layer ceramic capacitor resolves contact problems by printing integrally the internal electrode and the external electrode and reduces the manufacturing process.

Abstract: A multilayer capacitor includes a capacitor body having rectangular first and second main faces opposing each other, first and second end faces extending in a shorter side direction of the first and second main faces so as to connect the first and second main faces to each other, and first and second side faces extending in a longer side direction of the first and second main faces so as to connect the first and second main faces to each other. First and second terminal electrodes are arranged on the first and second side faces of the capacitor body, respectively. A first inner electrode connected to the first terminal electrode, a second inner electrode connected to the second terminal electrode, and first and second intermediate electrodes connected to none of the first and second terminal electrodes are arranged within the capacitor body.