Abstract: A method of manufacturing a thin film capacitor, having: a base electrode; dielectric layers consecutively deposited on the base electrode; an internal electrode deposited between the dielectric layers; an upper electrode deposited opposite the base electrode with the dielectric layers and the internal electrode being interposed therebetween; and a cover layer deposited on the upper electrode, has depositing an upper electrode layer which is to be the upper electrode, and a cover film which is to be the cover layer on the unsintered dielectric film which is to be the dielectric layer, to fabricate a lamination component, and sintering the lamination component.

Abstract: In a multilayer capacitor 1, burned layers 17A, 17B are formed so as to cover all of lead conductors 12A, 12B drawn from inner electrodes 6A, 6B to end faces of a multilayer body 2. This can keep a plating solution from infiltrating onto the inner electrodes 6A, 6B when forming plating layers 18A, 18B and prevent insulation failures from occurring. Since the burned layers 17A, 17B cover a part of dummy electrodes 13C, 13F, 13G, 13H, the area of the burned layers 17A, 17B can be suppressed. This can inhibit excessive stresses from occurring in the burned layers 17A, 17B and thus can prevent cracks from being generated by stresses in the burned layers 17A, 17B.

Abstract: A multi-layered ceramic capacitor with at least one chip and with first base metal plates in a parallel spaced apart relationship and second base metal plates in a parallel spaced apart relationship wherein the first plates and second plates are interleaved. A dielectric is between the first base metal plates and said second base metal plates and the dielectric has a first coefficient of thermal expansion. A first termination is in electrical contact with the first plates and a second termination is in electrical contact with the second plates. Lead frames are attached to, and in electrical contact with, the terminations wherein the lead frames have a second coefficient of thermal expansion and the second coefficient of thermal expansion is higher than said first coefficient of thermal expansion. The lead frame is a non-ferrous material.

Abstract: A feed-through capacitor is constructed in a printed wiring board using alternating layers of metal capacitive layers and plastic dielectric layers of the printed wiring board. The large number of layers, the avoidance of ceramic layers and the flexible geometry of this device allow it to be used in many applications, particularly in those involving high power high current. Also, because it utilizes a printed wiring board, the capacitor can be made in numerous sizes and shapes.

Abstract: A plurality of ceramic green sheets having printed strip inner electrodes patterns, each including a thick portion at a width-direction center and thin portions at respective width-direction sides of the thick portion, are laminated so that the thin portions overlap and the thick portions do not overlap to form an unfired mother laminated body. This unfired mother laminated body is cut along predetermined cut lines that are vertical to each other to obtain a plurality of unfired ceramic element assemblies. By applying ceramic paste to cover exposed portions of inner electrode patterns exposed to lateral surfaces, side gap areas are formed between a first inner electrode pattern and first and second lateral surfaces of the unfired ceramic element assembly and between a second inner electrode pattern and the first and second lateral surfaces.

Abstract: In a method for manufacturing a multilayer electronic component, after a plating layer for forming an external electrode is formed on an end surface of a laminate, conditions for heat-treating the laminate are set such that interdiffusion layers have ends which face internal electrodes and which are spaced from the end surface of the laminate at a distance of about 0.5 ?m to about 1.9 ?m.

Abstract: A multilayer chip capacitor includes a capacitor body including a first capacitor part and a second capacitor part, first and second external electrodes respectively formed on first and second longer side faces of the capacitor body, and third and fourth external electrodes respectively formed on first and second shorter side faces of the capacitor body. The first capacitor part includes first and second internal electrodes of opposite polarity, and the second capacitor part includes third and fourth internal electrodes of opposite polarity. The first to fourth internal electrodes each have one lead. The first to fourth external electrodes are respectively connected to the leads of the first to fourth internal electrodes. A series resonance frequency of the first capacitor part is different from that of the second capacitor part. Equivalent series resistance (ESR1) of the first capacitor part and the equivalent series resistance (ESR2) of the second capacitor part satisfy ERS1?20 m? and 0.7(ESR1)?ESR2?1.

Abstract: In a capacitor body, a single second capacitor unit is interposed between two first capacitor units. The width direction dimension of each of extended portions of first and second internal electrodes included in the first capacitor unit is larger than the width direction dimension of each of extended portions of third and fourth internal electrodes included in the second capacitor unit. The area of each of the respective portions of a first opposed portion of the first internal electrode and a second opposed portion of the second internal electrode, the respective portions being opposed to each other, is smaller than the area of each of respective portions of opposed portions of the third and fourth internal electrodes, the respective portions being opposed to each other. Thus, a multilayer capacitor has a characteristic that is a combination of a low-ESL characteristic of the first capacitor unit and a high-ESR characteristic of the second capacitor.

Abstract: A multilayer capacitor which can prevent chattering noises from occurring and improve the packaging density and packaging yield, and a method of manufacturing a multilayer capacitor are provided. Even when an electrostrictive vibration is generated in this multilayer capacitor upon voltage application, a joint surface of a metal terminal can flex, so as to mitigate the electrostrictive vibration, thereby preventing chattering noises from occurring. The joint surface is formed with a cutout and thus can fully secure its flexibility. In this multilayer capacitor, a step formed by a terminal connecting surface, a substrate connecting surface, and the joint surface is positioned within an area overlapping a capacitor element body as seen in the laminating direction of dielectric layers. Therefore, solder fillets do not protrude out of the capacitor element body, whereby the packaging density on a mounting substrate K can be improved.

Abstract: A first inner electrode has a first main electrode, a first lead conductor, a first coupling conductor, and a second lead conductor. A second inner electrode has a second main electrode, a third lead conductor, and a second coupling conductor. A third inner electrode has a third main electrode, and a fourth lead conductor. The third inner electrode is connected to only a first connection conductor. In the extending direction of the first and third lead conductors, the first and second coupling conductors have a length shorter than the lengths of the first and third lead conductors and of the first and second main electrodes, respectively. The second inner electrode is adjacent to at least one of the first and third inner electrodes so as to sandwich the insulating layer.

Abstract: A stacked capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit has a positive electrode that has a positive pin extended outwards therefrom. The positive pins of the capacitor units are divided into a plurality of positive pin units that are separated from each other, and the positive pins of each positive pin unit are electrically stacked onto each other. Each capacitor unit has a negative electrode, and the negative electrodes of the capacitor units are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins of the capacitor units and a negative guiding substrate electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.

Abstract: A multi-terminal monolithic ceramic capacitor arranged to reduce an equivalent series inductance and having an array structure is provided. A first same-polarity-connection conductor and a second same-polarity-connection conductor are provided inside a capacitor body so as to extend over at least two capacitors. The first same-polarity-connection conductor is electrically connected to a plurality of first external terminal electrodes, and the second same-polarity-connection conductor is connected to a plurality of second external terminal electrodes. In the monolithic ceramic capacitor which is mounted on a wiring substrate, the overall capacitance can be maintained even if an accident, such as cracking of a solder joint, occurs in one of the external terminal electrodes.

Abstract: Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.

Abstract: A chip element in the form of a substantially rectangular parallelepiped having end surfaces and side surfaces is formed (step of forming chip element). An electrically conductive green sheet is formed (step of forming electrically conductive green sheet). An electrically conductive paste is applied to the end surfaces of the chip element (step of application electrically conductive paste). A chip element is formed in which the electrically conductive green sheet is attached to the end surface via the electrically conductive paste applied to the end surface of the chip element (step of attaching electrically conductive sheet). In the step of attaching, the end surface of the electrically conductive green sheet on the side of the side surfaces is positioned on the outside of the side surfaces, and the electrically conductive paste applied to the end surface is pressed out into a space between the electrically conductive green sheet and ridge portions.

Abstract: A capacitor device mountable on a plane of a substrate includes an electrically conductive bottom plate adapted to be mounted substantially parallel to, and in electrical contact at the plane of the substrate and a first multilayer capacitor having substantially parallel first and second electrode plates oriented substantially perpendicular to the bottom plate with the first electrode plates being electrically connected to the bottom plate. An electrically conductive top lead frame overlaps with, and is electrically isolated from, the bottom plate. The top lead frame electrically connected to the second electrode plates and adapted to be electrically connected at the plane of the substrate. The bottom lead frame may have a corrugated shape, where the corrugated shape provides compliance between the first multilayer capacitor and the substrate. A portion of the top lead frame may contact at least a portion of a side of the first multilayer capacitor.

Abstract: A multilayer capacitive divider having first and second main electrodes on the same level to apply an input voltage, and a common electrode on another level to supply an attenuated voltage, at least a first auxiliary electrode on yet another level, the electrodes arranged to form capacitive units, with the auxiliary electrode extending towards a side of the device towards which the second main electrode is arranged for connecting the auxiliary electrode to the second main electrode by a linear conductor. One such device also includes a voltage sensor, a trip device module and an electrical protection apparatus.

Abstract: A laminated ceramic capacitor which has a dielectric ceramic with a high dielectric constant and has excellent reliability against changes in temperature and mechanical shocks, even when dielectric ceramic layers are reduced in thickness employs a dielectric ceramic containing (Ba1-xCax)yTiO3 (where 0.045?x?0.15 and 0.98?y?1.05) as its main constituent and containing Re2O3 (where Re is at least one of Gd, Dy, Ho, Yb, and Y), MgO, MnO, V2O5, and SiO2 as accessory constituents, which is represented by the general formula: 100(Ba1-xCax)yTiO3+aRe2O3+bMgO+cMnO+dV2O5+eSiO2, and satisfies each of the following conditions: 0.65?a?1.5; 0.98?y?1.05; 0.15?b?2.0; 0.4?c?1.5; 0.02?d?0.25; and 0.2?e?3.0.

Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).

Abstract: In a ceramic electronic component having a thin structure, the occurrence of cracks due to stress applied when the ceramic component is being mounted or in a mounted state are prevented. Each of first and second external terminal electrodes has a substantially rectangular region on a principal surface of a ceramic element body, the principal surface being directed to the mounting surface side. An end of the first external terminal electrode, which is arranged in contact with a gap region, and an end of the second external terminal electrode, which is positioned in contact with the gap region, each preferably have a concave-convex shape on the principal surface.

Abstract: A method is provided to mount a capacitor array onto a circuit board formed with first leads for connecting power lines to each other and a second lead for grounding. The method uses one of a first connection method of connecting such that first and second capacitor sections are parallel to each other, third capacitor section is in series with the parallel first and second capacitor sections; a second connection method of connecting such that the first to third capacitor sections are in series in sequence; and a third connection method of connecting such that the first and second capacitor sections are in series with each other without using the third capacitor section.

Abstract: The capacitor material of the present invention is comprised by laminating a titanium dioxide layer and a titanate compound layer having perovskite crystals.

Abstract: In a laminated ceramic electronic component in which, by directly carrying out a plating process on an outer surface of a component main body, an external electrode is formed thereon, an attempt is made to improve the adhesion strength between a plated film forming the external electrode and the component main body. A brazing material containing Ti is applied to at least one portion of a surface on which external electrodes of a component main body is formed, and by baking this brazing material, a metal layer containing Ti is formed. Moreover, the external electrodes are formed by a plating process so as to coat at least the metal layer, and a heating process is then carried out so as to cause counter diffusion between the metal layer and the plated film that is to form the external electrodes.

Abstract: There are provided a ceramic electronic component and a method for producing the ceramic electronic component, where a ground electrode layer can be directly coated with lead-free solder without lowering reliabilities. Terminal electrode 3 is provided with a ground electrode layer 21 of Cu having been formed by firing, a solder layer 22 formed of a lead-free solder based on five elements of Sn—Ag—Cu—Ni—Ge, and a diffusion layer 23 having been formed by the diffusion of Ni between the ground electrode layer 21 and the solder layer 22. Because the diffusion layer 23 of Ni is formed between the ground electrode layer 21 and the solder layer 22, the diffusion layer 23, which functions as a barrier layer, suppresses the solder leach of Cu from the ground electrode layer 21. The diffusion layer 23 of Ni can also suppress the growth of fragile intermetallic compounds of Sn—Cu. Therefore, a decrease in the bonding strength between the ground electrode layer 21 and the solder layer 22 can be prevented.

Abstract: A multilayer ceramic capacitor is provided. In the multilayer ceramic capacitor, a plurality of first and second inner electrodes are formed inside a ceramic sintered body. Ends of the first and second inner electrodes are alternately exposed to both ends of the ceramic sintered body. First and second outer electrodes are formed on both ends of the ceramic sintered body and connected to the first and second inner electrodes. The first and second outer electrodes include a first region having a porosity in the range of 1% to 10%, and a second region having a porosity less than that of the first region.

Abstract: There is provided an electronic apparatus capable of ESL reduction. The electronic apparatus includes a capacitor and a mounting board. The capacitor includes a multilayer body, an internal electrode, and a terminal electrode. The mounting board has a connection pad formed on its upper surface and has a through conductor formed inside thereof that is connected to the connection pad. The capacitor is mounted on the mounting board by connecting the terminal electrode to the connection pad. The internal electrode has an end portion exposed at an area ranging from an end face to a middle portion of a lateral face in the multilayer body. In a planar view, the through conductor is located immediately below a part of the end portion of the internal electrode exposed at the lateral face of the multilayer body, the part lying furthermost from the end face.

Abstract: A multilayer chip capacitor includes a capacitor body including a stack of a plurality of dielectric layers and having first and second side faces and first and second end faces, a plurality of external electrodes of opposite polarity alternated on each of the first and second side faces, and a plurality of internal electrodes each including one or two leads extending to an outer face of the capacitor body and respectively connected to the external electrodes. A horizontal distance between leads of the internal electrodes of opposite polarity adjacent to each other in a stack direction is longer than a pitch between the external electrodes of opposite polarity adjacent to each other on the same side face of the capacitor body.

Abstract: A multilayer capacitor array 1 comprises a capacitor element body 2 having first, second, third, and fourth inner electrodes 13 to 16, and first to fourth terminal electrodes 3 to 6 disposed on the outer surface of the capacitor element body 2 and respectively connected to the inner electrodes 13 to 16. The first and second inner electrodes 13, 14 form a first capacitor section C1, while the third and fourth inner electrodes 15, 16 form a second capacitor section C2. The multilayer capacitor array 1 is mounted to a circuit board such that the first and third terminal electrodes 3, 5 are connected to first leads 22, 23, while the second and fourth terminal electrodes 4, 6 are connected to a second lead 24.

Abstract: In a ceramic capacitor, first and second electrode terminals each include a bonded-to-substrate portion, a first bonded-to-electrode portion bonded to a first edge of one of first and second external electrodes, a second bonded-to-electrode portion bonded to a second edge of the one of first and second external electrodes and disposed at a distance from the first bonded-to-electrode portion in the first directions, and a connecting portion connecting the first and second bonded-to-electrode portions and the bonded-to-substrate portion. W1/W0 is about 0.3 or more, and h/L is about 0.1 or more.

Abstract: In a laminated ceramic electronic component, external terminal electrodes include plating films directly covering exposed portions of internal electrodes on end surfaces of a ceramic element assembly. On the boundaries between the end surfaces and principal surfaces of the ceramic element assembly, substantially rounded corners are provided, and the plating films are arranged such that the ends of the plating films stop at the corners and do not project from the principal surfaces.

Abstract: A container for a refrigerated fluid having an external container and an internal container between which an evacuated intermediate space is situated, which contains a superinsulator formed by several, separated layers of foil provided with a metal layer, is used as a storing device for electric energy. The foils act as foil capacitors and are electrically contacted so that an electric voltage can be applied to corresponding electric terminals on the exterior side of the container. In the container, a metal layer can be provided on both surfaces of the foil(s), and the foil(s) may consist of a material with a semiconductor characteristic. The foil capacitors are electrically connectable in series or parallel, and the electrical contacting of the foil metal surfaces can take place via a suspension structure of the internal container in the external container.

Abstract: A multilayer ceramic electronic component includes dummy conductor patterns on a ceramic green sheet laminated in an earlier stage of the lamination and sheet-by-sheet crimping process that have widths that are less than the widths of dummy conductor patterns on a ceramic green sheet laminated in a later stage of the lamination and sheet-by-sheet crimping process.

Abstract: A circuit for balancing a sub-stack voltage in a stack of ultracapacitors includes a pair of electrical leads that are connectable across a first sub-stack of one or more ultracapacitors, wherein a stack includes N sub-stacks of ultracapacitors coupled to an electrical bus, a discharge device switchably connectable with the pair of electrical leads, the discharge device configured to discharge the sub-stack of ultracapacitors, a voltage sensing circuit coupled to the electrical bus and configured to sense and output a voltage of the stack of ultracapacitors after the first sub-stack of one or more ultracapacitors has been discharged to a given threshold, and a voltage amplifier coupled to the output of the voltage sensing circuit and coupled to the pair of electrical leads, the voltage amplifier configured to provide a re-charge voltage to the first sub-stack of one or more ultracapacitors.

Abstract: The present invention is directed to a microfabricated RF capacitor. The capacitor includes two signal wirebond pads configured for being connected to an electrical current source. The capacitor further includes two backbone structures which are connected to the wirebond pads and receive electrical current from the electrical current source via the wirebond pads, each backbone structure including a first backbone portion and a second backbone portion. The capacitor further includes a plurality of protrusions which are connected to the backbone portions of the backbone structures. The protrusions are spaced apart from each other and parallel to each other. Further, the protrusions are configured for distributing current received by the backbone structures and for promoting structural stability of the capacitor. The capacitor further includes a ground wall structure which may be configured for receiving ground current from a ground current source.

Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Abstract: A multilayer chip capacitor includes a capacitor body including first and second longer side surfaces facing each other and first and second shorter side surfaces facing each other, first and second external electrodes respectively disposed at the first and second longer side surfaces, one or more first internal electrode pairs each including first and second internal electrodes, and one or more second internal electrode pairs each including third and fourth internal electrodes. The first to fourth internal electrodes each have one lead and are sequentially disposed in a stacked direction. The first to fourth internal electrodes have first to fourth leads respectively extending to first to fourth corners or portions adjacent thereto, and alternately connected with the first and second external electrodes. The first internal electrode pair and the second internal electrode pair cause a current to diagonally flow in opposite directions with respect to a long side direction.

Abstract: A first inner electrode is integrally provided with a first terminal connection part connected to a first terminal electrode and a first linking connection part connected to a first linking electrode. A second inner electrode is integrally provided with a second terminal connection part connected to a second terminal electrode and a second linking connection part connected to a second linking electrode. A third inner electrode is integrally provided with a third linking connection part connected to the first linking electrode. A fourth inner electrode is integrally provided with a fourth linking connection part connected to the second linking electrode. The third inner electrode is adjacent to the first and fourth inner electrodes in a laminating direction of the plurality of dielectric layers. The first and fourth inner electrodes overlap the third inner electrode as seen in the laminating direction of the plurality of dielectric layers.

Abstract: A multilayer electronic component includes a laminate including insulating layers that are laminated to each other and internal electrodes provided along interfaces between the insulating layers, edges of the internal electrodes being exposed at a predetermined surface of the laminate and an external electrode provided on the predetermined surface. The external electrode includes a plated film which is directly provided on the predetermined surface of the laminate so as to electrically connect edges of the internal electrodes exposed at the predetermined surface of the laminate, and at a boundary portion between each of the internal electrodes and the plated film, a counter diffusion layer is provided, in which a metal component in the plated film and a metal component in the internal electrodes are both detectable, and extend to both sides of the internal electrodes and the plated film, and, at a side of the internal electrodes.

Abstract: There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.

Abstract: A highly reliable electronic device that prevents entry of a plating solution via an external electrode and entry of moisture of external environment inside thereof, and generates no soldering defects or solder popping defects which are caused by precipitation of a glass component on a surface of the external electrode. The electrode structure of the electronic device is formed of Cu-baked electrode layers primarily composed of Cu, Cu plating layers formed on the Cu-baked electrode layers and which are processed by a recrystallization treatment, and upper-side plating layers formed on the Cu plating layers. After the Cu plating layers are formed, a heat treatment is performed at a temperature in the range of a temperature at which the Cu plating layers are recrystallized to a temperature at which glass contained in a conductive paste is not softened, so that the Cu plating layers are recrystallized.

Abstract: A monolithic ceramic capacitor includes dielectric ceramic layers having a thickness of less than 1 ?m. When this thickness is t and the crystal grains of a dielectric ceramic of the layers have a mean diameter of r, a mean number N of grain boundaries satisfies 0<N?2 where N=t/r?1. The dielectric ceramic contains, as a main component, a perovskite type compound ABO3 (where A is Ba or Ba and at least one of Ca and Sr, B is Ti or Ti and at least one of Zr and Hf), and further contains Mn and V as auxiliary components. On the basis of 100 molar parts of the main component, the content of Mn is 0.05 to 0.75 molar parts, the content of V is 0.05 to 0.75 molar parts, and the total content of Mn and V is 0.10 to 0.80 molar parts.

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: A ceramic electronic component has a chip element body having a conductor arranged inside, external electrodes, and a discrimination layer. The chip element body has first and second end faces facing each other, first and second side faces being perpendicular to the first and second end faces and facing each other, and third and fourth side faces being perpendicular to the first and second end faces and to the first and second side faces and facing each other. The external electrodes are formed on the first and second end faces, respectively, of the chip element body. The discrimination layer is provided on at least one side face out of the first side face and the second side face in the chip element body. The chip element body is comprised of a first ceramic. The discrimination layer is comprised of a second ceramic different from the first ceramic and has a color different from that of the third and fourth side faces.

Abstract: There is provided a ceramic electronic component including a ceramic sintered body, internal conductive layers, and external electrodes. Each of the external electrodes includes a first electrode layer, a conductive resin layer covering the first electrode layer, and a second electrode layer covering the conductive resin layer and having an extension length greater than the length of the first electrode layer extending from one of the side surfaces of the ceramic sintered body to the portions of the top and bottom surfaces thereof. The distance from the top or bottom surface of the ceramic sintered body to the closest layer of the internal conductive layers is greater than or equal to the length of the first electrode layer extending from one of the side surfaces of the ceramic sintered body to the portions of the top and bottom surfaces thereof.

Abstract: Disclosed is a thermosetting conductive paste which is advantageous in that an external electrode for multilayer ceramic electronic part formed using the paste exhibits excellent bonding properties with an internal electrode and is suitable for mounting on a substrate or plating, achieving excellent electric properties (electrostatic capacity, tan ?. A thermosetting conductive paste comprising: (A) metal powder having a melting point of 700° C. or higher; (B) metal powder having a melting point of higher than 300 to lower than 700° C.; and (C) a thermosetting resin.

Abstract: There is provided a dielectric ceramic composition including a base powder expressed by a composition formula of Bam(Ti1-xZrx)O3, where 0.995?m?1.010 and 0<x?0.10, and first to fifth accessory components, and a multilayer ceramic capacitor having the same. The multilayer ceramic capacitor having the dielectric ceramic composition has a high dielectric constant and superior high-temperature reliability.

Abstract: A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.

Abstract: A laminate is prepared in which adjacent internal electrodes are electrically insulated from each other at an end surface at which the internal electrodes are exposed, a space between the adjacent internal electrodes, which is measured in the thickness direction of insulating layers, is about 10 ?m or less, and a withdrawn distance of the adjacent internal electrodes from the end surface is about 1 ?m or less. In an electroplating step, electroplating deposits deposited on the ends of the adjacent internal electrodes are grown so as to be connected to each other.

Abstract: A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.

Abstract: A laminated electronic component is configured to include substrate plating films disposed on outer surfaces of an electronic component main body through direct plating such that external terminal electrodes are connected to exposed portions of internal conductors (internal electrodes), and the average particle diameter of metal particles defining the substrate plating film is at least about 1.0 ?m. The external terminal electrode includes at least one layer of an upper plating film disposed on the substrate plating film. The metal particles defining the substrate plating film are Cu particles.

Abstract: A ceramic electronic component has a ceramic element assembly, external electrodes, and metal terminals. The external electrodes are arranged on the surface of the ceramic element assembly. The external electrodes contain a sintered metal. The metal terminals are electrically connected to the external electrodes, respectively. The external electrode and the metal terminal are directly diffusion-bonded by diffusion of metal in the metal terminals into the external electrodes. The above arrangement provides a ceramic electronic component having highly reliable metal particle bonding and a method for manufacturing the same.