Abstract: A capacitor forming unit includes a dielectric plate, a first conductor film formed on a plate upper surface region other than front and rear end portions, a first insulator film formed on the upper surface front end portion, a second insulator film formed on the upper surface rear end portion, a second conductor film formed on a plate lower surface region other than front and rear end portion, a third insulator film formed on the front end portion lower surface, and a fourth insulator film formed on the lower surface rear end portion. One or more first electrode rods are disposed in through holes, and electrically connected to the first conductor film and electrically insulated from the second conductor film. One or more second electrode rods are disposed in other through holes, and electrically connected to the second conductor film and electrically insulated from the first conductor film.

Abstract: A capacitor includes a capacitor body made of a dielectric, a first internal electrode, a second internal electrode, a first signal terminal, a second signal terminal, and a grounding terminal. The first and second signal terminals are connected to the first internal electrode. The grounding terminal is disposed on the outer surface of the capacitor body so as to be connected to the second internal electrode. The grounding terminal is connected to the ground potential. The grounding terminal includes a plating layer which is disposed on the capacitor body and which is connected to the second internal electrode.

Abstract: A ceramic electronic component includes a first dielectric layer, a second dielectric layer, and an intermediate layer. The first dielectric layer is a layer containing BaO, Nd2O3, and TiO2, the second dielectric layer is a layer containing a different material from the material of the first dielectric layer, and the intermediate layer is a layer formed between the first dielectric layer and the second dielectric layer and containing main components that are not contained in the first dielectric layer and the second dielectric layer in common as the main components.

Abstract: A thin-film capacitor that is less prone to generation of internal cracking or peeling is provided. In a thin-film capacitor according to the present embodiment, because through holes H are formed in internal electrodes containing Ni as a principal component in a lamination direction, a surface area of at least some of the through holes H is in the range of 0.19 ?m2 to 7.0 ?m2, and a ratio of a surface area of the through holes H to a surface area of an entire main surface of the internal electrodes is in the range of 0.05% to 5%, peeling or cracking is suppressed from occurring at the boundaries between the internal electrodes and dielectric layers, and as a result, the yield is enhanced.

Abstract: In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

Abstract: A composite dielectric material having a plurality of particle cores, each surrounded by polymer strands that are chemically bonded to the surface of the particle core. Each polymer strand includes a linker, through which the polymer strand is attached to the surface, an interfacial core-shielding (ICS) group bound to the linker, and a polymer molecule bound to the ICS group. The ICS groups are designed to inhibit electrical breakdown of the composite dielectric material by (i) deflecting or scattering free electrons away from the particle cores and/or (ii) capturing free electrons by being transformed into relatively stable radical anions. Representative examples of the particle core material, linker, ICS group, and polymer molecule are titanium dioxide, a phosphonate group, a halogenated aromatic ring, and a polystyrene molecule, respectively.

Abstract: In a ceramic capacitor according to the present invention, the electrode strips of an internal electrode and the dielectric strips of a ceramic dielectric member are arranged perpendicularly to the surface of a substrate, and as such, the plurality of electrode strips and the plurality of dielectric strips are arranged alternately along a parallel direction relative to the substrate surface. That is, the electrode strips and the dielectric strips are multi-layered along a parallel direction relative to the substrate surface, thereby facilitating the realization of multi-layering in the ceramic capacitor by a known patterning technology.

Abstract: A power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.

Abstract: The method for adjusting a hearing device (11) to the hearing preferences of a user of the hearing device comprises a) adjusting at least one of N parameters (P1, P2), preferably with 2?N?4; b) obtaining a gain model (G), which is identical with the output of a fitting rationale (F) applied to a model audiogram (A), wherein the model audiogram depends on the N parameters and is independent of possibly existing audiogram values measured for the user; and c) using the gain model (G) or a gain model derived therefrom in said hearing device (11). Preferably, the model audiogram (A) is an approximation to an audiogram occurring in a pre-defined empirical sample of individual audiograms. The user preferably carries out the method by himself and without external equipment. A corresponding arrangement (1) is disclosed, too. A simple and efficient hearing device fitting can be achieved.

Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.

Abstract: The disclosed is a capacitor substrate structure to reduce the high leakage current and low insulation resistance issue of organic/inorganic hybrid materials with ultra-high dielectric constant. The insulation layer, disposed between two conductive layers, includes multi-layered dielectric layers. At least one of the dielectric layers has high dielectric constant, including high dielectric constant ceramic powder and conductive powder evenly dispersed in organic resin. The other dielectric layers can be organic resin, or further include high dielectric constant ceramic powder dispersed in the organic resin. The substrate has an insulation resistance of about 50K? and leakage current of below 100 ?Amp under operational voltage.

Abstract: A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.

Abstract: A structural body which includes a first dielectric layer formed on a first substrate and including first conductive particles, each surface of the first conductive particles being entirely covered with a first dielectric film; and a second dielectric layer formed on the first dielectric layer wherein a volume ratio of a dielectric in the second dielectric layer is higher than a volume ratio of a dielectric in the first dielectric layer.

Abstract: A multilayer capacitor operable to allow adjustment of its equivalent series resistance substantially independent of its equivalent series inductance is disclosed. The multilayer capacitor can be used in decoupling circuits such as power supply decoupling circuits. The equivalent series resistance of the multilayer capacitor can be increased while suppressing an increase in the equivalent series inductance resulting in improved noise grounding.

Abstract: A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.

Abstract: A clad capacitor and method of manufacture includes assembling a preform comprising a ductile, electrically conductive fiber; a ductile, electrically insulating cladding positioned on the fiber; and a ductile, electrically conductive sleeve positioned over the cladding. One or more preforms are then bundled, heated and drawn along a longitudinal axis to decrease the diameter of the ductile components of the preform and fuse the preform into a unitized strand.

Abstract: A ductile preform for making a drawn capacitor includes a plurality of electrically insulating, ductile insulator plates and a plurality of electrically conductive, ductile capacitor plates. Each insulator plate is stacked vertically on a respective capacitor plate and each capacitor plate is stacked on a corresponding insulator plate in alignment with only one edge so that other edges are not in alignment and so that each insulator plate extends beyond the other edges. One or more electrically insulating, ductile spacers are disposed in horizontal alignment with each capacitor plate along the other edges and the pattern is repeated so that alternating capacitor plates are stacked on alternating opposite edges of the insulator plates. A final insulator plate is positioned at an extremity of the preform. The preform may then be drawn to fuse the components and decrease the dimensions of the preform that are perpendicular to the direction of the draw.

Abstract: A method for manufacturing a capacitor includes the steps of: sequentially laminating, on a substrate, a lower electrode layer, a dielectric layer and an upper electrode layer; forming a patterned mask layer on the upper electrode layer; patterning at least the upper electrode layer and the ferroelectric layer using the mask layer as a mask; removing the mask layer; and conducting a plasma treatment to contact plasma with an exposed surface of the dielectric layer.

Abstract: The present invention relates to composite materials with a high dielectric constant and high dielectric strength and to methods of producing the composite materials. The composite materials have high dielectric constants at a range of high frequencies and possess robust mechanical properties and strengths, such that they may be machined to a variety of configurations. The composite materials also have high dielectric strengths for operation in high power and high energy density systems. In one embodiment, the composite material is composed of a trimodal distribution of ceramic particles, including barium titanate, barium strontium titanate (BST), or combinations thereof and a polymer binder.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: Devices for storing energy at a high density are described. The devices include a solid dielectric that is preformed to present a high exposed area onto which an electrode is formed. The dielectric material has a high dielectric constant (high relative permittivity) and a high breakdown voltage, allowing a high voltage difference between paired electrodes to effect a high stored energy density.

Abstract: The capacitor material of the present invention is comprised by laminating a titanium dioxide layer and a titanate compound layer having perovskite crystals.

Abstract: One embodiment includes an apparatus that includes an implantable device housing, a capacitor disposed in the implantable device housing, the capacitor including a dielectric comprising CaCu3Ti4O12 and BaTiO3, the dielectric insulating an anode from a cathode and pulse control electronics disposed in the implantable device housing and connected to the capacitor.

Abstract: A film capacitor is provided which has a smaller size and improved capacity while securing a sufficient withstand voltage. The film capacitor comprising a basic element 10 containing a plurality of dielectric layers and at least one vapor-deposited metal film layer 14a, 14b, where the plurality of dielectric layers consisting of a resin film layer 12 and at least one vapor-deposited polymer film layer 16a, and the at least one vapor-deposited polymer film layer 16a is formed on at least one of the resin film layer 12 and the at least one vapor-deposited metal film layer 14a, 14b.

Abstract: Methods of forming an oxide are disclosed and include contacting a ruthenium-containing material with a tantalum-containing precursor and contacting the ruthenium-containing material with a vapor that includes water and optionally molecular hydrogen (H2). Articles including a first crystalline tantalum pentoxide and a second crystalline tantalum pentoxide on at least a portion of the first crystalline tantalum pentoxide, wherein the first tantalum pentoxide has a crystallographic orientation that is different than the crystallographic orientation of the second crystalline tantalum pentoxide, are also disclosed.

Abstract: A capacitor and a method of manufacturing the capacitor are disclosed. The capacitor may include a board, a polymer layer formed on one side of the board, a circuit pattern selectively formed over the polymer layer, and a titania nanosheet corresponding with the circuit pattern. Embodiments of the invention can provide flatness in the board, and allows the copper of the board to maintain its functionality as an electrode while increasing the adhesion to the titania nanosheet. The titania nanosheet may thus be implemented on a patterned board in a desired shape, number of layers, and thickness.

Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Abstract: Provided is a dielectric element comprising a dielectric thin film formed of a layer of perovskite nanosheets. The dielectric element has the advantages of inherent properties and high-level texture and structure controllability of the perovskite nanosheets, therefore realizing both a high dielectric constant and good insulating properties in a nano-region.

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract: A capacitor includes a pair of electrically conductive layers; a plurality of substantially or nearly tubular dielectric materials disposed between the pair of electrically conductive layers formed of anodic oxide of metal; first electrodes which are filled in hollow portions of the dielectric materials and connected to one of the electrically conductive layers; and a second electrode that is filled in voids between the respective dielectric materials and connected to the other electrically conductive layer.

Abstract: A capacitor comprises a substrate layer, a first electrode layer disposed on the substrate layer, and a first dielectric layer disposed on the electrode layer. The dielectric layer comprises a polymeric material having an elongation less than or equal to about 5 percent.

Abstract: In one aspect of the present invention, a method for increasing the dielectric breakdown strength of a polymer is described. The method comprises providing the polymer and contacting a surface of the polymer in a reaction chamber with a gas plasma, under specified plasma conditions. The polymer is selected from the group consisting of a polymer having a glass transition temperature of at least about 150° C., and a polymer composite comprising at least one inorganic constituent. The contact with the gas plasma is carried out for a period of time sufficient to incorporate additional chemical functionality into a surface region of the polymer film, to provide a treated polymer. Also provided are an article and method of manufacture.

Abstract: A capacitor element includes a positive electrode body made of valve metal, a dielectric oxide layer on the positive electrode body, a solid electrolytic layer made of conductive polymer on the dielectric oxide layer, and a negative electrode layer on the solid electrolytic layer. A solid electrolytic capacitor includes the capacitor element, a package made of insulating resin covering the capacitor element, a base electrode provided at an edge surface of the package and made of non-valve metal coupled with the positive electrode body, a diffusion layer for connecting the positive electrode body to the base electrode, an external electrode on the base electrode, and an external electrode connected to the negative electrode layer. The solid electrolytic capacitor reduces the number of components and processes to reduce its cost and to have a small size, and has a small equivalent series resistance and a small equivalent series inductance.

Abstract: Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.

Abstract: A capacitor includes a multi layer structure on a ceramic or crystalline substrate. The multilayer structure includes a lower electrode, an upper electrode, and a dielectric that is tunable by a voltage applied to the electrodes. The multilayer structure is configured such that resonant oscillation modes of bulk acoustic waves can be propagated in the multilayer structure and such that the resonant frequencies of the oscillation modes are outside a first band range of between 810 and 1000 MHz, second band range of between 1700 and 2205 MHz and third band range of between 2400 and 2483.5 MHz.

Abstract: A composite dielectric material having a plurality of particle cores, each surrounded by polymer strands that are chemically bonded to the surface of the particle core. Each polymer strand includes a linker, through which the polymer strand is attached to the surface, an interfacial core-shielding (ICS) group bound to the linker, and a polymer molecule bound to the ICS group. The ICS groups are designed to inhibit electrical breakdown of the composite dielectric material by (i) deflecting or scattering free electrons away from the particle cores and/or (ii) capturing free electrons by being transformed into relatively stable radical anions. Representative examples of the particle core material, linker, ICS group, and polymer molecule are titanium dioxide, a phosphonate group, a halogenated aromatic ring, and a polystyrene molecule, respectively.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: An electrical storage unit includes a plurality of sets of layers. Each set of layers includes a first layer, a second layer, a third layer, and a fourth layer. The first layer includes a first electrode and plastic surrounding the first electrode on three sides of the first electrode within the first layer. The second layer includes a first active dielectric and plastic surrounding the first active dielectric on all four sides of the first active dielectric within the second layer. The third layer includes a second electrode and plastic surrounding the second electrode on three sides of the second electrode within the third layer. The fourth layer includes a second active dielectric and plastic surrounding the second active dielectric on all four sides of the second active dielectric within the fourth layer.

Abstract: One embodiment includes an apparatus that includes an implantable device housing, a capacitor disposed in the implantable device housing, the capacitor including a dielectric comprising CaCu3Ti4O12 and BaTiO3, the dielectric insulating an anode from a cathode and pulse control electronics disposed in the implantable device housing and connected to the capacitor.

Abstract: A laminated ceramic electronic component includes a ceramic element and two external electrodes on both end surfaces of the ceramic element. The ceramic element includes a function part and lead parts thinner than the function part. Internal electrode layers are provided facing each other via a ceramic layer therebetween in the function part. The internal electrode layers are drawn out of the function part in the lead part. The external electrode includes an extended part and a curled part. The extended part is formed from the lead part through the function part on the main face. On the main face, the part of the extended part in the lead part is lower than the part of the function part. The curled part is formed from the end face of the ceramic element through the surface of the part of the extended part in the lead part on the main face.

Abstract: A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.

Abstract: A thin-film capacitor that is less prone to generation of internal cracking or peeling is provided. In a thin-film capacitor 100 according to the present embodiment, because through holes H are formed in internal electrodes 3, 5, 7, and 9 containing Ni as a principal component in a lamination direction, a surface area of at least some of the through holes H is in the range of 0.19 ?m2 to 7.0 ?m2, and a ratio of a surface area of the through holes H to a surface area of an entire main surface of the internal electrodes 3, 5, 7, and 9 is in the range of 0.05% to 5%, peeling or cracking is suppressed from occurring at the boundaries between the internal electrodes 3, 5, 7, and 9 and dielectric layers 2, 4, 6, 8, and 10, and as a result, the yield is enhanced.

Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Abstract: A capacitor element includes a pair of conductor layers, a plurality of generally tube-shaped dielectric substances, a first electrode outside the dielectric substances and second electrodes in the insides thereof, and insulation caps for insulating the first electrode from the conductor layer, wherein an electrode material is filled in gaps of a structure of an oxide base material resulting from anodic oxidation of a metal, and then, the structure is removed and replaced by a high permittivity material.

Abstract: A film capacitor is provided which has a smaller size and improved capacity while securing a sufficient withstand voltage. The film capacitor comprising a basic element 10 containing a plurality of dielectric layers and at least one vapor-deposited metal film layer 14a, 14b, where the plurality of dielectric layers consisting of a resin film layer 12 and at least one vapor-deposited polymer film layer 16a, and the at least one vapor-deposited polymer film layer 16a is formed on at least one of the resin film layer 12 and the at least one vapor-deposited metal film layer 14a, 14.

Abstract: A semiconductor ceramic comprising a donor element within the range of 0.8 to 2.0 mol relative to 100 mol of Ti element contained as a solid solution with crystal grains, a first acceptor element in an amount less than the amount of the donor element is contained as a solid solution with the crystal grains, a second acceptor element within the range of 0.3 to 1.0 mol relative to 100 mol of a Ti element is present in crystal grain boundaries, and the average grain size of the crystal grains is 1.0 ?m or less. A monolithic semiconductor ceramic capacitor is obtained by using this semiconductor ceramic. To form the semiconductor ceramic, in a first firing treatment to conduct reduction firing, a cooling treatment is conducted while the oxygen partial pressure at the time of starting the cooling is set at 1.0×104 times or more the oxygen partial pressure in the firing process.

Abstract: A method of fabricating an integrated circuit device includes forming a plurality of lower capacitor electrodes vertically extending from a substrate. The plurality of lower capacitor electrodes respectively include an inner sidewall and an outer sidewall. At least one support pattern is formed vertically extending between ones of the plurality of lower capacitor electrodes from top portions thereof opposite the substrate and along the outer sidewalls thereof towards the substrate to a depth that is greater than a lateral distance between adjacent ones of the plurality of lower capacitor electrodes. A dielectric layer is formed on the support pattern and on outer sidewalls of the plurality of lower capacitor electrodes, and an upper capacitor electrode is formed on the dielectric layer. Related devices are also discussed.

Abstract: Film capacitor assembly has a plurality of film capacitive layers for storing an electric charge. The plurality of film capacitive layers have a first metal contact and a second metal contact. A heat sink removes heat from the plurality of film capacitive layers. The heat sink is in thermal conductive communication with at least one of the first metal contact and the second metal contact. A dielectric material is configured to prevent a transmission of electric current through the heat sink from the plurality of film capacitor capacitive layers.

Abstract: This invention provides navel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.