Abstract: A thin-film capacitor having a first and a second capacitor element disposed on a substrate substantially on the same plane adjacent to each other and laterally spaced in a direction along the plane. Each capacitor includes a dielectric layer and two electrode layers formed on the upper and lower side of the dielectric layer, respectively. The upper electrode layer of the first capacitor and the lower electrode layer of the second capacitor are electrically connected, and lower electrode layer of the first capacitor and the upper electrode layer of the second capacitor are electrically connected, via connection terminal electrodes. A plurality of such thin-film capacitors may be laminated, or placed side-by-side on the substrate.

Abstract: There is provided a (Ba, Sr) TiO.sub.3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM).sub.2 /THF, Sr(DPM).sub.2 /THF and TiO(DPM).sub.2 /THF solutions which are used as source material solutions. A (Ba, Sr) TiO.sub.3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.

Abstract: A capacitor and method of making is described incorporating a semiconductor substrate, a bottom electrode formed on or in the substrate, a dielectric layer of barium or lead silicate, and a top electrode. A sandwich dielectric of a barium or lead silicate and a high dielectric constant material such as barium or lead titanate may form the dielectric. The silicate layer may be formed by evaporating and diffusing, ion implanting, or electroplating and diffusing barium or lead. The high epsilon dielectric constant material may be formed by sol gel deposition, metal organic chemical vapor deposition or sputtering. The invention overcomes the problem of a bottom electrode and dielectric layer which chemically interact to form a silicon oxide layer in series or below the desired dielectric layer.

Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

Abstract: A metallized film capacitor is provided with a polyurethane oil insulating fluid. The insulating fluid has a viscosity in the range of about 500 to 3000 poise at 25.degree. C. The polyurethane oil insulating fluid is produced by reacting an organic polyisocyanate with a primary polyol selected from the group consisting of castor oil, ricinoleic acid derivatives of castor oil and mixtures thereof. The reaction may be carried out in the presence of a secondary polyol chain extender such as a hydroxy-terminated polybutadiene diol. The reaction to produce the insulating fluid is carried out under conditions wherein the ratio of NCO groups of the organic polyisocyanate to OH groups of the primary and secondary polyols, if present, is in the range of about 0.1 to 1 to about 0.6 to 1. The ratio ensures that there is no excess of unreacted NCO groups in the insulating fluid and that the reaction produces a viscous fluid, not a substantially solid elastomer.

Abstract: An adherent separator structure with a post projecting from a surface which may be a substrate, and a separator adhering to the post, the separator spaced a distance above the surface. A discontinuous film is then formed in a single process step having a first portion on the substrate and a second portion on the post, the discontinuity proximate to and caused by the separator. The structure is made into a stacked capacitor with the second (post) portion of the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A monolithic ceramic capacitor has laminated plural dielectric ceramic layers, internal electrodes disposed between dielectric ceramic layers, and external electrodes formed at edge surfaces of the dielectric ceramic layers such that they are connected to alternate internal electrodes, wherein the dielectric ceramic layers are composed of a material comprising a principal component shown by the formula: (1-.alpha.-.beta.-.gamma.){BaO}.sub.m.TiO.sub.2 +.alpha.M.sub.2 O.sub.3 +.beta.Re.sub.2 O.sub.3 +.gamma.(Mn.sub.1-x-y Ni.sub.x Co.sub.y)O (wherein M.sub.2 O.sub.3 is at least one kind of Sc.sub.2 O.sub.3 and Y.sub.2 O.sub.3 ; Re.sub.2 O.sub.3 is at least one kind of Sm.sub.2 O.sub.3 and Eu.sub.2 O.sub.3 ; 0.0025.ltoreq..alpha.+.beta..ltoreq.0.025, 0<.beta..ltoreq.0.0075, 0.0025.ltoreq..gamma..ltoreq.0.05, .gamma./(.alpha.+.beta.).ltoreq.4, 0.ltoreq.x<1.0, 0.ltoreq.y<1.0, 0.ltoreq.x+y.ltoreq.1.0, and 1.000<m.ltoreq.1,035), and containing definite amounts of MgO and SiO.sub.2 as side components.

Abstract: Ferroelectric PbZr.sub.x T.sub.1-x O.sub.3 (PZT) thin films are deposited on Pt coated Si substrates by using RF magnetron sputtering. A method for obtaining desirable stoichiometric PZT, the desired ferroelectric perovskite phase, and better dielectric properties using a PZT target with Pb/(Zr+Ti) ratio of 1.2 and depositing at 350.degree. C., followed by thermal treatment at 620.degree. C. for 30 min is disclosed. The structural and electrical properties of the PZT layer were further improved by a method of fabricating a novel multi-layer structure which combined the PZT thin film with nanolayers of BaTiO.sub.3. The method and device of the present invention provided reduced leakage current density while maintaining high relative effective dielectric constants.

Abstract: A capacitor and method in which there is provided additional extraneous plate surface area, beyond the paired plate surface area normally provided to furnish capacitance. This additional extraneous plate surface area is located outside the intraplate internal volume, of plate pairs contributing substantial capacitance, or of mutually facing n-tuples of plates. Various configurations for this additional extraneous plate surface area are taught. This additional extraneous plate surface area can improve the electrical performance of the capacitor.

Abstract: A finished capacitor product and method in which the outer dielectric, protecting or encapsulating the basic inner capacitor structure, is improved in dielectric quality, relative to prior art and relative to the inner dielectric between plates. This improved outer dielectric has been experimentally demonstrated to provide improved electrical performance, including better signal handling performance, for the capacitor. This finding is contrary to prior art, which has attached great significance to the quality of the inner dielectric between capacitor plates, but has not attached great significance to the quality of the dielectric outside the capacitor plates.

Abstract: A capacitor module having a solid dielectric is cleared in a gaseous environment having an electric strength greater than that of air at a pressure of one atmosphere. A plurality of such cleared capacitor modules is formed into a stack which itself is then cleared by the same clearing process. During intended operation in an electric circuit, the capacitor arrangement would be maintained in such gaseous environment having an electric strength greater than that of air at a pressure of one atmosphere.

Abstract: A multilayer ceramic capacitor is made of a principal component (100 mol) represented by the compositional formula(1-.alpha.-.beta.) {BaO}.sub.m .multidot.TiO.sub.2 +.alpha.Re.sub.2 O.sub.3 +.beta.(Mn.sub.1-x-y Ni.sub.x CO.sub.y)O(where Re.sub.2 O.sub.3 is at least one of Y.sub.2 O.sub.3, Tb.sub.2 O.sub.3, Dy.sub.2 O.sub.3, Ho.sub.2 O.sub.3, Er.sub.2 O.sub.3 and Yb.sub.2 O.sub.3 ; and .alpha., .beta., m, x, and y are 0.0025 .ltoreq..alpha..ltoreq.0.025, 0.0025 .ltoreq..beta..ltoreq.0.05, .beta./.alpha..ltoreq.4, 0 .ltoreq.x <1.0, 0 .ltoreq.y <1.0, 0 .ltoreq.x +y<1.0, and 1.000<m.ltoreq.1.035.), a secondary component (about 1-3.0 mol) of magnesium oxide (MgO), and Al.sub.2 O.sub.3 -MO-B.sub.2 O.sub.3 oxide glass (where MO is at least one of BaO, CaO, SrO, MgO, ZnO and MnO) in an amount of about 0.2-3.0 parts by weight for 100 parts by weight of the total amount of said principal component and secondary component.

Abstract: An in situ method for forming a bypass capacitor element internally within a PCB including the steps of arranging one or more uncured dielectric sheets with conductive foils on opposite sides thereof and laminating the conductive foils to the dielectric sheet simultaneously as the PCB is formed by a final lamination step, the conductive foils preferably being laminated to another layer of the PCB prior to their arrangement adjacent the dielectric sheet or sheets, the dielectric foils even more preferably being initially laminated to additional dielectric sheets in order to form multiple bypass capacitive elements as a compound subassembly within the PCB. A number of different dielectric materials and resins are disclosed for forming the capacitor element.

Abstract: The invention provides a multilayer ceramic chip capacitor which satisfies X7R property or a temperature response of its capacitance and shows a minimal change of capacitance with time under a DC electric field, a long accelerated life of insulation resistance (IR) and good DC bias performance and also provides a multilayer ceramic chip capacitor which is resistant to dielectric breakdown in addition to the above advantages. In a first form of the invention, dielectric layers contain BaTiO.sub.3 as a major component and MgO, Y.sub.2 O.sub.3, at least one of BaO and CaO, and SiO.sub.2 as minor components in a specific proportion. In a second form, the dielectric layers further contain MnO and at least one of V.sub.2 O.sub.5 and MoO.sub.3 as minor components in a specific proportion. In the first form, the dielectric layer has a mean grain size of up to 0.45 .mu.

Abstract: One aspect of the present invention is directed to a capacitor. The capacitor includes a first layer and a second layer. The first layer includes a first electrically conductive substrate having a first surface and a second surface. A first dielectric film is deposited on the first surface of the first substrate and a second dielectric film is deposited on the second surface of the first substrate. The second layer contacts the first layer. The second layer includes a second electrically conductive substrate having a first surface and a second surface. A third dielectric film is deposited on the first surface of the second substrate, and a fourth dielectric film is deposited on the second surface of the second substrate.

Abstract: An encapsulated capacitor structure and method for fabricating same. The capacitor structure is created by selectively depositing a lower electrode, a dielectric thin film of BST or other ferrodielectric, and an upper electrode, onto a substrate, and subsequently depositing a conformal layer of a non-reductively deposited dielectric material. Contact windows are then opened through the encapsulating layer for contacting the capacitor electrodes. The underlying structure is protected by the encapsulating layer from metal deposition and post-processing which would otherwise damage the structure.

Abstract: An MIM capacitor includes a lower electrode; a first insulating film disposed on the lower electrode; a second insulating film disposed on the first insulating film and having a first opening exposing a portion of the surface of the first insulating film on the lower electrode, the first opening having a perimeter; a third insulating film disposed on the second insulating film and having a second opening exposing a portion of the surface of the second insulating film, the second opening having a perimeter that surrounds the perimeter of the first opening on the second insulating film; and an upper electrode disposed on the first insulating film through the first opening and extending onto the second insulating film.

Abstract: A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer.

Abstract: Disclosed is a capacitor incorporating a material having a high dielectric constant. In a preferred embodiment, the bottom electrode is first deposited and patterned. An insulating diffusion barrier, such as LPCVD silicon nitride, is deposited over the bottom electrode and a contact is opened in the silicon nitride to exposed the bottom electrode. This contact is filled with the dielectric material. In a disclosed embodiment, the dielectric material is deposited in solution form and crystallized in a high-temperature step. A top conductive layer is deposited over the dielectric material, masked and etched to form the top conductive layer. This etch may simultaneously etch any portion of the dielectric layer overflowing the contact via.

Abstract: A capacitor structure is described as having a plurality of dielectric materials located so that each dielectric material is in parallel between capacitor plates. The capacitor value of this structure is preset, therefore, for operation electrically at different specific temperatures. The description gives a specific stacked arrangement for the various dielectric materials in which this capacitor can be formed, as one example of that to which it is adaptable.

Abstract: A ferroelectric capacitor structure and its method of making in which a ferroelectric stack of two metal-oxide electrodes sandwiching a ferroelectric layer is fabricated on a silicon substrate with an intervening barrier layer, preferably of TiN. In one embodiment, a platinum layer is grown between the TiN and the lower metal-oxide electrode at a sufficiently high temperature that provides crystallographically ordered growth of the ferroelectric stack. In another embodiment, the platinum layer was completely eliminated with the lower electrode being grown directly on the TiN. Although the conventional conductive metal-oxide used in the electrode is lanthanum strontium cobalt oxide (LSCO), lanthanum nickel oxide provides good electrical and lifetime characteristics in a ferroelectric cell. Alternatively, the electrodes can be formed of the rock-salt metal oxides, such as neodymium oxide (NdO).

Abstract: An overhanging separator structure with a post projecting from a surface which may be a substrate, an underlying layer on the surface, and a separator layer on the underlying layer, with the separator layer overhanging the underlying layer. A discontinuous film is then formed in a single process step having a first portion on the separator layer and a second portion on the post, the discontinuity caused by the overhanging separator layer. The structure is made into a stacked capacitor with the second (post) portion of the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

Abstract: A multi-layer printed circuit board comprises a first metallic layer, a first Ta or Hf layer on one face of the first metallic layer, a first layer of Ta.sub.2 O.sub.5 or HfO on a face of the Ta or Hf layer opposite the first metallic layer, a second metallic layer on the Ta.sub.2 O.sub.5 or HfO layer opposite the Ta or Hf layer, a first dielectric layer on the first metallic layer opposite the Ta of Hf layer, and a second dielectric layer on the second metallic layer opposite the Ta.sub.2 O.sub.5 or HfO layer. A multi-layer printed circuit board is formed by adding the following layers to form the second capacitor. A third metallic layer on said second dielectric layer, a second Ta or Hf layer on a face of the third metallic layer, a second Ta.sub.2 O.sub.5 or HfO layer on a face of the second Ta or Hf layer opposite the third metallic layer, a fourth metallic layer on the second Ta.sub.2 O.sub.

Abstract: A capacitor is formed of at least two metal conductors having a multilayer dielectric and opposite dielectric-conductor interface layers in between. The multilayer dielectric includes many alternating layers of amorphous zirconium oxide (ZrO.sub.2) and alumina (Al.sub.2 O.sub.3). The dielectric-conductor interface layers are engineered for increased voltage breakdown and extended service life. The local interfacial work function is increased to reduce charge injection and thus increase breakdown voltage. Proper material choices can prevent electrochemical reactions and diffusion between the conductor and dielectric. Physical vapor deposition is used to deposit the zirconium oxide (ZrO.sub.2) and alumina (Al.sub.2 O.sub.3) in alternating layers to form a nano-laminate.

Abstract: Metal, normally gold or platinum, is printed, and is adhered by a glass frit, on the top and/or bottom surfaces of a multi-layer laid-up green ceramic wafers containing typically up to 16 layers and 800+ separate devices, typically 800+ monolithic, buried-substrate, ceramic multiple capacitors. The wafer is diced, and the multiple ceramic capacitors each with its patterned surface metal are co-fired. The integrally formed, top and bottom surface, conduction traces connect similarly formed pads, typically disposed in a "pin-grid" pattern, to later-added side traces or conductive castellations that connect to the electrodes of multiple buried-substrate capacitors. The pads are precisely located, and extend over such ample areas, to support the stable surface mounting, and the reliable electrical connection of, diverse external electrical circuits and components.

Abstract: Sheet capacitive materials for use in forming a thin-film capacitor comprise an electrically nonconductive substrate, a layer of electrically conductive material disposed a surface of the substrate, and a layer of electrically nonconductive material disposed onto a surface of the conductive material layer. The conductive material layer includes a contact area along a first lengthwise edge of the substrate that is thicker than remaining portions of the material layer. A portion of the substrate adjacent a second lengthwise edge remains exposed. The electrically nonconductive material includes an anti-stick component, and covers the exposed substrate surface and a major portion of the material layer except for the contact area. A first and second sheet is constructed having contact areas along opposite lengthwise edges. The sheets are placed together so that the contact areas are oriented at opposite lengthwise edges, and are staggered so that the contact areas remain exposed.

Abstract: A solid electrolytic capacitor having a solid electrolyte comprising manganese dioxide dispersed in an aromatic polyamide capable of further cure to form polyimide linkages, the solid electrolyte being disposed between a first electrode made of valve metal covered by an anodic oxide film and a second electrode opposite the first electrode. The electrolyte autogenously produces water, oxygen, and hydroxyl groups which act as healing substances and is not itself produced pyrolytically. Reduction of the manganese dioxide and the water molecules released by formation of imide linkages result in substantially improved self-healing of anodic dielectric layer defects.

Abstract: A capacitor having an enhanced dielectric breakdown strength is obtained m a base dielectric film by coating the base dielectric film on both sides with an adherent coated dielectric film having a dielectric constant that is at least 50 percent higher than that of the base dielectric film and that adheres to the base dielectric film; and wherein metal foil is adherently joined to each of the coated dielectrics films to form electrodes for the capacitor.

Abstract: Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. A thick, planarized insulating layer is deposited over the bottom electrode and a contact via is opened in the insulating layer to exposed the bottom electrode. This via is filled with the dielectric material. A top conductive layer is deposited over the dielectric material, masked and etched to form the top conductive layer. This etch may simultaneously etch any portion of the dielectric layer overflowing the contact via.

Abstract: A monolithic, buried-substrate, ceramic multiple capacitor is laid up as multiple capacitors that are isolated, one to the next, by a dual-dielectric-constant, three-layer-laminate, isolation layer. Each isolation layer has and presents (i) an innermost layer of a low dielectric constant (low K) material, located between (ii) outer laminate layers of a high dielectric constant (high K) material. By such construction negative effects of the physio-chemical reaction (i) occurring at the boundary between the high-K and low-K layers, (ii) contaminating the high-K dielectric and lowering its K, and (iii) undesirably serving both to lower the capacitance of any (buried substrate) capacitor that makes use of the ("contaminated") high-K dielectric while increasing capacitor leakage current, are mitigated or avoided.

Abstract: A preferred embodiment of this invention comprises a thin unreactive film (e.g. ruthenium dioxide 36) contacting a high-dielectric-constant material (e.g. barium strontium titanate 38) to an electrode. The thin unreactive film provides a stable conductive interface between the high-dielectric-constant material layer and the electrode base (e.g palladium 34). As opposed to a standard thin-film layer, the thin unreactive film is generally less than 50 nm thick, preferably less than 35 nm thick, more preferably between 5 nm and 25 nm thick, and most preferably between 10 nm and 20 nm thick. A thin unreactive film can benefit from the advantages of the materials used while avoiding or minimizing many of their disadvantages. A thin unreactive film would generally be substantially less expensive than a standard thin-film layer since much less material can be used while not significantly affecting the surface area of the electrode in contact with the HDC material.

Abstract: A film capacitor in which the unmetallized margin is provided with a semiconductive layer. The layer provides a parallel resistive path within the capacitor, itself, obviating the need for an external resistor. It also grades the electric field across the margin, i.e., makes the field more uniform, thus allowing the margin to be made narrower without electrical breakdown, permitting a reduction in the physical size of the capacitor. A refractory, semiconductive layer is provided between the metal layer and the dielectric film. The refractory layer accelerates the self-clearing process, by insulating the underlying dielectric film from the heat generated by the vaporizing metal, thus hastening vaporization and reducing the tendency of the dielectric film to carbonize. As a result, faults are cleared with substantially less energy consumption. Preferably, the refractory layer is also semiconductive, to reduce field emission effects, and thereby decrease the frequency of faults in the dielectric film.

Abstract: A capacitor employing plural dielectric materials between oppositely facing, distinctly electrically connected plates, or employing interspersed plural dielectric materials outside the space between oppositely facing, distinctly electrically connected plates, wherein one material is a plastic and a second material is a plastic, gas, or vacuum. A method for ameliorating the frequency dependent variation pattern in dielectric behavior, of a single material employed as a dielectric in a capacitor, by employing a plurality of materials between oppositely facing, distinctly electrically connected plates, and/or by employing an interspersed plurality of materials outside the space between oppositely facing, distinctly electrically connected plates.

Abstract: An on-chip decoupling capacitor is disclosed. The capacitor of the present invention is fabricated using an embedded conductive layered structure. A first insulative layer, a first conductive layer, a second insulative layer, a second conductive layer, and a third insulative layer are deposited sequentially on a substrate having electronic circuitry. Next, a patterning layer is formed to provide for vias for interconnection between metal layers above and below the capacitor plates. An etch is then performed to form a via through the first, second and third insulative layers and the first and second conductive layers. Next, a fourth insulative layer is deposited and anisotropically etched to form sidewall insulators on the vias. Finally, interconnection between lower level metal levels and upper level metal levels is made through the vias. Additionally, methods of coupling the upper and lower capacitor plates to either power or ground are described.

Abstract: A capacitor array in which a plurality of inner electrodes are formed so as to be overlapped with each other in the thickness direction while being separated by a ceramic layer in a ceramic sintered body to construct a plurality of capacitor units, and the plurality of capacitor units are separated from each other by a layer having a lower dielectric constant than that of ceramics composing the sintered body.

Abstract: A film capacitor element produced from a metallized polyester film is described. In the metallized polyester film, the adhesion between a vapor-deposited metal layer and a polyester substrate is improved by providing a coating layer comprising a specific water soluble or water dispersible resin. The film capacitor produced by the use of the metallized polyester film has good moist heat resistance and long term stability in performance.

Abstract: A flexible, multilayer thin film capacitor comprises a flexible substrate and at least two electrode layers mounted on the substrate alternately with at least one dielectric layer. The dielectric layer may include amorphous hydrogenated carbon. The at least two electrode layers and the at least one dielectric layer are capable of acting as at least one capacitor, and the flexible substrate is capable of being manipulated so as to have a desired shape.

Abstract: A capacitor includes a planar electrode layer which is mounted between a pair of dielectric layers. The electrode layer generally is centered inwardly with respect to the dielectric layers leaving an outward margin of dielectric material. One of the dielectric layers has two spaced apart contact members, each having a different polarity from the other. The electrode layer is isolated from electrical contact with any conductor and is buried within the dielectric layers. The electrode layer, in combination with the dielectric layer on which the contact members are mounted and the contact members, allow development of a selected value of capacitance between the contact members. Providing trimmed contact members as well as controlling their size and spacing allow for convenient preselection of desired operative characteristics of the capacitor. The contact members could be positioned on a substrate to which a buried electrode is mounted.

Abstract: A preferred embodiment of this invention comprises a thin unreactive film (e.g. platinum 36) contacting a high-dielectric-constant material (e.g. barium strontium titanate 38) to an electrode. The thin unreactive film provides a stable conductive interface between the high-dielectric-constant material layer and the electrode base (e.g. palladium 34). As opposed to a standard thin-film layer, the thin unreactive film is generally less than 50 nm thick, preferably less than 35 nm thick, more preferably between 5 nm and 25 nm thick, and most preferably between 10 nm and 20 nm thick. A thin unreactive film can benefit from the advantages of the materials used while avoiding or minimizing many of their disadvantages. A thin unreactive film would generally be substantially less expensive than a standard thin-film layer since much less material can be used while not significantly affecting the surface area of the electrode in contact with the HDC material.

Abstract: In an electronic device using lead zirconate titanate (PZT) or lanthanum lead zirconate titanate (PLZT) as the main insulating material, a PZT film or a PLZT film is formed on a sub-insulating layer consisting essentially of lead titanate, lanthanum lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate, or lanthanum lead zirconate. In an MIS structure, a semiconductor, the sub-insulating layer, the PZT film and metal are deposited in order. In a capacitor, the sub-insulating layer and the PZT film are sandwiched between a pair of electrodes. The sub-insulating layer improves crystallinity of PZT or PLZT, and the dielectric constant. An oxide of Pb, La, Zr or Ti can be added as the sub-insulating layer in order to further suppress current leakage.

Abstract: A preferred embodiment of this invention comprises a thin unreactive film (e.g. platinum 36) contacting a high-dielectric-constant material (e.g. barium strontium titanate 38) to an electrode. The thin unreactive film provides a stable conductive interface between the high-dielectric-constant material layer and the electrode base (e.g palladium 34). As opposed to a standard thin-film layer, the thin unreactive film is generally less than 50 nm thick, preferably less than 35 nm thick, more preferably between 5 nm and 25 nm thick, and most preferably between 10 nm and 20 nm thick. A thin unreactive film can benefit from the advantages of the materials used while avoiding or minimizing many of their disadvantages. A thin unreactive film would generally be substantially less expensive than a standard thin-film layer since much less material can be used while not significantly affecting the surface area of the electrode in contact with the HDC material.

Abstract: A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

Abstract: In a semiconductor device which has a substrate, at least one thin film capacitor having a lower electrode layer deposited on the substrate, a dielectric layer overlaid on the lower electrode layer, and an upper electrode layer stacked on the dielectric layer, the lower electrode layer is surrounded by an insulator layer of Si.sub.3 N.sub.4.

Abstract: A capacitor structure is described as having a plurality of dielectric materials located so that each dielectric material is in parallel between capacitor plates. The capacitor value of this structure is preset, therefore, for operation electrically at different specific temperatures. The description gives a specific stacked arrangement for the various dielectric materials in which this capacitor can be formed, as one example of that to which it is adaptable.

Abstract: A semiconductor device and a manufacturing method thereof are disclpsed, the semiconductor device comprising: a first conductive layer; an oxide layer formed upon the first conductive layer; a nitride layer composed of multiple sublayers formed upon the oxide layer; another oxide layer formed upon the nitride layer in the form of multiple sublayers; and a second conductive layer formed upon the structure obtained through the preceding steps. Due to the unique feature of the nitride layer composed of multiple sublayers, the electrical characteristics of the semiconductor device according to the present invention is improved, and the nitride layer according to the present invention is widely applicable to semiconductor devices.

Abstract: A reduced size three-terminal type capacitor for removing jamming signals from an electrical signal. The three-terminal type capacitor comprises a ceramic substrate with a first ground electrode layer formed on the ceramic substrate, and a first dielectric layer formed on the first ground electrode layer. On the first dielectric layer reaching at least from one end of the first dielectric layer to the other end is a signal electrode. A second dielectric layer is formed on the first dielectric layer to surround the signal electrode together with the first dielectric layer, and a second ground electrode layer is formed on the second dielectric layer together with the first ground electrode layer. The second ground electrode layer is electrically connected to the first ground electrode layer. The structure of this three-terminal capacitor is such that first and second conductive layers (i.e.

Abstract: A method of fabricating a semiconductor wafer comprises providing an electrically conductive area on a semiconductor wafer. Multiple alternating layers of first and second materials are provided atop the wafer. The first and second materials need be selectively etchable relative to one another. The multiple layers are etched and the electrically conductive area upwardly exposed to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area. One of the first or second materials is selectively isotropically etched relative to the other to produce indentations which extend generally laterally into the exposed edges of the multiple layers. A layer of electrically conductive material is applied atop the wafer and electrically conductive area, and fills the exposed edge indentations.

Abstract: An electrical filter connector comprises a metal shell (10,18) in which is secured a dielectric housing (8) having electrical contacts (6,6',6") secured therein, a filter member (30,50,70) electrically connected to the metal shell and having a plate member (34,52,72) provided with a multiplicity of through holes (32,54,74) with capacitors (42,56,80) at each through hole, and post members (6a,6a',6a") of the contacts disposed in the through holes and electrically connected to the capacitors thereat.