Abstract: Embodiments relate to a capacitor in a semiconductor device having high capacitance and a manufacturing method thereof. The capacitor includes a bottom electrode over a substrate, a dielectric layer stacked over the bottom electrode and including a first dielectric layer having a thickness of about 30 ?±2 ?, a second dielectric layer having a thickness of about 100 ?±5 ?, and a third dielectric layer having a thickness of about 30 ?±2 ?, and a top electrode over the dielectric layer. Since dielectric layers having great band gaps are deposited over and under the top and bottom of the dielectric layer having a small band gap, the electric stability and leakage current characteristic are improved. The capacitor may have a high capacitance of 8 fF or above, and may be used for semiconductor devices, for example in development of high technology DRAM and CMOS devices.

Abstract: A dielectric ceramic is provided having a high relative dielectric constant, and in the case in which it is used for a multilayer ceramic capacitor, high insulating properties and superior reliability can be obtained even when the thickness of a dielectric ceramic layer is decreased. The dielectric ceramic used for forming the dielectric ceramic layer of a multilayer ceramic capacitor has a composition represented by 100 (Ba1?w?x?mCawSrxGdm)k(Ti1?y?z?nZryHfzMgn)O3+a+pMnO2+qSiO2+rCuO, in which 0.995?k?1.010, 0?w<0.04, 0?x?0.04, 0?y?0.10, 0?z?0.05, 0.015?m?0.035, 0.015?n?0.035, 0.01?p?1.0, 0.5?q?2.5, and 0.01?r?5.0. In addition, a is a value selected with respect to the deviation from 3 so that the primary component is electrically neutral.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.

Abstract: A method of manufacturing a sensor for in vivo applications includes the steps of providing two wafers of an electrically insulating material. A recess is formed in the first wafer, and a capacitor plate is formed in the recess of the first wafer. A second capacitor plate is formed in a corresponding region of the second wafer, and the two wafers are affixed to one another such that the first and second capacitor plates are arranged in parallel, spaced-apart relation.

Abstract: An apparatus comprising a capacitor stack, including one or more substantially planar anode layers, and one or more substantially planar cathode layers. Additionally, the capacitor has a case having a first opening and a second opening, the first opening sized for passage of the capacitor stack, and a cover substantially conforming to the first opening and sealingly connected to the first opening. Also, the capacitor includes a plate substantially conforming to the second opening and sealingly connected to the second opening, the plate defining an aperture. Additionally, the capacitor includes a plug substantially conforming to the aperture in the plate, the plug sealingly connected to the plate. The capacitor stack is disposed in the case, and the terminal is in electrical connection with the case and at least one capacitor electrode.

Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.

Abstract: Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).

Abstract: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes forming a lower electrode over a certain structure, forming a dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer over the lower electrode, and forming an upper electrode over the dielectric structure.

Abstract: A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a silicon nitride film that has a plurality of silicon-hydrogen bonds and a plurality of nitride-hydrogen bonds. A ratio of silicon-hydrogen bonds to nitride-hydrogen bonds is equal to or smaller than 0.5. Accordingly, the nitrogen-rich and compressive silicon nitride film can improve the breakdown voltage of the MIM capacitor.

Abstract: Described herein are methods for making articles comprising a dielectric layer formed from any solution composition that can form barium titanate during firing and containing manganese in an amount between 0.002 and 0.05 atom percent of the solution composition, wherein the dielectric layer has been formed on metal foil and fired in a reducing atmosphere.

Abstract: It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film.

Abstract: A thin-film device includes a substrate, and a capacitor provided on the substrate. The capacitor incorporates a lower conductor layer having a top surface and a side surface; a flattening film disposed to cover the top and side surfaces of the lower conductor layer; a dielectric film disposed on the flattening film; and an upper conductor layer disposed on the dielectric film. The lower conductor layer is composed of an electrode film and a plating film disposed on the electrode film. The dielectric film has a thickness that falls within a range of 0.02 to 1 ?m inclusive and that is smaller than a thickness of the lower conductor layer. A surface roughness in maximum height of a top surface of the flattening film is smaller than that of the top surface of the lower conductor layer and equal to or smaller than the thickness of the dielectric film.

Abstract: The present invention relates to a multi-layer ceramic capacitor printed simultaneously with internal electrode and external electrode by employing an inkjet printing. A method for manufacturing the multi-layer ceramic capacitor comprising first external electrode, dielectric, internal electrode and second external electrode prints simultaneously the first external electrode; the internal electrode which is connected with the first external electrode and formed at an invaginated portion of the dielectric invaginated to allow one side to be opened at one portion; and the second external electrode which is formed integrally with the internal electrode by employing an inkjet printing. According to the present invention, a method for manufacturing the multi-layer ceramic capacitor resolves contact problems by printing integrally the internal electrode and the external electrode and reduces the manufacturing process.

Abstract: Provided is a multilayer ceramic capacitor including external electrodes which also functions as a resistive element, and the external electrodes achieve strong bonding with internal electrodes containing Ni or a Ni alloy. The external electrodes include a resistive electrode layers contacting a ceramic laminate and internal electrodes. The resistive electrode layers contains a complex oxide which reacts with Ni or a Ni alloy contained in the internal electrodes in a proportion of 26 to 79% by weight, a glass component in a proportion of 20 to 56% by weight, and metal which reacts with Ni or a Ni alloy in a proportion of 1 to 18% by weight.

Abstract: The invention aims at providing a dielectric ceramic composition including BamTiO2+m where “m” satisfies 0.99?m?1.01 and BanZrO2+n where “n” satisfies 0.99?n?1.01, an oxide of Mg, an oxide of R where R is at least one selected from Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, an oxide of at least one element selected from Mn, Cr, Co and Fe, and an oxide of at least one element selected from Si, Li, Al, Ge and B. 35 to 65 moles of BanZrO2+n, 4 to 12 moles of an oxide of Mg, 4 to 15 moles of an oxide of R, 0.5 to 3 moles of an oxide of Mn, Cr, Co and Fe, and 3 to 9 moles of an oxide of Si, Li, Al, Ge and B are included therein per 100 moles of the BamTiO2+m.

Abstract: A thin film capacitor element composition having a bismuth layered compound with a c-axis oriented substantially vertical to the substrate surface, wherein the bismuth layered compound is expressed by the formula (Bi2O2)2+(Am?1BmO3m+1)2? or Bi2Am?1BmO3M+3, the symbol m in the formula is an odd number, at least part of the Bi and/or A of the bismuth layered compound is substituted by a rare earth element, and the number of moles substituted by the rare earth element is larger than 1.0 and 2.8 or less with respect to the number of moles (m+1) of the total of Bi and A.

Abstract: Disclosed herein is a polymer-ceramic dielectric composition. The dielectric composition comprises a polymer and a ceramic dispersed in the polymer wherein the ceramic is composed of a material having a perovskite structure represented by ABO3 and a metal oxide dopant and has an electrically charged surface. According to the dielectric composition, the surface of the ceramic is electrically charged to induce space-charge polarization (or interfacial polarization) at the polymer/ceramic interface, resulting in an increase in dielectric constant. Since the dielectric composition has a high dielectric constant particularly in a low-frequency range, it can be suitably used to produce decoupling capacitors.

Abstract: A method for forming a variable capacitor including a conductive strip covering the inside of a cavity, and a flexible conductive membrane placed above the cavity, the cavity being formed according to the steps of: forming a recess in the substrate; placing a malleable material in the recess; having a stamp bear against the substrate at the level of the recess to give the upper part of the malleable material a desired shape; hardening the malleable material; and removing the stamp.

Abstract: This electronic component comprises a substrate; and a capacitor part provided on the substrate, the capacitor part includes a first electrode part provided on the substrate; a dielectric film covering the first electrode part; an insulating film that contacts the dielectric film and has an opening part; and a second electrode part that contacts an inner wall surface of the opening part of the insulating film and a surface of the dielectric film, and when the angle between a first interface between the dielectric film and the insulating film, and a second interface between the insulating film and the second electrode part is ?, ? is not more than 22°.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a method may include forming a multilayer dielectric film on and/or over a lower metal line and forming an upper metal layer on and/or over the multilayer dielectric film. A semiconductor device fabricated by the method may include a lower metal line, a multilayer dielectric film including a plurality of layers laminated in this order on and/or over the lower metal line, and an upper metal layer arranged on and/or over the multilayer dielectric film. Accordingly, a semiconductor device may achieve a high-capacitance (i.e. not less than 6 fF/um2) capacitor that may be useful for non-memory products, e.g., logic products. In addition, the capacitor may have a high capacitance, and may exhibit superior durability and reliability due to good leakage current and breakdown voltage properties.

Abstract: A multi-layer ceramic capacitor including: a ceramic sintered body having cover layers provided on upper and lower surfaces thereof as outermost layers and a plurality of ceramic layers disposed between the cover layers; first and second internal electrodes formed on the ceramic layers, the first and second internal electrodes stacked to interpose one of the ceramic layers; first and second external electrodes formed on opposing sides of the ceramic sintered body to connect to the first and second internal electrodes, respectively; and anti-oxidant electrode layers formed between the cover layers and adjacent ones of the ceramic layers, respectively, the anti-oxidant electrode layers arranged not to affect capacitance.

Abstract: A method of forming a conductor on a substrate including steps of depositing tantalum on a glass layer of the substrate; oxidizing the tantalum; and depositing a noble metal on the oxidized tantalum to form the conductor. The method can be used to form a ferroelectric capacitor or other thin film ferroelectric device. The device can include a substrate comprising a glass layer; and an electrode connected to the glass layer. The electrode comprising can include a noble metal connected to the glass layer by an adhesion layer comprising Ta2O5.

Abstract: A capacitor is provided. The capacitor includes a dielectric polymer film comprising a cyanoresin and at least one electrode coupled to the dielectric polymer film. The capacitor has an energy density of at least about 5 J/cc. A method of making a capacitor is provided. The method includes dissolving a cyanoresin in a solvent to form a solution and coating the solution on a substrate to form a dielectric polymer film. The dielectric polymer film has a breakdown strength of at least about 300 kV/mm.

Abstract: Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof.

Abstract: In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

Abstract: Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. In one embodiment, the new MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.

Abstract: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each component is Ni: 80 to 100 mol % (note that 100 mol % is excluded) and a total of Ru, Rh, Re and Pt: 0 to 20 mol % (note that 0 mol % is excluded).

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

Abstract: Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: In a multilayer capacitor including a capacitor body, first capacitor portions and a second capacitor portion are arranged in the direction of lamination. While a resonant frequency of the first capacitor portions is set to be greater than a resonant frequency of the second capacitor portion so that the first capacitor portions contribute to low ESL, an ESR per layer of the second capacitor portion is set to be greater than an ESR per layer of the first capacitor portions so that the second capacitor portion contributes to high ESR. Furthermore, a combined ESR of the first capacitor portions is set to be less than or greater than a combined ESR of the second capacitor portion.

Abstract: The present invention aims to provide an electronic component capable of reducing the occurrence of cracks at the joining portion to a board etc. A capacitor 1 (laminated ceramic capacitor) being one example of the electronic component is provided with an element assembly 10 (ceramic) and a pair of external electrodes 20 formed on both side surfaces of the element assembly 10. In the element assembly 10, a dielectric layer 12 and an internal electrode 14 are laminated alternately. The external electrode 20 has such constitution that a first electrode layer connected with the internal electrode, a second electrode layer (electroconductive resin layer) including a hardened product of thermohardening resin containing a polyphenol compound having a side chain composed of an aliphatic group, a third electrode layer composed of Ni and a fourth electrode layer composed of Sn are formed in this order from the element assembly side.

Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Abstract: Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO2 layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf1-xLaxO layer on the bottom electrode; and a top electrode on the Hf1-xLaxO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf1-xLaxO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf1-xLaxO layer and removing impurities existed within the Hf1-xLaxO layer; nitriding a surface of the crystallized Hf1-xLaxO layer; and forming the top electrode being made of polysilicon doped with impurities on the nitrided surface of the crystallized Hf1-xLaxO layer.

Abstract: A multilayer capacitor has a capacitor element, inner electrodes arranged within the capacitor element, and first to fourth terminal electrodes. Electrode parts of the first to fourth terminal electrodes cover ridges formed between first and third side faces, first and fourth side faces, second and third side faces, and second and fourth side faces. The capacitor element has an element part. The element part is formed such as to overlap the electrode parts when seen in a second and a third directions and keep away from respective areas about the electrode parts when seen in a first direction.

Abstract: A polymeric dielectric composition is disclosed, having a paraelectric filler with a dielectric constant between 50 and 150. Such compositions are well suited for electronic circuitry, such as, multilayer printed circuits, flexible circuits, semiconductor packaging and buried film capacitors.

Abstract: One embodiment includes a method that includes positioning a first substantially planar electrode including material defining a first aperture into a capacitor stack in alignment with a second substantially planar electrode such that a first non-aperture portion of the second substantially planar electrode at least partially overlays the first aperture and joining the first substantially planar electrode to the second substantially planar electrode proximal the material defining the first aperture and the first non-aperture portion of the second substantially planar electrode.

Abstract: An embodiment of the present invention provides a method, comprising reducing the losses due to electro-mechanical coupling and improving Q in a multilayered capacitor by placing a first capacitor layer adjacent at least one additional capacitor layer and sharing a common electrode in between the two such that the acoustic vibration of the first layer is coupled to an anti-phase acoustic vibration of the at least one additional layer.

Abstract: A high voltage capacitor design is provided that provides improved performance. The high voltage capacitor includes a stack of mechanically joined capacitor cells, which in one variant utilize a separator formed of two layers of paper. In one version, the high voltage capacitor may be used as a capacitative voltage divider.

Abstract: A high voltage capacitor design is provided that provides improved performance. The high voltage capacitor includes a stack of mechanically joined capacitor cells, which in one variant utilize a separator formed of two layers of paper. In one version, the high voltage capacitor may be used as a capacitative voltage divider.

Abstract: In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portions of the polysilicon film for a first amount of time; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that defines the patterned polysilicon layer; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon layer have about the same thickness and form a planar surface.

Abstract: The present invention has a configuration which allows manufacturing a capacitor comprising a first electrode layer, conductive first convex sections layered on a surface of the first electrode layer, a first dielectric layer formed on a surface of the first convex sections and a surface of the first electrode layer, and a second electrode layer formed so as to be superimposed on the first convex sections and the first electrode layer via the first dielectric layer.

Abstract: Disclosed is an ultracapacitor having electrodes containing mineral microtubules, an electrolyte between the electrodes, and a separator in the electrolyte to provide electrical insulation between the electrodes, while allowing ion flow within the electrolyte. The electrodes may be formed from a paste containing microtubules, a conductive polymer containing mineral microtubules, or an aerogel containing the mineral microtubules. The mineral microtubules may be filled with carbon, a pseudocapacitance material, or a magnetoresistive material. The mineral microtubules may also be coated with a photoconductive material.

Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).

Abstract: A multilayer electronic component has: a first capacitive electrode layer of a rectangular shape on which four capacitive electrode portions are formed at four comers; and a ground electrode layer which is laid on the first capacitive electrode layer and on which a ground electrode is formed so as to be arranged as superposed over the four capacitive electrode portions. The four capacitive electrode portions are equidistant from a first facing edge pair of the first capacitive electrode layer and equidistant from a second facing edge pair different from the first edge pair. This configuration equalizes distributions of electric fields established between the respective capacitive electrode portions and the ground electrode, which realizes uniformization of the capacitances in the four respective capacitive electrode portions.

Abstract: In a multilayer capacitor including a capacitor body, first capacitor portions and a second capacitor portion are arranged in the direction of lamination. While a resonant frequency of the first capacitor portions is set to be greater than a resonant frequency of the second capacitor portion so that the first capacitor portions contribute to low impedance, an ESR per layer of the second capacitor portion is set to be greater than an ESR per layer of the first capacitor portions so that the second capacitor portion contributes to high ESR. Further, a combined ESR of the first capacitor portions is set to be substantially equal to a combined ESR of the second capacitor portion.

Abstract: This invention provides novel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.

Abstract: A highly reliable multilayer ceramic electronic device is obtained while preventing crack defects generated in a ceramic laminate by application of a heat shock in a mounting step or the like. The multilayer ceramic electronic device is constructed such that the average value of continuities of internal electrodes located in two regions (f) is lower by 5% to 20% inclusive than the average value of continuities of internal electrodes located in the central portion in a lamination direction. The two regions (f) are the regions from the topmost internal electrode and the bottommost internal electrode located in the lamination direction to the inside, respectively, within 10% of the distance (d) therebetween. Continuity is defined by (X?Y)/X in which X is the length of a cross section of an internal electrode in one direction and Y indicates the sum of gaps (g) formed by pores in the cross section of the internal electrode.