Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of first and second polarity electrode layers. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups and thin-film plated deposition is formed thereon by electroless and/or electrolytic plating techniques. A solder dam layer is provided over a given component surface and formed to expose predetermined areas where solder barrier and flash materials may be deposited before attaching solder preforms. Some embodiments include plated terminations substantially covering selected component surfaces to facilitate with heat dissipation and signal isolation for the electronic components.

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract: A multilayer electronic component having a ceramic substrate and a resin layer mounted on a mounting substrate. Recess portions are formed at an outside-facing major surface side of the resin layer. In the resin layer, columnar conductors are disposed so that axis line directions thereof are aligned in a thickness direction of the resin layer. End portions of the columnar conductors are located inside the recess portions further from opening faces thereof and have end surfaces exposed in the recess portions. When a multilayer electronic component is mounted on a mounting substrate, solder is provided on the end surfaces of the columnar conductors in the recess portions. The thickness of solder used in the above mounting does not interfere with a reduction in size and height of an electronic device that includes the above multilayer electronic component.

Abstract: A mixed dispersant which can improve the efficiency of dispersing metal powder by effectively adsorbing on the surface of the metal powder and preventing aggregation thereof, and a paste composition and a dispersion method using the same are provided. A multilayer ceramic capacitor (MLCC) is also provided. The mixed dispersant includes a basic dispersant and an acidic dispersant in accordance with the acidity and basicity of nickel metal powder and thus can achieve an optimal dispersion efficiency. An improvement in the dispersion efficiency as such can consequently suppress aggregation of the nickel metal powder during the preparation of a conductive paste composition containing a nickel metal powder, and therefore a larger amount of the nickel metal powder can be used in the paste composition. The increased amount of nickel metal powder allows producing an internal nickel electrode having improved electric properties and mechanical properties during the production of MLCCs.

Abstract: The present invention relates to a capacitor device (500), an electronic circuit comprising a capacitor device, to an electronic component, and to a method of forming a capacitor device. In the capacitor device of the invention, a current-path region (530) extends from one of two trench capacitor electrodes to a respective contact structure (520). The current-path region of the capacitor device of the invention is obtainable by thinning the substrate from an original substrate thickness down to reduced substrate thickness either in a lateral substrate portion containing the capacitor region or over the complete lateral extension of the substrate before forming the first and second contact structures. The capacitor device of the invention has the advantage of exhibiting a reduced impedance in the current-path region. This reduced impedance implies a low self-inductance and self-resistance that is caused by the current-path region of the capacitor device.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: Systems and methods are provided for fabricating a thin film capacitor involving depositing an electrode layer of conductive material on top of a substrate material, depositing a first layer of ferroelectric material on top of the substrate material using a metal organic deposition or chemical solution deposition process, depositing a second layer of ferroelectric material on top of the first layer using a high temperature sputter process and depositing a metal interconnect layer to provide electric connections to layers of the capacitor.

Abstract: A multi-layer ceramic capacitor includes a plurality of dielectric ceramic layers; internal electrodes formed between the dielectric ceramic layers; and end termination electrodes electrically connected to the internal electrodes, wherein the dielectric ceramic layer is a sintered body constituted of a primary component that, when it is expressed by ABO3+aRe2O3+bMnO, satisfies 1.000?A/B?1.035, 0.05?a?0.75 and 0.25?b?2.0; and a subcomponent that includes at least one kind of B, Li or S in the range of 0.16 to 1.6 parts by mass in total in terms of B2O3, Li2O and SiO2; and the internal electrode is constituted of Cu or a Cu alloy.

Abstract: A monolithic or essentially monolithic single layer capacitor with high structural strength and capacitance, a printed circuit board having the capacitor mounted thereon, and a method of making. Sheets of green-state ceramic dielectric material and glass/metal composite material are laminated together, diced into individual chips, and fired to sinter the glass and the ceramic together. The composite material contains an amount of metal sufficient to render the composite conductive whereby the composite may be used for one or both electrodes and for mounting the capacitor to the printed circuit board. Vertically-oriented surface mountable capacitors and hybrid capacitors are provided.

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract: A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx.

Abstract: A capacitor and a method of manufacturing the capacitor are disclosed. The capacitor may include a board, a polymer layer formed on one side of the board, a circuit pattern selectively formed over the polymer layer, and a titania nanosheet corresponding with the circuit pattern. Embodiments of the invention can provide flatness in the board, and allows the copper of the board to maintain its functionality as an electrode while increasing the adhesion to the titania nanosheet. The titania nanosheet may thus be implemented on a patterned board in a desired shape, number of layers, and thickness.

Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).

Abstract: A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.

Abstract: A capacitor is provided having a tough surface portion which prevents cracking that tends to occur when the capacitor is built-in or surface-mounted on a wiring board. A ceramic sintered body of the capacitor includes a capacitor forming layer portion, a cover layer portion and an interlayer portion. The capacitor forming layer portion has a laminated structure wherein ceramic dielectric layers and inner electrodes connected to a peripheral portion of capacitor via conductors, are alternately laminated. The cover layer portion is exposed at a surface portion of the ceramic body and has a laminated structure wherein ceramic dielectric layers and dummy electrodes not connected to the capacitor via conductors, are alternately laminated.

Abstract: A laminated ceramic capacitor has a high breakdown voltage and excellent withstand-voltage performance, and prevents cracks generated during firing even when the number of lamination layers constituted by ceramic layers and inner electrode layers is increased. The laminated ceramic capacitor includes capacitance forming layers in which ceramic dielectric layers and capacitance-forming inner electrode layers are laminated, and a stress relieving layer. The stress relieving layer is disposed between the capacitance forming layers. In the stress relieving layer, ceramic dielectric layers, dummy inner electrode layers (split electrodes) that do not contribute to the formation of electrostatic capacitance, and capacitance-formation-preventing inner electrode layers that prevent capacitance from being formed between the capacitance-forming inner electrode layers and the dummy inner electrode layers are laminated. The thickness of the stress relieving layer is in the range of about 100 ?m to about 300 ?m inclusive.

Abstract: This electronic component comprises a substrate; and a capacitor part provided on the substrate, the capacitor part includes a first electrode part provided on the substrate; a dielectric film covering the first electrode part; an insulating film that contacts the dielectric film and has an opening part; and a second electrode part that contacts an inner wall surface of the opening part of the insulating film and a surface of the dielectric film, and when the angle between a first interface between the dielectric film and the insulating film, and a second interface between the insulating film and the second electrode part is ?, ? is not more than 22°.

Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.

Abstract: A capacitive structure and technique for allowing near-instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates is presented. Methods for introducing resistive loss, dielectric loss, magnetic loss, and/or radiation loss in a signal absorption ring implemented around a non-absorptive area of one or more conductive layers of an integrated circuit structure to dampen laterally flowing Electro-Magnetic (EM) waves between electrically adjacent conductive layers of the device are also presented.

Abstract: A multilayered high performance capacitor formed of two or more conductors with a dielectric layer and one or more a dielectric-conductor interface layer sandwiched in between the conductors. The capacitor may be fabricated using many thin layers, at the nano level, providing a nanocapacitor. The capacitor may employ an interleaved structured where numerous conductor layers are interleaved with other conductor layers. The dielectric layers may be multilayered or a single layer and may consist of materials with high dielectric constants ranging from 800 to over 1 million, including materials in the perovskite-oxide family. The capacitor can be shaped, sized and the appropriate materials selected to obtain breakdown voltages within the range of 0.1 to over 11 MV/cm and to obtain specific energies and energy densities equivalent to or exceeding the power characteristics of known capacitors, fuel cells, and batteries.

Abstract: A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the carbon nanotubes formed on opposed substrates. In some embodiments, the carbon nanotubes may be covered by a dielectric which may be adhered by functionalizing the carbon nanotubes.

Abstract: An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted.

Abstract: A multilayer capacitor comprises a capacitor body, a first connecting conductor arranged on a first side face of the capacitor body, first and second terminal electrodes, and a first insulator arranged between the first connecting conductor and first terminal electrode. The capacitor body has a plurality of laminated insulator layers and a plurality of first and second inner electrodes. The second terminal electrode is connected to the second inner electrode. Each of the first inner electrodes has a first lead portion exposing an end to the first side face. At least one of the first inner electrodes also has a second lead portion whose end is exposed to the first side face. The first connecting conductor continuously covers all the ends of the first lead portions of the first inner electrodes and mechanically connects with the ends of the first lead portions.

Abstract: A storage capacitor having a scattering effect is positioned in a substrate for use in a thin film transistor array loop. The storage capacitor is characterized by having a rough layer overlapped by a medium layer and a passivation layer. The storage capacitor further has a reflective layer with high reflectivity so as to provide the storage capacitor with the scattering effect toward an external light source. A method of manufacturing the storage capacitor by two photolithography processes is also shown.

Abstract: A multilayer capacitor array comprises a multilayer body, and first to fourth terminal conductors and first and second outer connecting conductors formed on the multilayer body. The multilayer body includes a first electrode group having a plurality of first and second inner electrodes, and a second electrode group having a plurality of third and fourth inner electrodes. The first to fourth inner electrodes are connected to the first to fourth terminal conductors, respectively. In the plurality of first inner electrodes, at least one first inner electrode whose number is smaller than the total number of the first inner electrodes by at least one is connected to the first terminal conductor. In the plurality of second inner electrodes, at least one second inner electrode whose number is smaller than the total number of the second inner electrodes by at least one is connected to the second terminal conductor.

Abstract: A thin-film capacitor and a method for making the thin-film capacitor having a structure that can prevent vertical stress acting on outer connecting terminals, such as bumps, from concentrating on electrode layers, and capable of easily increasing the equivalent series resistance to a desired value. The thin-film capacitor includes a substrate, a capacitor unit disposed above the substrate and composed of at least one dielectric thin film and two electrode layers, a protective layer covering at least part of the capacitor unit, a lead conductor electrically connected to one of the electrode layers of the capacitor unit, and a bump disposed above the lead conductor. The lead conductor includes a connecting part disposed in an opening in the protective layer and electrically connected to one of the electrode layers of the capacitor unit, and a wiring part extending over the protective layer. The bump is disposed above the wiring part.

Abstract: There is disclosed a thin film capacitor and the like capable of suppressing fluctuations of a capacity, increasing a VBD, and accordingly improving a device characteristic and reliability of a product. In electronic components 1 to 4, a capacitor 11 is formed on a flat substrate 51 as a base material including a planarization layer 52 formed on the surface thereof. The capacitor 11 has a structure in which a lower conductor 21 constituted of an underlayer conductor 21a and a conductor 21b, a dielectric film 31 made of alumina or the like, a resin layer J1 mainly formed of a novolak resin or the like, a resin layer J2 mainly formed of a polyimide resin or the like, and an upper conductor 25 constituted of an underlayer conductor 25a and a conductor 25b are formed on the planarization layer 52 of the substrate 51. The resin layer J1 has an opening K1 above the lower conductor 21, and the resin layer J2 is provided with an opening K2 opened more widely than the opening K1.

Abstract: In one aspect of the invention, a thin layer capacitor element has a capacitor with a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, and a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.

Abstract: A flat type capacitor-use polypropylene film having a Ad(thickness determined by micrometer method—thickness determined by weighing method) of 0.05-0.2 ?m and a lengthwise shrinkage dimensional change rate of 3% or less, or a flat type capacitor-use polypropylene film having a ?d of 0.1-0.3 ?m and a lengthwise F5 value of 50 MPa or more, and a flat type capacitor using it. A film excellent in handling ability in a capacitor element winding process is obtained, and a small, a large-capacity flat type capacitor excellent in withstand voltage characteristics such as self-recovering property, and used suitably under a high rated voltage, is obtained.

Abstract: Disclosed is an ultracapacitor having electrodes containing mineral microtubules, an electrolyte between the electrodes, and a separator in the electrolyte to provide electrical insulation between the electrodes, while allowing ion flow within the electrolyte. The electrodes may be formed from a paste containing microtubules, a conductive polymer containing mineral microtubules, or an aerogel containing the mineral microtubles. The mineral microtubules may be filed with carbon, a pseudocapacitance material, or a magnetoresistive material. The mineral microtubules may also be coated with a photoconductive material.

Abstract: A dielectric layer of a capacitor includes a first dielectric layer, a second dielectric layer formed over the first dielectric layer, the second dielectric layer having a dielectric constant lower than that of the first dielectric layer, and a third dielectric layer formed over the second dielectric layer, the third dielectric layer having a dielectric constant higher that of than the second dielectric layer, wherein the third dielectric layer has a greater thickness than each of the first and second dielectric layers.

Abstract: The present invention is intended to provide a laminated electronic component having a configuration in which the number of extraction electrodes is reduced to realize a high ESR, the adhesion of a terminal electrode with respect to an ECA is increased and a short-circuit defect between an internal electrode and a dummy electrode can be prevented. An electrode layer in the ECA includes the internal electrode, the extraction electrode and the dummy electrode. One end of the extraction electrode is connected with the internal electrode in the same layer, and the other end of the same is led onto a side surface of the ECA 1 to be connected with the terminal electrode. This is also applied to other extraction electrodes.

Abstract: A decoupling module for decoupling high-frequency signals from a voltage supply line, the module including a plurality of parallel-connected capacitors (K1, K2, . . . ), which each have a capacitance (C1, C2, . . . ), and are characterized in that at least one of the capacitors (K1) has an inductance (L1) which is selected dependent on the capacitance (C1) of the capacitor (K1) and the voltage supply line inductance (L12), so that a resonance is generated which compensates the self-resonance of the system from at least a further capacitor (K2, . . . ) and the entire voltage supply line (S). L12 is the inductance of the voltage supply line running between the parallel-connected capacitors.

Abstract: A green sheet coating material includes ceramic powder and a binder resin containing a butyral based resin as the main component, which furthermore includes a xylene based resin as a tackifier. The xylene based resin is included in a range of 1.0 wt % or less, more preferably 0.1 or more and 1.0 wt % or less, and particularly preferably more than 0.1 and 1.0 wt % or less with respect to 100 parts by weight of ceramic powder.

Abstract: The monolithic ceramic electronic component includes a first external electrode 5, a second external electrode 6, and a ceramic sintered compact 4 including internal electrodes 2 and 3, the first and second external electrodes 5 and 6 being disposed on both end faces 4a and 4b of the ceramic sintered compact 4. The first and second external electrodes 5 and 6 have a multilayer structure in which sintered electrode layers 5a and 6a, intermediate electroplated layers 5b and 6b, and plated layers 5c and 6c are arranged in that order. Exposed surface regions 7a of insulating oxides 7 are exposed from the outer faces of the sintered electrode layers 5a and 6a, the oxides 7 being derived from a glass frit contained in the sintered electrode layers. Metals 8 are deposited on the exposed surface regions 7a and the intermediate electroplated layers 5b and 6b are then formed by electroplating.

Abstract: The present invention is directed to a power semiconductor device in which a control circuit controls a power switching element, comprising: a semiconductor substrate having a front surface and a back surface; a capacitor disposed on the front surface side of the semiconductor substrate and being comprised of a stacked structure of a first conductive layer, an insulation film and a second conductive layer; and a bonding pad which is disposed on the front surface side to the capacitor and to which a bonding wire being connected, wherein the bonding pad are arranged overlapping the capacitor.

Abstract: Crystal grains mainly composed of barium titanate have a mean grain size of not more than 0.2 ?m. The volume per unit cell V that is represented by a product of lattice constant (a, b, c) figured out from the X-ray diffraction pattern of the crystal grains is not more than 0.0643 nm3. Thereby, a dielectric ceramics having high relative dielectric constant can be obtained. A multilayer ceramic capacitor comprises a capacitor body and an external electrode that is formed at both ends of the capacitor body. The capacitor body comprises dielectric layers composed of the dielectric ceramics, and internal electrode layers. The dielectric layers and the internal electrode layers are alternately laminated.

Abstract: A chip-type electronic component includes a ceramic chip body incorporating an element, an external electrode formed on a side surface of the chip body, a conductive elastic resin film which is larger in width than the external electrode and formed to cover the external electrode and extend onto part of a mount surface of the chip body, and a metal plating film for soldering formed on the conductive elastic resin film.

Abstract: A green sheet coating material including ceramic powder, a binder resin including a butyral based resin as the main component, and a solvent. The solvent includes a first solvent medium having a relatively low boiling point, wherein said binder resin is easy to be dissolved, and a second solvent medium having a relatively high boiling point. The boiling point of the second solvent medium is in a range of 130 to 230° C. The second solvent medium is included by 5 to 70 wt %, and more preferably 8 to 52 wt % with respect to 100 wt % of the entire solvent.

Abstract: An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.

Abstract: A capacitor has stacking capacitor elements, each of which contains a conductor plate, a first band being an insulator and disposed around the plate, a second band being an insulator and disposed around the plate so as to be substantially parallel to the first band, an insulating coating covering a region sandwiched between the first and second bands, a cathode layer formed on the insulating coating, and an anode containing the plate and formed on an outer side of at least one of the first and second bands. The cathode layers are elctrically connected to each other through paths each connecting in series the facing two cathode layers of the adjacent two elements and path(s) connecting in parallel the cathode layers to each other, and the anodes are electrically connected to each other through path(s) connecting in parallel the anodes to each other.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Abstract: A composite distributed dielectric structure includes one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further formed around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers.

Abstract: The present invention provides the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.

Abstract: An on-chip capacitor having a plurality of capacitor layers. Each capacitor layer includes a pair of frames. A first frame of the pair is electrically connected to first frames on each other capacitor layer and a second frame of the pair is electrically connected to second frames on each other capacitor layer. A plurality of tines project from each frame within the respective capacitor layer. The tines from each frame mesh so as to form an array of sequentially alternating tines from each frame to provide a layer capacitance within the capacitor layer. The multi-layer capacitor further includes a plurality of projections from the tines. The projections extend between frames of adjacent capacitor layers so as to provide an interstitial capacitance between the capacitor layers. The total capacitance of the on-chip capacitor is the sum of each layer capacitance and each interstitial capacitance.

Abstract: A reduction resistant lead-free and cadmium-free glass composition that is particularly suitable for use in conductive ink applications is disclosed. The invention includes a capacitor, which includes a conductive copper termination. The copper termination is made by firing an ink including a glass component, which may include ZnO, provided the amount does not exceed about 65 mole %; B2O3, provided the amount does not exceed about 61 mole %; and, SiO2, provided the amount does not exceed about 63 mole %. The molar ratio of B2O3 to SiO2 is from about 0.05 to about 3.

Abstract: A multilayer capacitor 1 has a laminated body 20 configured by laminating a plurality of dielectric substrates 2 each having a plurality of internal electrodes 3 and 5 formed on its main surface and a capacitance component is generated between the facing internal electrodes 3 and 5. The dielectric constant of the dielectric substrate located at a central portion of a lamination direction of the laminated body 20 is lower than that of the dielectric substrate 2 located at the edge of the lamination direction.

Abstract: Disclosed is a method of forming individual thin-film capacitors for embedding inside printed wiring boards or organic semiconductor package substrates, which includes removal of selective portions of the capacitor by sandblasting or other means so that the ceramic dielectric does not come in contact with acid etching solutions.

Abstract: An assembly includes a semiconductor device having surface-connecting terminals, a substrate having surface-connecting pads, and a capacitor having an approximately plate-shaped capacitor main body having a first surface on which the semiconductor device is mounted and a second surface at which the capacitor main body is mounted on the substrate and a plurality of electrically conductive vias penetrating the capacitor main body between the first and second surfaces and connected to the surface-connecting terminals and the surface-connecting pads.

Abstract: A capacitor structure includes a first electrode structure, a second electrode structure, and a capacitor dielectric. The first electrode structure includes a plurality of first conductive plates vertically disposed and parallel to one another. The second electrode structure includes a plurality of second conductive plates disposed alternately with the first conductive plates. Each first conductive plate includes a plurality of first conductive bars electrically coupled to the first conductive bar stacked thereon with at least a first conductive via. Each second conductive plate includes a plurality of second conductive bars electrically coupled to the second conductive bar stacked thereon with at least a second conductive via.