Abstract: Methods for manufacturing a light source circuit board having one or more light emitting components that include providing at least one circuit component on a light source circuit board, wherein the at least one circuit component has an electrical circuit constant that specifies one or more performance parameters for the light source. The methods also include measuring the electrical circuit constant of the at least one circuit component. The methods also include identifying one or more performance parameters for the light source based on the measured electrical constant.

Abstract: In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes.

Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.

Abstract: A printed circuit board (PCB) having a decoupling capacitor includes: a PCB including a power supply layer, ground layer, and first decoupling capacitor; a package mounted at a surface of the PCB, wherein the first decoupling capacitor is embedded in a via hole of the PCB, and a first electrode of the first decoupling capacitor is connected to one of power supply pins of the package, and a second electrode of the first decoupling capacitor is connected to the ground layer.

Abstract: A multi-piece substrate includes a unit component having four sides and including multiple wiring boards arrayed in a matrix, and a frame component supporting the unit component such that the frame component is surrounding an outer periphery of the unit component. Each of the wiring boards has a semiconductor element built therein, and the frame component has multiple slit portions formed such that the slit portions are formed along the four sides of the unit component, respectively.

Abstract: Disclosed is a wiring board with a built-in component and a method for manufacturing the same, the wiring board including: a wiring pattern; an electric/electronic component electrically and mechanically connected with a surface of said wiring pattern; and an insulating layer formed on the same surface of said wiring pattern as said electric/electronic component is connected and configured so as to embed said electric/electronic component, said insulating layer having an insulating resin and a reinforcing material included in the insulating resin, wherein the reinforcing material of said insulating layer exists in the insulating resin without reaching a region of said electric/electronic component in a lateral direction, and wherein the insulating resin of said insulating layer reaches said electric/electronic component so as to adhere to said electric/electronic component.

Abstract: An embedded-electronic-device package includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer, a shielding-metal layer and conductive vias. The core layer includes a first surface, a second surface opposite to the second surface and a cavity penetrating the core layer. The electronic device is disposed in the cavity including an inner surface. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers part of the electronic device. The second dielectric layer disposed on the second surface is filled in rest of the cavity, covers rest of the electronic device. The first and second dielectric layers cover the electronic device. The shielding-metal layer covers the inner surface. The conductive vias are respectively disposed in the first and second dielectric layers and extended respectively from outer surfaces of the first and second dielectric layers to the shielding-metal layer.

Abstract: A method of manufacturing a cover structure is provided. A first insulating layer is provided. The first insulating layer has a first surface and a second surface opposite to each other. A second insulating layer is provided. The second insulating layer has a third surface and a fourth surface opposite to each other and an opening passing through the third surface and the fourth surface. A thickness of the second insulating layer is greater than a thickness of the first insulating layer. The first insulating layer and the second insulating layer are laminated to each other, so that the third surface of the second insulating layer connects to the second surface of the first insulating layer. A cavity is defined by the opening of the second insulating layer and the first insulating layer. A metal layer is formed on the cavity.

Abstract: Provided is a component-embedded board. The board includes: a first base including first substrate incorporating a first electric component and first electrode provided on a first face of the substrate and electrically connected to the electric component; a second electronic component fixed on the first face with a first adhesion portion therebetween; a second base including second substrate in which the second electronic component is embedded and second electrode exposed at a first face of the second substrate; a second adhesion portion arranged between the first and second bases; a third base including third substrate and third electrode exposed at a first face of the third substrate; and a third adhesion portion arranged between the second and third bases. The first, second and third electrodes are electrically connected to the second electronic component, and the second electronic component is surrounded, at least, by the first and third adhesion portions.

Abstract: A multilayer circuit substrate has a high frequency switch embedded therein. In the multilayer circuit substrate, a first conductive layer that faces a main surface of the high frequency switch through an insulating layer has circuit patterns formed therein so as to be connected to input/output terminals through via conductors. The first conductive layer has an opening pattern in which a ground conductor is not present in a region that faces the main surface of the high frequency switch and that is outside of the circuit patterns. In a third conductive layer disposed outer side of the first conductive layer with respect to the high frequency switch, a ground conductor is formed at least in a region where the main surface of the high frequency switch is projected in the thickness direction.

Abstract: A fingerprint sensor package includes a flat surface having a dielectric protective coating protecting a sensing element of a fingerprint sensor and an electrically conductive bezel that discharges electrostatic discharge (ESD). Both the protective coating and the bezel can be colored to have desired colors. Accordingly, the flat surface can be colored as desired enhancing the attractiveness for consumer applications. Further, light emitting diodes are integrated into the fingerprint sensor package providing a visual feedback to the user that the user's fingerprint has been successfully sensed. Further, the fingerprint sensor package is formed using a high volume low cost assembly technique.

Abstract: Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a conductor portion having a first portion and a second portion; at least three slots formed in the conductor portion between the first and second portions, each of the at least three slots having a length and at least one tip portion; at least two bridge portions each having a width separating two of the at least three slots and a length coupling the first and second portions; a first contact region disposed relative to the first portion and a second contact region disposed relative to the second portion; and at least one pair of magnetic sensor elements, a first pair of magnetic sensor elements arranged relative to and spaced apart from a first of the at least two bridge portions.

Abstract: An environmental sensitive electronic device package may include a first substrate, a second substrate, an environmental sensitive electronic device, at least one side wall barrier structure, and a filler layer. The first substrate has at least one predetermined flexure area. The second substrate is located above the first substrate. The environmental sensitive electronic device is located on the first substrate and between the first substrate and the second substrate. The side wall barrier structure is located between the first substrate and the second substrate and surrounds the environmental sensitive electronic device. The side wall barrier structure has at least one flexure stress dispersing structure that is located in the predetermined flexure area. The filler layer is located between the first substrate and the second substrate and covers the side wall barrier structure and the environmental sensitive electronic device.

Abstract: A printed wiring board includes a core substrate having opening, an electronic component device accommodated in the opening of the substrate and including inductor and passive components, a wiring structure connecting the inductor and passive components in the electronic device, a filler resin body filling space formed between the substrate and electronic device in the opening of the substrate, a first buildup layer including a first interlayer insulation layer on first surface of the substrate, a first conductive layer on the first insulation layer, and a first via conductor in the first insulation layer, and a second buildup layer including a second interlayer insulation layer on second surface of the substrate on the opposite side of the first surface of the substrate, a second conductive layer on the second insulation layer, and a second via conductor in the second insulation layer.

Abstract: A circuit board having a semiconductor chip embedded therein includes: a core board having opposing first and second surfaces and a through-hole; a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer provided on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as to secure the semiconductor chip in position to the through-hole; and a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads.

Abstract: Representative implementations of devices and techniques provide improved electrical access to components, such as chip dice, for example, disposed within layers of a multi-layer printed circuit board (PCB). One or more insulating layers may be located on either side of a spacer layer containing the components. The insulating layers may have apertures strategically located to provide electrical connectivity between the components and conductive layers of the PCB.

Abstract: A circuit board includes a laminated body including insulation layers made of a flexible material that are stacked on one another. External electrodes are provided on a bottom surface of the laminated body. Ground conductors are provided in the laminated body and that are harder than the insulation layers. The laminated body includes a flexible region and a rigid region that is adjacent to the flexible region when viewed in plan from a z-axis direction. The rigid region is defined by the ground conductors when viewed in plan from the z-axis direction. The external electrodes are provided within the flexible region when viewed in plan from the z-axis direction.

Abstract: In a manufacturing method of a package carrier, a substrate having an upper surface, a lower surface, and an opening communicating the two surfaces is provided. An electronic device is disposed inside the opening. A first insulation layer and a superimposed first metal layer are laminated on the upper surface; a second insulation layer and a superimposed second metal layer are laminated on the lower surface. The opening is filled with the first and second insulation layers. First blind holes, second blind holes, and a heat-dissipation channel are formed. A third metal layer is formed on the first and second blind holes and an inner wall of the heat-dissipation channel. A heat-conducting device is disposed inside the heat-dissipation channel and fixed into the heat-dissipation channel via an insulation material. The first and second metal layers are patterned to form a first patterned metal layer and a second patterned metal layer.

Abstract: Disclosed herein are a hybrid lamination substrate and a manufacturing method thereof. The hybrid lamination substrate includes: a core layer; at least one first insulating layer that is made of a photosensitive resin material and is formed on an upper portion, a lower portion, or upper and lower portions of the core layer; and at least one second insulating layer that is made of a non-photosensitive resin material and is formed on the upper portion, the lower portion, or the upper and lower portions of the core layer. Further, a package substrate including the same and a manufacturing method of a hybrid lamination substrate are proposed.

Abstract: Manufacturing method and circuit module, which comprises an insulator layer (1) and, inside the insulator layer (1), at least one component (6), which comprises contact areas (7), the material of which contains a first metal. On the surface of the insulator layer (1) are conductors (22), which comprise at least a first layer (12) and a second layer (32), in such a way that at least the second layer (32) contains a second metal. The circuit module comprises contact elements between the contact areas (7) and the conductors (22) for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area (7), an intermediate layer (2), which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer (2) and the contact area (7) is less that the surface area (APAD) of the contact area (7).

Abstract: An improved method for producing a PCB assembly requiring at least two different encapsulants is disclosed. The PCB assembly may have two or more separate regions in which electronic devices are attached. In each region, a unique encapsulant with different mechanical, electrical, physical and or chemical properties is used according to the particular requirements of the electronic devices in that region.

Abstract: A wiring board is configured by stacking one or more conductor wiring layers and one or more insulating resin layers and comprising one or more metal vias configured to penetrate the insulating resin layer, wherein the boundary surface between the metal via and the insulating resin layer has a concavo-convex boundary cross-section structure in which the metal via and the insulating resin layer are engaged with each other.

Abstract: A thick-film hybrid circuit structure includes a first thick-film substrate, a second thick-film substrate stacked on the first thick-film substrate and electrically connected to the first thick-film substrate, a chip and an encapsulation body. The second thick-film substrate defines a receiving area, and the chip is fixed in the receiving area and electrically connected to the first thick-film substrate.

Abstract: A wiring substrate is provided with a core substrate including a first main surface, a second main surface, and a through hole. An electronic component including a resin cover is arranged in the through hole. A projection projects from an inner wall of the through hole toward the resin cover of the electronic component. An insulator is filled between the inner wall of the through hole and the electronic component. A first insulation layer covers the electronic component and the first main surface. A second insulation layer covers the electronic component and the second main surface. The resin cover of the electronic component includes an engagement groove formed by the projection and extending along a direction in which the electronic component is fitted into the through hole.

Abstract: Provided is a method for manufacturing a printed circuit board. The method for manufacturing the printed circuit board includes applying an adhesive on a support board, attaching an electronic device on the adhesive, forming an insulation layer for burying the electronic device, separating the insulation layer from the support board, forming a lower insulation layer under the insulation layer, and forming a via connected to terminals of the electronic device in the insulation layer or the lower insulation layer. Thus, since an adhesion material of an adhesion film does not remain between the internal circuit patterns, and the internal circuit patterns are not stripped by an adhesion force of the adhesion film, device reliability may be secured.

Abstract: A wiring board includes: a core layer having a through hole therethrough and comprising a first surface and a second surface opposite to the first surface; a first wiring layer formed on the first surface of the core layer and having a first opening which is communicated with the through hole, wherein an opening area of the first opening is larger than that of the through hole in a plan view; an electronic component disposed in the through hole and the first opening and having a first surface, and a second surface opposite to the first surface, the electronic component further having a pair of terminal on the first surface thereof; and a first resin layer filled in the through hole, the first opening and a gap between the pair of terminals so as to cover the second surface and the side surface of the electronic component.

Abstract: A semiconductor device package having reduced form factor and a method for forming said semiconductor device are disclosed. In an embodiment, an active die is embedded within a cavity in the core layer of the package substrate, wherein an in-situ electromagnetic shield is formed on the sidewalls of the cavity. In another embodiment, a crystal oscillator is at least partially embedded within the core layer of the package substrate. In another embodiment, a package having a component embedded in the core layer is mounted on a PCB, and a crystal oscillator generating a clock frequency for the package is mounted on the PCB. By embedding components within the core or removing components from the package to be mounted directly on the PCB, the x, y, and z dimensions of a package may be reduced. In addition, in-situ electromagnetic shield may reduce EM noise emitted from the active die.

Abstract: There is provided a wiring board including a first stiffener, one face of which is bonded to a circuit board, a second stiffener having a disposition hole in which an electronic component is disposed, and a laminate that is formed by laminating a plurality of insulating layers and a plurality of wiring layers between the other face of the first stiffener and one face of the second stiffener, and includes a terminal connection part that is connected to the wiring layers, positioned in the disposition hole, and connected to a terminal part of the electronic component.

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element.

Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region.

Abstract: Provided is a substrate with a built-in electronic component that can avoid as much as possible the occurrence of malfunctions in the electronic component due to moisture entering, even when an electronic component, provided with a structure in which a terminal pad is present where a hole in the sealing part provided on the main body of a component is located, is built into the substrate. A SAW filter 12 built into a substrate 11 is provided with a structure that has terminal pads 12c to 12e on the bottom of respective holes 12f1 in a sealing part 12f. The lower surfaces of respective conductive vias 11d2 are connected to the upper surfaces of the terminal pads 12c to 12e through the respective holes 12f1 such that a ring-shaped gap CC is formed between outer surfaces of the conductive vias 11d2 and inner surfaces of the holes 12f1. Each ring-shaped gap CC is filled with a part that is integral with a first insulating layer 11c.

Abstract: A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50.

Abstract: A wiring board including a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on one surface of the first substrate and including multiple interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including multiple conductive circuits for being connected to multiple semiconductor elements, and a filler filling the opening portion of the built-up layer such that the interposer is held in the opening portion of the built-up layer. The opening portion of the built-up layer has a tapered portion tapering toward the outermost surface of the built-up layer.

Abstract: An electronic assembly that includes a circuit board having a substrate in which an open space is defined, and a component having a housing and a plurality of leads, the open space being large enough to receive the housing of the component at least partially.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: A multi-layer PCB includes a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-hole formed in the insulating layers so as to allow electrical connection through the contact-holes; a first integrated circuit arranged in a first insulating layer as one of the insulating layers so as to be embedded in the multi-layer PCB, the first integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the first integrated circuit; and a second integrated circuit stacked on a lower surface of the first integrated circuit, the second integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the second integrated circuit.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: An electric element-embedded multilayer substrate, which is a multilayer substrate including an electric element embedded therein and a plurality of base material layers having flexibility, the electric element including a main surface and being embedded in the multilayer substrate to be sandwiched between the base material layers, and a slide member provided between the main surface of the electric element and the base material layer.

Abstract: The present invention provides a three-dimensional System-In-Package (SIP) Package-On-Package (POP) structure comprising a support element formed around a first electronic device. A filling material is filled between the first electronic device and the support element. Signal channels are coupled to first die pads of the first electronic device. Conductive elements form signal connection between the first end of the signal channels and the second die pads of a second electronic device.

Abstract: An electronic component embedded printed circuit board is disclosed. In accordance with an embodiment of the present invention, the electronic component embedded printed circuit board is a printed circuit board in which an electronic component is embedded in a core board, and the electronic component includes a silicon layer and a passivation layer, which is formed on one surface of the silicon layer. Here, a center line of the silicon layer and a center line of the core board are placed on a same line.

Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.

Abstract: A printed wiring board includes an insulating resinous substrate having an aperture unit, a first terminal unit and a second terminal unit consisting of a conductor and formed on top of the resinous substrate, and a fuse unit that electrically couples the first terminal unit and the second terminal unit to each other. At least a part of the fuse unit is disposed over the aperture unit, and in addition, is covered by a porous inorganic covering material having insulating properties.

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract: A suspension board with circuit includes a conductive pattern. The conductive pattern includes a first terminal provided on the front face of the suspension board with circuit and electrically connected with a magnetic head; and a second terminal provided on the back face of the suspension board with circuit and electrically connected with an electronic device.

Abstract: An electronic device is disclosed. The electronic device may include a component made of a ceramic material. The electronic device may also include circuitry configured to transmit signals. The signals may pertain to input received through the component.

Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.