Abstract: An electronic component is provided between at least two wiring boards. An electrode of the electronic component is electrically connected to at least one of the wiring boards. Also, the wiring boards and are electrically connected to each other. Additionally, the gap between the wiring boards and is sealed with a resin. The electronic component built-in substrate is featured in that a bonding pad formed on one of the wiring boards and is electrically connected to an electrode of the electronic component by a bonding wire, and that at least a connection portion between the electrode of the electronic component and the bonding wire is coated with a protection material.

Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

Abstract: A circuit board structure with an embedded semiconductor chip and a fabrication method thereof are provided, including the steps of providing a semiconductor wafer having an active surface with a plurality of electrode pads, a connection metal layer formed on the electrode pads: forming a protective layer on the connection metal layer and the semiconductor wafer, performing a cutting process to form a plurality of semiconductor dies, providing a carrier board having at least one cavity for receiving the semiconductor chip; and forming sequentially on the protective layer covering the semiconductor chip and the carrier board a dielectric layer and a circuit layer electrically connected to the connection metal layer of the semiconductor chip. The present invention is a simple, in process and low in process cost, due to the connection metal layer covered by the protective layer formed on the semiconductor chip protected from oxidation and contamination.

Abstract: An electrical assembly including a substantially planar substrate having at least one recess therein and a plurality of electrical components. The electrical components are positioned in the at least one recess and include a first electrical component and a second electrical component. Each of the electrical components has a body and an electrical connection. The electrical connection of the first electrical component and the electrical connection of the second electrical component are aligned with each other when the body of the first electrical component is in a recess and the body of the second electrical component is in a recess.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: This publication discloses an electronics module comprising an insulating-material layer having two opposite surfaces, and at least one microcircuit embedded to the insulating-material layer. The microcircuit has a first contact surface comprising first contact terminals, from which the microcircuit is electrically connected to first conductor structures in the form of a patterned first conductor layer contained on first surface of the insulating-material layer, and a second contact surface opposite to the first contact surface, in which there is at least one second contact terminal, from which the microcircuit is electrically connected to second conductor structures contained in the form of a patterned second conductor layer on second surface of the insulating-material layer. According to the invention there is provided a local adhesive layer between the component and the first contact surface and first conductor layer, the adhesive layer filling the space between the component and the first conductor layer.

Abstract: According to one embodiment, there is a high frequency circuit having a multi-chip module structure, including a semiconductor substrate set formed with discrete transistors connected in series, a first dielectric substrate set formed with capacitors, and a second dielectric substrate set formed with strip lines.

Abstract: Organic laminate stack ups are disclosed for a variety of applications, including high frequency RF applications. One or more inner core layers may be disposed between outer layers along with bondply or prepreg layers as needed. Discrete devices, including surface mount components and flip chips, may be embedded within the organic laminate stack up structures. The embedding of the discrete devices, which may be active or passive devices, may be in the form of a layer of bondply or prepreg encapsulating the discrete devices. In addition or in the alternative, cavities may be formed in at least the outer layers for housing discrete devices, which include surface mount components, flip chips, and wire bonded integrated circuits. A variety of caps may be utilized to seal the cavities. Further, shielding may be provided for the organic laminate stack up structure, including through a wall of vias or a plated trench cut along at least one side of the stack up structure.

Abstract: In a COF of an embodiment of the present invention, the smaller distance to edges of a heat-releasing member an area of the heat-releasing member has, the larger openings the area has. Accordingly, a volume per area (an area per length) of the heat-releasing member decreases toward the edges. The arrangement improves flexibility of the COF. This prevents a stress caused by bending the COF from concentrating at the edges. This makes it possible to prevent a line on an insulating film from being broken. Also, it becomes possible to prevent an anisotropic conductive resin from coming off which is used to bond the COF with a display panel in providing the COF in a display apparatus.

Abstract: Printed circuit boards are provided with embedded components. The embedded components may be mounted within recesses in the surface of a printed circuit board substrate. The printed circuit board substrate may have grooves and buried channels in which wires may be mounted. Recesses may be provided with solder pads to which the wires may be soldered or attached with conductive adhesive. An integrated switch may be provided in an opening within a printed circuit board substrate. The integrated switch may have a dome switch member that is mounted within the opening. A cover member for the switch may be formed from a flexible layer that covers the dome switch member. Terminals for the integrated switch may be formed from conductive structures in an interior printed circuit board layer. Interconnects may be used to electrically connect embedded components such as switches, integrated circuits, solder pads for wires, and other devices.

Abstract: Disclosed is an embedded printed circuit board, in which electronic devices having different thicknesses can be embedded together, thus achieving highly dense electronic devices, and when electronic devices having considerably different thicknesses are embedded, two electronic devices which are comparatively thinner can be embedded in a perpendicular direction, thus reducing an embedding area and suppressing warping of the printed circuit board, and an insulating member the thickness of which is variably adjusted is interposed between base substrates, so that spaces between the electronic devices are completely filled therewith, thus solving the problem of void defects, resulting in reliable printed circuit boards, and, when a base substrate includes a core made of metal, the printed circuit board can less warp. Also a method of manufacturing the embedded printed circuit board is provided.

Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are formed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.

Abstract: Disclosed are any electronic system or module which includes embedded actives and discrete passives, and methods for use in fabricating packages containing embedded active devices and/or discrete passive devices. Exemplary apparatus comprises a plurality of build-up layers defining circuit interconnections and that comprise one or more thin film type of embedded passive devices, at least a cavity formed in the build-up layers, and at least an active device and/or at least a discrete passive device disposed in the cavity and electrically connected to the circuit interconnections of the build-up layers. A stiffener may be coupled to an exposed (back) surface of the active device and to an adjacent surface of the build-up layers. The build-up layers may be mounted to a core, and the core may be attached to a printed circuit board. Alternatively, a bottom surface of the build-up layers may be mounted to a printed circuit board without core.

Abstract: A multilayer circuit board includes a first circuit layer, an insulating layer, a second circuit layer, an intermediate frame, an electronic element, and a third circuit layer. The insulating layer is disposed on the first circuit layer, and the second circuit layer is disposed on the insulating layer. The intermediate frame is disposed on the second circuit layer and has an accommodating space. The electronic element is disposed on the second circuit layer, electrically connected to the second circuit layer and located in the accommodating space. The third circuit layer is disposed on the intermediate frame.

Abstract: A wiring board has a core structure having a first surface and a second surface on the opposite side of the first surface of the core structure, a first buildup structure formed on the first surface of the core structure and having insulation layers and conductive layers, and a second buildup structure formed on the second surface of the core structure and having insulation layers, conductive layers and an inductor device. The conductive layers in the second buildup structure include conductive patterns forming the inductor device, and one or more of the conductive patterns forming the inductor device has the thickness which is greater than the thicknesses of the conductive layers in the first buildup structure.

Abstract: A device has a first terminal, second terminal and at least four lateral faces provided with contact areas, of which two respective ones each are mutually opposite. The contact areas of the mutually opposite lateral faces are connected to different ones of the first and second terminals.

Abstract: Disclosed herein is a wiring board including: a shield layer; and n layers (n is an integer of two or more) of inductor wiring formed above the shield layer and forming an inductor; wherein of the n layers of inductor wiring, the inductor wiring closest to the shield layer has a smallest wiring area.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: The invention provides an electronic component and a manufacturing method thereof that: can allow electronic components to be mounted on an external substrate at a higher density than before; can adjust the height (level) of a terminal electrode as required and desired, thereby solving problems that would occur in the inspection of the conventional electronic components; and can also improve the yield in the mounting of electronic components, thereby achieving increased productivity.

Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.

Abstract: An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.

Abstract: An electronic component module includes a circuit substrate including surface mount components mounted thereon, a resin layer embedding the surface mount components, and a conductor layer provided on a surface of the resin layer, wherein a conductive post is provided on the surface mount component, and an external electrode having a ground potential provided on the surface mount component is conductively connected to the conductor layer through the conductive post, whereby the conductor layer defines a shielding layer.

Abstract: In a multi-layer substrate including a core formed with a plurality of holes capable of containing an electronic part, a bottom insulating resin layer formed on a bottom surface of the core, a top insulating resin layer formed on a top surface of the core, a wiring layer selectively formed on an outer layer of the bottom insulating resin layer or top insulating resin layer, and an electronic part contained in the holes, both of the bottom and top insulating resin layers have a structure that is a combination of a resin which is changed to cohesiveness when heated and which undergoes smaller plastic deformation when heated to a higher temperature and an insulating resin layer which has a thickness sufficient to maintain insulation between the electronic part or a conductor of the core and the wiring layer and which inherently undergoes small plastic deformation, so that the electronic part can be securely and sealed in the holes without using a particular adhesive.

Abstract: A method of manufacturing an electronic component built-in substrate, includes the steps of mounting a chip-like electronic component having a connection pad and a metal protection layer formed on a whole of one surface to cover the connection pad, on a wiring substrate to direct the connection pad upward; embedding the electronic component with the insulating layer; processing the insulating layer in a thickness direction to leave the insulating layer in a side of the electronic component and to expose the metal protection layer of the electronic component; and forming an upper wiring layer having an in-chip wiring part which is connected to the connection pad and contacts an upper surface of the electronic component and is constructed by an underlying metal pattern layer formed by patterning the metal protection layer and a conductive pattern layer formed thereon, and an extended wiring part which is connected to the in-chip wiring part to extend onto the insulating layer and is formed by an identical layer

Abstract: A circuit module is mounted with an IC that modulates and demodulates a multicarrier signal. The circuit module has a laminated board, which is provided internally with a plurality of conductive layers laminated having insulating layers in between, and an IC, which is provided with a plurality of ground terminals to be grounded. Of the plurality of conductive layers, a conductive layer provided proximate to the IC configures a ground layer electrically connected to the plurality of ground terminals.

Abstract: A circuit board having a semiconductor chip embedded therein includes: a core board having opposing first and second surfaces and a through-hole; a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer provided on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as to secure the semiconductor chip in position to the through-hole; and a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads.

Abstract: Disclosed herein is a printed circuit board, including: a substrate including an insulation layer in which a cavity is formed; an electronic component mounted in the cavity of the substrate and having connection terminals; an insulation material layer formed on one side of the substrate to bury the electronic component; a first circuit layer formed on the other side of the substrate and including a connection pattern connecting with the connection terminals of the electronic component; and a second circuit layer formed on the insulation material layer. The printed circuit board is advantageous in that it can prevent the warpage thereof and ensure the reliability of electrical connection between an electronic component and a circuit layer by adjusting the thickness, thermal expansion coefficient and elastic modulus of insulation layer or the insulating material.

Abstract: The invention relates to a method and a semifinished product for producing an inlay, in particular for chip cards, stored value cards, identification documents, or the like, having at least two electronic components, all electronic components being arranged in a relative configuration on a carrier substrate to implement a component configuration and the component configuration being arranged in a filler material. Furthermore, the invention relates to a method for producing a card having a semifinished product and a card produced using the semifinished product.

Abstract: According to various aspects of the present disclosure, an apparatus is disclosed that includes a small form factor mobile platform including a system-on-package architecture, the system-on-package architecture arranged as a stack of layers including: a first layer having a first conformable material; a second layer having a second conformable material; a third layer having a third material; and one or more electronic components embedded within the stack of layers, wherein the first conformable material, the second conformable material, or both are configured to allow high frequency signal routing.

Abstract: A circuit substrate includes an electrically conductive layer having electrically conductive patterns formed therein, an insulating layer having a through hole, and a composite layer positioned between the electrically conductive layer and the insulating layer. The through hole is configured for having an electronic component mounted thereon. The composite layer includes a polymer matrix and at least one carbon nanotube bundle embedded in the polymer matrix. One end of the at least one carbon nanotube bundle contacts the electrically conductive patterns, and the other is exposed in the through hole of the insulation layer.

Abstract: A method of forming a stackable treated via package includes coupling interconnection balls to terminals. The interconnection balls are encapsulated in a package body. Via apertures are formed in the package body to expose the interconnection balls. The interconnection balls are treated to form treated interconnection balls comprising treated surfaces. The treated interconnection balls of the stackable treated via package enhance bonding with interconnection balls of a stacked electronic component package thus maximizing yield.

Abstract: In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.

Abstract: The present invention provides devices for controlling a desired output of an output device. These devices include a first conductor, a second conductor having a varying, predetermined spacing from the first conductor, and a third conductor positioned on the actuator mechanism and having a plurality of interconnecting positions between the first conductor and the second conductor. A predetermined one of a plurality of output signals may be produced when the third conductor connects the first conductor and the second conductor to control the desired output of the output device.

Abstract: An electro device embedded printed circuit board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, a printed circuit board embedded with an electro device, in which a pair of electrodes are formed on either end, includes: a core substrate in which a first cavity is formed; a first passive device embedded in the first cavity and being thinner than the core substrate; and a second passive device stacked on an upper side of the first passive device such that the second passive device is embedded in the first cavity. The first passive device and the second passive device are stacked to cross each other.

Abstract: The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

Abstract: A modem, in particular for subsea power line communication, has electronic components on a circuit board, and a metal encapsulation, wherein the encapsulation forms at least two chambers separated by at least one wall, wherein each of the chambers surrounds at least one of the electronic components.

Abstract: A printed circuit board having an embedded chip capacitor includes a first conductive layer; a second conductive layer, placed away from the first conductive layer; a chip capacitor, having a first electrode connected to the first conductive layer through being seated in a cavity formed between the first conductive layer and the second conductive layer; a filled material, filled in a space excluding a space occupied by the chip capacitor in the cavity; and a via, penetrating the filled material and connecting the second conductive layer to the second electrode of the chip capacitor.

Abstract: An electronic device is provided with an improved reliability and a reduced contamination in a functional unit of an exposed element, and a method for manufacturing thereof is also provided. An electronic device includes a light receiving element, a frame member composed of a first resin provided so as to surround a photo acceptor unit of the light receiving element, and an encapsulating resin layer composed of a second resin and filling a periphery of the frame member. The photo acceptor unit of the light receiving element is exposed in a space surrounded by the frame member. The upper surface of the frame member and the upper surface of the encapsulating resin layer form a common plane, or the upper surface of the frame member is higher than the upper surface of the encapsulating resin layer.

Abstract: A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.

Abstract: An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus include an at least one stiffener layer that is integral to the coreless substrate and the stiffener layer is made of overmold material, underfill material, or prepreg material.

Abstract: An electrical assembly having controlled impedance signal traces and a portable electronic device comprising an electrical assembly having controlled impedance signal traces are provided. In accordance with one embodiment, there is provided an electrical assembly, comprising: a chassis for mounting electronic components, the chassis being made from a conductive material and forming a first ground plane; a first dielectric layer overlaying the chassis; a first signal trace overlaying the first dielectric layer; and a second dielectric layer overlaying the first signal trace.

Abstract: A method for fabricating electronic cards includes: A) forming a plurality of card bodies in the form of a thick sheet in which is respectively imbedded a plurality of electronic units or modules; B) printing a plurality of first patterns on a first face of the thick sheet in a printing station in which ink is applied on the first face for making the first patterns; and C) applying a first at least partially transparent coating on each printed first pattern, that adheres to the card body. The method also includes printing a plurality of second patterns on the inner surface of a film forming the first coating. Preferably, the printing of the first patterns is carried out in an offset type station for printing high definition patterns, essentially of the security type. The second patterns define personal data. The printed thick sheet defines an intermediate product.

Abstract: A submount for arranging electronic components on a substrate is provided. The submount comprises a head member and at least one substrate-engaging member protruding from the head member. The head member comprises at least two, from each other isolated, electrically conductive portions, where each electrically conductive portion comprises a component contact, adapted for connection of electronic components thereto, and a substrate contact on arranged on said substrate side, adapted for bringing said electrically conductive portions in contact with a circuitry comprised in said substrate. The submount of the present invention may be used to attach electronic components, such as light-emitting diodes, to a textile substrate, without the need for soldering the electronic component directly on the substrate.

Abstract: Disclosed herein is a printed circuit board. The printed circuit board includes a base substrate including a first region on which a semiconductor chip is mounted and a second region positioned outside the first region, first insulating patterns covering the base substrate and including trenches formed on the second region, and second insulating patterns protruding from the first insulating patterns on the second region. The trench and the second insulating pattern may be used as a structure defining an underfill forming material in a preset shape during the process of forming an underfill.

Abstract: An electronic device includes: an outline configuration including a first surface, a second surface facing opposite from the first surface, and a mounting surface coupled to the first and second surfaces; a first substrate including a first electrode; a second substrate including a second electrode; a resin disposed between the first and second substrates; and an electric element sealed with the resin and having an outline configuration of a polyhedron, the electric element being disposed such that a broadest surface of the polyhedron faces one of the first substrate and the second substrate. The first surface is one surface of the first substrate, the one surface being opposite from another surface of the first substrate on a side adjacent to the resin. The second surface is one surface of the second substrate, the one surface being opposite from another surface of the second substrate on a side adjacent to the resin.

Abstract: A method of creating a layout geometry for a multilayer printed circuit board is described. The method involves identifying a signal trace connected to a connector pin via. A antipad is selected for use in conjunction with the connector pin via, where the antipad is of a size selected to prevent interference with said signal trace.

Abstract: An integrated circuit mounted board includes a printed wiring board and an integrated circuit bare chip mounted on the printed wiring board. The printed wiring board includes a metal base, an insulating member made of an insulating material and disposed on the metal base, and a wiring pattern disposed on the insulating member. The wiring pattern includes an electrode part to which the integrated circuit bare chip is electrically coupled. The insulating member includes an under region being opposite to the electrode part. The metal base includes a metal substrate and a metal portion protruding from the metal substrate. The metal portion is buried in the under region of the insulating member.

Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Abstract: The present invention provides a printed wiring board assembly having active and passive components embedded between the printed wiring board layers and associated fabrication method so as to complete a multilayer printed wiring board to improve the flexibility of circuit layout.

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.