Component Within Printed Circuit Board Patents (Class 361/761)
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Patent number: 8575496Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.Type: GrantFiled: October 7, 2011Date of Patent: November 5, 2013Assignee: Ibiden Co., Ltd.Inventor: Hironori Tanaka
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Publication number: 20130286613Abstract: The invention provides an LCD module, an LCD device, and a backplane. The LCD module includes a backplane, and a circuit board arranged on a back of the backplane. The backplane is provided with a slot into which a circuit board is inserted, and the circuit board are arranged on the slot. In the invention, because the backplane of the LCD module is provided with the slot, the circuit board of the LCD module is fixed in the slot of the backplane by insertion. Thus, a screw is not used for fixing a plurality of fixed points of the circuit boards, thereby improving the assembly efficiency of the circuit board and the LCD modules.Type: ApplicationFiled: May 2, 2012Publication date: October 31, 2013Inventor: Yinhung Chen
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Patent number: 8558636Abstract: A passive equalizer circuit is embedded within a substrate of a package containing an integrated circuit. It is believed that substantial reduction in uneven frequency dependent loss may be achieved for interconnects interconnecting the integrated circuit with other integrated circuits on a printed circuit board. Other aspects are described and claimed.Type: GrantFiled: March 30, 2007Date of Patent: October 15, 2013Assignee: Intel CorporationInventors: Jaemin Shin, Pascal A. Meier, Telesphor Kamgaing, Kemal Aygun
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Patent number: 8559184Abstract: A first wiring substrate has a first wiring substrate main body and a first wiring pattern provided on a first surface of the first wiring substrate main body. A first electronic component is surface-mounted on the first wiring pattern. A second wiring substrate has a second wiring substrate main body and a second wiring pattern provided on a first surface of the second wiring substrate main body. The second wiring substrate is arranged under the first wiring substrate such that the first surface of the first wiring substrate main body opposes to the first surface of the second wiring substrate main body. A second electronic component is surface-mounted on the second wiring pattern, and arranged to oppose to the first electronic component. A resin member seals a space between the first wiring substrate and the second wiring substrate.Type: GrantFiled: December 10, 2009Date of Patent: October 15, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Eiji Takaike
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Publication number: 20130265730Abstract: A photostructurable ceramic is processed using photostructuring process steps for embedding devices within a photostructurable ceramic volume, the devices may include one or more of chemical, mechanical, electronic, electromagnetic, optical, and acoustic devices, all made in part by creating device material within the ceramic or by disposing a device material through surface ports of the ceramic volume, with the devices being interconnected using internal connections and surface interfaces.Type: ApplicationFiled: June 5, 2013Publication date: October 10, 2013Inventor: Henry Helvajian
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Publication number: 20130258623Abstract: A package structure having an embedded electronic element includes: a substrate having two opposite surfaces and a cavity penetrating the two opposite surfaces; at least a metal layer disposed on the sidewall of the cavity and extending to the surfaces of the substrate; an electronic element disposed in the cavity and having a plurality of electrode pads disposed on side surfaces thereof; and a solder material electrically connecting the electrode pads of the electronic element and the metal layer, thereby effectively alleviating the problems of alignment difficulty and high fabrication cost as encountered in the prior art.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: UNIMICRON TECHNOLOGY CORPORATIONInventor: Zhao-Chong Zeng
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Patent number: 8546700Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.Type: GrantFiled: March 8, 2011Date of Patent: October 1, 2013Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
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Patent number: 8546922Abstract: A wiring board including a core substrate made of an insulative material and having a penetrating portion, a first interlayer insulation layer formed on the surface of the core substrate, a first conductive circuit formed on the surface of the first interlayer insulation layer, a first via conductor formed in the first interlayer insulation layer, and an electronic component accommodated in the penetrating portion of the core substrate and including a semiconductor element, a bump body mounted on the semiconductor element, a conductive circuit connected to the bump body, an interlayer resin insulation layer formed on the conductive circuit, and a via conductor formed in the interlayer resin insulation layer. The first via conductor has a tapering direction which is opposite of a tapering direction of the via conductor in the electronic component.Type: GrantFiled: September 28, 2011Date of Patent: October 1, 2013Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Daiki Komatsu, Nobuya Takahashi, Masatoshi Kunieda, Naomi Fujita, Koichi Tsunoda, Minetaka Oyama, Toshimasa Yano
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Publication number: 20130242517Abstract: A component assembly that can be easily built in a main substrate with high accuracy is formed such that a glass transition temperature of a built-in-component layer of an assembly substrate in which multiple capacitors are embedded is higher than a glass transition temperature of a built-in-component layer of a built-in-component substrate. Thus, thermal deformation of the component assembly is prevented when the built-in-component substrate in which the component assembly is built is heated during reflow, for example. The component assembly can thus be highly accurately built in the built-in-component substrate. Moreover, when the component assembly in which the multiple capacitors are embedded is built in the built-in-component substrate, electrode pads of the component assembly in which the multiple capacitors are embedded can be electrically connected to wiring layers of the built-in-component substrate by soldering despite the variation in height among the capacitors.Type: ApplicationFiled: September 14, 2012Publication date: September 19, 2013Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Masanori FUJIDAI, Kazuo HATTORI, Isamu FUJIMOTO
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Publication number: 20130242516Abstract: A thin conductive layer which is to form a conductor pattern (18) is prepared, a mask layer (3) is formed on the conductive layer except a plurality of actual connection spots and at least one dummy connection spot on the conductive layer, actual solder pads (6) and a dummy solder pad (7) are formed, with use of solder, on the actual connection spots and the dummy connection spot, respectively, where the conductive layer is exposed, connection terminals (9) of an electric or electronic component (8) are connected to the actual solder pads (6), an insulating base (16) of resin is formed which is laminated directly on or indirectly via the mask layer (3) on the conductive layer and in which the component (8) is embedded, and part of the conductive layer is removed by using the dummy solder pad (7) as a reference, to form the conductor pattern (18).Type: ApplicationFiled: October 1, 2010Publication date: September 19, 2013Applicant: MEIKO ELECTRONICS CO., LTD.Inventors: Yoshio Imamura, Tohru Matsumoto, Ryoichi Shimizu
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Patent number: 8537553Abstract: In accordance with an embodiment of the present invention, a device includes a circuit board with a thermally conductive core layer and a chip disposed over the circuit board. The device further includes a heat sink disposed over the chip. The thermal conductivity of the heat sink along a first direction is larger than a thermal conductivity along a second direction. The first direction is perpendicular to the second direction. The heat sink is thermally coupled to the thermally conductive core layer.Type: GrantFiled: March 24, 2011Date of Patent: September 17, 2013Assignee: Futurewei Technologies, Inc.Inventors: Anwar Mohammed, Renzhe Zhao
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Patent number: 8525630Abstract: A laminated inductor having a laminate structure constituted by magnetic layers and internal conductive wire-forming layers, wherein the magnetic layer is formed by soft magnetic alloy grains, the internal conductive wire-forming layer has an internal conductive wire and a reverse pattern portion around it, and the reverse pattern portion is formed by soft magnetic alloy grains whose constituent elements are of the same types as those of, and whose average grain size is greater than that of, the soft magnetic alloy grains constituting the magnetic layer.Type: GrantFiled: March 23, 2012Date of Patent: September 3, 2013Assignee: Taiyo Yuden Co., Ltd.Inventors: Tomomi Kobayashi, Hitoshi Matsuura, Takayuki Arai, Masahiro Hachiya, Kenji Otake
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Publication number: 20130223032Abstract: A laminate and method for producing the laminate are provided for contacting at least one electronic component. An insulating layer is laminated between first and second metal layers electrically contacted to each other in at least one contact region. At least one recess in the contact region is generated with at least one embossing and/or bulging in the first metal layer. The distance between the two metal layers is reduced, such that dimensions of the embossing/bulging are sufficient for taking up the electronic component, which is inserted and connected into the embossing/bulging in a conductive manner therein. The electronic component is taken up in the embossing/bulging entirely with respect to its circumference and at least partly with respect to the height (H) of the electronic component. The laminate may be used as a circuit board, sensor, LED lamp, mobile phone component, control, or regulator.Type: ApplicationFiled: October 21, 2011Publication date: August 29, 2013Applicants: OSRAM OPTO SEMICONDUCTORS GMBH, HERAEUS MATERIALS TECHNOLOGY GMBH & CO. KGInventors: Andreas Steffen Klein, Eckhard Ditzel, Frank Krüger, Michael Schumann
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Patent number: 8519270Abstract: A circuit board having a cavity is provided. The circuit board includes a first core layer, a second core layer, and a central dielectric layer. The first core layer includes a core dielectric layer and a core circuit layer, wherein the core circuit layer is disposed on the core dielectric layer. The second core layer is disposed on the first core layer. The central dielectric layer is disposed between the first core layer and the second core layer. The cavity runs through the second core layer and the central dielectric layer and exposes a portion of the core circuit layer.Type: GrantFiled: May 19, 2010Date of Patent: August 27, 2013Assignee: Unimicron Technology Corp.Inventor: Chen-Chuan Chang
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Publication number: 20130215585Abstract: A package includes a main unit having formed therein a through hole that penetrates the package from a first surface to a second surface; and a connection terminal that is provided inside the through hole. The second surface is a bottom surface of the main unit, and has an electric circuit incorporated therein. The connection terminal is electrically connected to the electric circuit incorporated in the main unit, and configured to be contactable by an insertion target that is inserted in the through hole from a side of an inserting direction.Type: ApplicationFiled: November 9, 2010Publication date: August 22, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshiyuki Kusano, Mutsumi Shimazaki
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Patent number: 8505613Abstract: A structure including a die with at least one via within a semiconductor portion of the die, the via being proximate to a hot spot. The via is at least partially filled with a heat-dissipating material and is also capable of absorbing heat from the hot spot.Type: GrantFiled: August 12, 2011Date of Patent: August 13, 2013Assignee: Intel CorporationInventors: Gregory M. Chrysler, James G. Maveety
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Patent number: 8508950Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.Type: GrantFiled: July 23, 2010Date of Patent: August 13, 2013Assignee: Micron Technology, Inc.Inventors: Houfei Chen, Shiyou Zhao
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Publication number: 20130201615Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to an interposer with an encapsulated third layer of components disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can couple signals between the components on the first and second layers.Type: ApplicationFiled: August 22, 2012Publication date: August 8, 2013Applicant: APPLE INC.Inventors: Shawn X. ARNOLD, Douglas P. KIDD, Sean A. MAYO, Scott P. MULLINS, Dennis R. PYPER, Jeffrey M. THOMA, Kenyu TOJIMA
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Publication number: 20130194764Abstract: A wiring board includes a substrate having an opening portion, electronic components positioned in the opening portion of the substrate and including first and second electronic components, and an insulation layer formed over the substrate and the first and second components. The first component has first and second electrodes having side portions on side surfaces of the first component, the second component has first and second electrodes having side portions on side surfaces of the second component, the first electrode of the first component and the first electrode of the second component are set to have substantially the same electric potential, and the first component and the second component are positioned in the opening portion of the substrate such that the side portion of the first electrode of the first component is beside the side portion of the first electrode of the second component.Type: ApplicationFiled: July 31, 2012Publication date: August 1, 2013Applicant: IBIDEN CO., LTD.Inventors: Yukinobu MIKADO, Shunsuke SAKAI, Takashi KARIYA, Toshiki FURUTANI
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Patent number: 8498130Abstract: A solid state drive includes a printed circuit board, at least one memory and a controller. The at least one memory stores data. The at least one memory is embedded in the substrate of the printed circuit board. The controller controls the at least one memory to perform a write operation or a read operation. The controller is also embedded in the substrate of the printed circuit board.Type: GrantFiled: April 6, 2010Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Il-Jong Song
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Patent number: 8492658Abstract: An apparatus comprises a multi-layer printed circuit board having at least three conductor layers, a dielectric material layer between each of the conductor layers, and a laminate capacitor stack arranged transversely through the printed circuit board.Type: GrantFiled: November 16, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Nickolaus J. Gruendler, Bhyrav M. Mutnury, Terence Rodrigues
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Patent number: 8493741Abstract: A Subsea Electronics Module for a well installation, comprising: a housing; at least two printed circuit boards having control circuitry provided thereon; and a communications component for enabling communication between the control printed circuit boards; wherein the module further comprises a communications handling board operatively connected to the printed circuit boards, the communications component being mounted on the communications handling board.Type: GrantFiled: June 5, 2009Date of Patent: July 23, 2013Assignee: Vetco Gray Controls LimitedInventor: Julian R. Davis
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Patent number: 8482930Abstract: An electronic device is disclosed. The electronic device may include a component made of a ceramic material. The electronic device may also include circuitry configured to transmit signals. The signals may pertain to input received through the component.Type: GrantFiled: May 23, 2007Date of Patent: July 9, 2013Assignee: Apple Inc.Inventors: John DiFonzo, Chris Ligtenberg
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Patent number: 8481863Abstract: A substrate includes a storage portion which is defined by a base for mounting a light emitting element and a wall portion standing up on and from the base. A package is structured such that the upper end of the wall portion so formed as to surround the periphery of the storage portion is connected to a cover to thereby seal a light emitting element. A seal structure is composed of an uneven portion formed on the lower surface side surface of the base, a close contact layer formed on the surface of the uneven portion, a power supply layer formed on the close contact layer, and an electrode layer formed on the surface of the power supply layer. The uneven portion includes a first recessed portion formed at a position spaced in the radial direction from the outer periphery of a through electrode or from the inner wall of a through hole, and a second recessed portion formed at a position spaced further outwardly from the first recessed portion.Type: GrantFiled: April 2, 2008Date of Patent: July 9, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Akinori Shiraishi, Kei Murayama, Masahiro Sunohara, Naoyuki Koizumi, Mitsutoshi Higashi
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Patent number: 8481864Abstract: The invention relates to a method for producing a functional assembly as well as a functional assembly. According to the inventive method, at least one first material and a second material which are provided with different properties are applied layer by layer, partially in some parts, so as to create an encapsulation from the first material and a strip conductor structure from the second material, one or several functional units being embedded in the layer structure and being contacted with the strip conductor structure when the materials are applied. The disclosed method makes it possible to carefully structure a unit while offering a great degree of creative freedom.Type: GrantFiled: June 30, 2006Date of Patent: July 9, 2013Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.Inventors: Kathrin Badstübner, Frank Ansorge
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Patent number: 8482929Abstract: A printed circuit board assembly is provided. The assembly includes a chassis, a heatframe coupled to the chassis, a printed circuit board (PCB), a thermal interface material (TIM) coupled between the PCB and the heatframe, and at least one thermal via extending through the PCB and coupled to the TIM, wherein the assembly is configured to transfer heat from the PCB to the chassis through the TIM and the at least one thermal via.Type: GrantFiled: May 17, 2011Date of Patent: July 9, 2013Assignee: General Electric CompanyInventors: David S. Slaton, David McDonald, Jerry L. Wright
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Patent number: 8479375Abstract: A photostructurable ceramic is processed using photostructuring process steps for embedding devices within a photostructurable ceramic volume, the devices may include one or more of chemical, mechanical, electronic, electromagnetic, optical, and acoustic devices, all made in part by creating device material within the ceramic or by disposing a device material through surface ports of the ceramic volume, with the devices being interconnected using internal connections and surface interfaces.Type: GrantFiled: January 13, 2010Date of Patent: July 9, 2013Assignee: The Aerospace CorporationInventor: Henry Helvajian
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Patent number: 8472207Abstract: An electronic device includes a substrate with a circuit layer thereon that has a solder pad. There is a liquid crystal polymer (LCP) solder mask on the substrate that has an aperture aligned with the solder pad. There is a fused seam between the substrate and the LCP solder mask. Solder is in the aperture, and a circuit component is electrically coupled to the solder pad via the solder. A first dielectric layer stack having a first plurality of dielectric layers is on the LCP solder mask and has an aperture aligned with the solder pad. There is a first LCP outer sealing layer on the first dielectric layer stack, and a second dielectric layer stack having a second plurality of dielectric layers on the substrate on a side thereof opposite the LCP solder mask. Further, there is a second LCP outer sealing layer on the second dielectric layer stack.Type: GrantFiled: January 14, 2011Date of Patent: June 25, 2013Assignee: Harris CorporationInventors: Louis Joseph Rendek, Jr., Casey Philip Rodriguez, Steven R. Snyder
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Patent number: 8461458Abstract: A card structure includes a first substrate, a second substrate, and a connector. The first substrate includes a base surface, wherein at least one electronic part region and a terminal region are disposed on the base surface. The second substrate is disposed on the base surface and is coupled to the terminal region of the first substrate. The connector is disposed on the base surface to juxtapose the second substrate. The connector includes a connecting surface, a contact unit, and a plurality of contact regions disposed on the connecting surface and coupled to the contact unit and the terminal region, such that the plurality of contact regions are coupled to the second substrate via the terminal region of the first substrate.Type: GrantFiled: December 6, 2012Date of Patent: June 11, 2013Assignee: Industrial Technology Research InstituteInventors: Chih-Yuan Liu, Chien-Hong Lin, Yuan-Heng Sun
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Patent number: 8461463Abstract: A composite module is obtained which enables high-density mounting of components without increasing its size. A composite module includes a main substrate which is a multilayer circuit board, a sub-substrate mounted on a lower surface of the main substrate, a sealing layer arranged on the lower surface of the main substrate to cover the sub-substrate, the sealing layer defining a mount surface arranged to be mounted on a mount board, and terminal electrodes disposed on the mount surface. The terminal electrodes include at least one first terminal electrode drawn directly from the main substrate and at least one second terminal electrode drawn directly from the sub-substrate.Type: GrantFiled: April 6, 2011Date of Patent: June 11, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Noboru Kato, Jun Sasaki, Katsumi Taniguchi
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Patent number: 8461957Abstract: An article of manufacture having an in-molded resistive and/or shielding element and method of making the same are shown and described. In one disclosed method, a resistive and/or shielding element is printed on a film. The film is formed to a desired shape and put in an injection mold. A molten plastic material is introduced into the injection mold to form a rigid structure that retains the film.Type: GrantFiled: May 16, 2012Date of Patent: June 11, 2013Assignee: Ink-Logix, LLCInventors: Ronald H. Haag, Jeffrey R. Engel, William W. Boddie, Jr.
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Patent number: 8451618Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.Type: GrantFiled: October 28, 2010Date of Patent: May 28, 2013Assignee: Infineon Technologies AGInventors: Josef Boeck, Rudolf Lachner, Maciej Wojnowski, Thorsten Meyer
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Patent number: 8451613Abstract: According to one embodiment, an electronic apparatus includes a housing, a module in the housing, and an electrical interconnection. The housing includes a first portion, a second portion including a step between the first portion and the second potion, and a slope between the first portion and the second portion. The electrical interconnection extends from the first portion to the second portion via the slope and is electrically connected to the module.Type: GrantFiled: June 3, 2011Date of Patent: May 28, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ichioh Murakami, Shuya Takahashi
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Patent number: 8450616Abstract: A circuit board having a removing area is provided. The circuit board includes a first dielectric layer, a first laser resistant structure disposed on the first dielectric layer and located at the periphery of the removing area, a second dielectric layer disposed on the first dielectric layer, a circuit layer disposed on the second dielectric layer, a second laser resistant structure disposed on the second dielectric layer and located at the periphery of the removing area, and a third dielectric layer disposed on the second dielectric layer. The second laser resistant structure is insulated from the circuit layer. There is a gap between the second laser resistant structure and the circuit layer, and the vertical projection of the gap on a first surface overlaps the first laser resistant structure. The third dielectric layer exposes the portion of the circuit layer within the removing area.Type: GrantFiled: April 1, 2010Date of Patent: May 28, 2013Assignee: Unimicron Technology Corp.Inventor: Chen-Chuan Chang
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Patent number: 8446736Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.Type: GrantFiled: May 28, 2008Date of Patent: May 21, 2013Assignee: Panasonic CorporationInventors: Takayuki Kita, Masaaki Katsumata, Tadashi Nakamura, Kota Fukasawa, Kazuhiro Furugoori
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Publication number: 20130119652Abstract: A device comprising a laminate (2) comprising at least two layers (31, 32, 33, 34, 35) and a plurality of electronic components (5, 6, 7, 8) disposed between two layers. At least one of the layers (31, 34) supports conductive tracks (10, 11) arranged to connect electronic components.Type: ApplicationFiled: July 15, 2011Publication date: May 16, 2013Applicant: NOVALIA LTD.Inventor: Kate Stone
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Publication number: 20130121523Abstract: Electric components and methods of manufacture are specified. An electric component comprises a carrier having a recess which penetrates the carrier and also a first chip and external contact area. The first chip is arranged in the recess in the carrier. The external contact area is provided for connecting up the first chip to an external circuit environment.Type: ApplicationFiled: May 16, 2011Publication date: May 16, 2013Applicant: Epcos AGInventor: Wolfgang Pahl
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Publication number: 20130107481Abstract: A multi-piece substrate includes a frame portion, and a unit portion in which multiple wiring boards is arrayed. The frame portion is formed on the periphery of the unit portion, the wiring boards have semiconductor elements built in the wiring boards, respectively, and the frame portion has multiple slits formed such that the slits have openings on the periphery of the frame portion.Type: ApplicationFiled: October 31, 2012Publication date: May 2, 2013Inventors: Keisuke SHIMIZU, Yasuyuki Kurabe
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Patent number: 8420954Abstract: The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.Type: GrantFiled: November 30, 2010Date of Patent: April 16, 2013Assignee: Nan Ya PCB Corp.Inventors: Hsien-Chieh Lin, Tung-Yu Chang
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Patent number: 8418356Abstract: The present invention relates to an embedded printed circuit board and a manufacturing method thereof. The present invention provides an embedded printed circuit board including a substrate in which a cavity is formed in a predetermined portion and a wiring layer is formed in a portion without the cavity; a chip inserted into the cavity and including a plurality of pads; a filler filled between the chip and the cavity to fix the chip; and a connection layer formed between the wiring layer and the pads to connect the wiring layer and the pads to each other. Further, the present invention provides a manufacturing method of the embedded printed circuit board.Type: GrantFiled: June 23, 2008Date of Patent: April 16, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kwang Soo Park, Myung Gun Chong, Dek Gin Yang, Dae Jung Byun
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Patent number: 8422243Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; processing a top edge of the support structure along an outermost periphery thereof, to include a recess for preventing mold bleed, the recess surrounded by the lead finger system; and encapsulating the recess and the electrical interconnect system with an encapsulation material to interlock the encapsulation material.Type: GrantFiled: December 13, 2006Date of Patent: April 16, 2013Assignee: Stats Chippac Ltd.Inventors: Seng Guan Chow, Antonio B. Dimaano, Jr.
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Publication number: 20130088841Abstract: The present invention has an object to provide a substrate with a built-in functional element, including the functional element above a metal plate, in which crosstalk noise between signal wirings can be reduced and higher characteristic impedance matching can be achieved. An aspect of the present invention provides a substrate with a built-in functional element, including: a metal plate that includes a concave portion and serves as a ground; the functional element that is placed in the concave portion and includes an electrode terminal; a first insulating layer that covers the functional element and is placed in contact with the metal plate; a first wiring layer including first signal wiring that is opposite the metal plate with the first insulating layer being interposed therebetween; a second insulating layer that covers the first wiring layer; and a ground layer formed of a ground plane that is opposite the first wiring layer with the second insulating layer being interposed therebetween.Type: ApplicationFiled: January 19, 2011Publication date: April 11, 2013Applicant: NEC CorporationInventors: Daisuke Ohshima, Kentaro Mori, Yoshiki Nakashima, Katsumi Kikuchi, Shintaro Yamamichi
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Patent number: 8411459Abstract: A device includes an interposer including a substrate, and a first through-substrate via (TSV) penetrating through the substrate. A glass substrate is bonded to the interposer through a fusion bonding. The glass substrate includes a second TSV therein and electrically coupled to the first TSV.Type: GrantFiled: July 13, 2010Date of Patent: April 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Chen-Hua Yu, Jing-Cheng Lin
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Patent number: 8411448Abstract: A security protection device includes a cover circuit board, at least one inner wiring layer being included within the cover circuit board. The device also includes a base circuit board, at least one inner wiring layer being included within the base circuit board. The device further includes a security frame between the base circuit board and the cover circuit board, at least one electrically conductive wire being wound and included within the security frame to form at least one winding protection layer around sides of the security frame. The cover circuit board, the security frame, and the base circuit board form an enclosure enclosing a security zone, and the at least one inner wiring layer within the cover circuit board, the at least one inner wiring layer within the base circuit board, and the at least one electrically conductive wire within the security frame are connectable to a security mechanism configured to detect an intrusion into the security zone.Type: GrantFiled: September 3, 2010Date of Patent: April 2, 2013Assignee: PAX Computer Technology, Co., Ltd.Inventors: Shuxian Shi, Hongtao Sun
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Publication number: 20130063854Abstract: A stackable layer is provided for 3-Dimensional multi-layered modular computers. The stackable layer comprises at least one encapsulated chip die. Sets of electrical contacts are provided on each one of the large surfaces of the layer. The encapsulated chip die and the two large opposite surfaces of the layer are substantially parallel.Type: ApplicationFiled: September 6, 2012Publication date: March 14, 2013Inventor: AVIV SOFFER
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Patent number: 8389867Abstract: For the purpose of providing a semiconductor element built-in type multilayered circuit board in which a semiconductor element is closely joined to a recess of an insulating substrate to effectively disperse heat generated from the semiconductor element through the insulating substrate at a working temperature region of the semiconductor element circuit board, to surely conduct an electrical connection of an electronic part such as semiconductor element or the like in a short wiring and to enable the high density mounting of semiconductor elements, miniaturization and increase of working speed, there is proposed a semiconductor element built-in type multilayered circuit board formed by laminating a plurality of semiconductor element built-in type boards each comprising an insulating substrate and a semiconductor element accommodated in a recess formed therein, characterized in that a difference between a linear expansion coefficient of the insulating substrate and a linear expansion coefficient of the semiconType: GrantFiled: September 29, 2006Date of Patent: March 5, 2013Assignees: Ibiden Co., Ltd., National University Corporation Tohoku UniversityInventors: Ryo Enomoto, Tadahiro Ohmi, Akihiro Morimoto
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Patent number: 8385028Abstract: A galvanic isolator having a split circuit element, a polymeric substrate, a transmitter and receiver is disclosed. The split circuit element has first and second portions, the first portion being disposed on a first surface of the substrate and the second portion being disposed a second surface of the substrate. The transmitter receives an input signal and couples a signal derived from the input signal to the first portion. The receiver is connected to the second portion of the circuit element and generates an output signal that is coupled to an external circuit. The galvanic isolator can be economically fabricated on conventional printed circuit board substrates and flexible circuit substrates.Type: GrantFiled: March 25, 2010Date of Patent: February 26, 2013Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Julie E. Fouquet, Gary R. Trott
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Patent number: 8381394Abstract: A circuit board has an embedded electronic component such as an integrated circuit chip with a wafer level chip size package. A via hole extends through the electronic component. Another via hole extends through the substrate or prepreg on which the electronic component is mounted inside the circuit board. Conductors in the via holes enable a terminal on the surface of the electronic component to be electrically connected to a wiring pattern or another electronic component on the opposite side of the substrate or prepreg. Routing the connection through the electronic component itself saves space and reduces the length of the connection.Type: GrantFiled: June 23, 2011Date of Patent: February 26, 2013Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshinori Shizuno
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Patent number: 8375576Abstract: A method for manufacturing a wafer scale heat slug system includes: dicing an integrated circuit from a semiconductor wafer; forming a heat slug blank equivalent in size to the semiconductor wafer; dicing the heat slug blank to produce a heat slug equivalent in size to the integrated circuit; attaching the integrated circuit to a substrate; attaching the heat slug to the integrated circuit; and encapsulating the integrated circuit.Type: GrantFiled: June 15, 2011Date of Patent: February 19, 2013Assignee: STATS Chippac Ltd.Inventor: Hyeog Chan Kwon
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Publication number: 20130027896Abstract: The present invention relates to an electronic component embedded printed circuit board including: a substrate in which a cavity is formed; a plurality of electronic components embedded in the cavity; a metal member inserted between the plurality of electronic components; and insulating layers formed on both surfaces of the substrate to cover the plurality of electronic components, and it is possible to effectively improve heat radiation characteristics.Type: ApplicationFiled: January 25, 2012Publication date: January 31, 2013Inventors: Seung Eun LEE, Hyun Ho Kim, Yee Na Shin