Abstract: There is provided a wiring substrate. The wiring substrate includes: a wiring pattern of an outermost layer; a solder resist layer having an opening portion therein, wherein a portion of the wiring pattern is exposed through the opening portion, and the exposed portion of the wiring pattern is defined as a connection pad; and a solder bump on the connection pad. The connection pad includes: a solder layer; and a metal post that is entirely covered by the solder layer, wherein a portion of the solder layer is interposed between the connection pad and the metal post.

Abstract: A circuit board mounting apparatus includes a chassis, a circuit board defining two recesses in a front side, two fixing members engaged in the recesses, and two fasteners. The chassis includes a side plate defining two through holes. Each recess is bounded by two sidewalls. A latching slot is defined in each sidewall. A fixing hole is defined in a front side of each fixing member. Two resilient arms are formed at opposite sides of each fixing member, and slantingly extend into the corresponding fixing hole. A projection protrudes from an outer surface of each resilient arm. The fasteners extend through the through holes of the side plate and engage in the fixing holes of the fixing members. The resilient arms are deformed outward by the fasteners, to allow the projections to engage in the corresponding latching slots. Therefore, the circuit board is perpendicularly fixed to the side plate.

Abstract: This invention provides a multilayer printed wiring board in which electric connectivity and functionality are obtained by improving reliability and particularly, reliability to the drop test can be improved. No corrosion resistant layer is formed on a solder pad 60B on which a component is to be mounted so as to obtain flexibility. Thus, if an impact is received from outside when a related product is dropped, the impact can be buffered so as to protect any mounted component from being removed. On the other hand, land 60A in which the corrosion resistant layer is formed is unlikely to occur contact failure even if a carbon pillar constituting an operation key makes repeated contacts.

Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

Abstract: A display apparatus for improving corrosion resistance of a pad area and a method of manufacturing the same. The display apparatus includes a first substrate including a display area, a non-display area, and a pad area, and a second substrate facing the first substrate and corresponding to at least the display area, wherein the pad area includes, a connection area connected to a driving circuit; an exposed area spaced from the connection area; and a plurality of blocking areas between the connection area and the exposed area.

Abstract: A wire bonding joint structure of a joint pad in which electroless surface treatment plating layers of joint pads configured by a nickel layer/a palladium layer/a gold layer are connected to each other by a metal wire and when the metal wire is joined to the electroless surface treatment plating layer, a depth of the wire bonding pad formed by wedge deformation is 1.0 m or more. The electroless surface treatment layer of the joint pad can lower strength and hardness of the wire bonding pad of which the surface is treated to improve follow-up capability between a gold wire and the bonding pad, such that a joint area between the gold and the bonding pad is maximized, thereby increasing joinability at the wire bonding finish process by wedge pressure and greatly improving wire bonding workability.

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract: Described is a preamp flex cable for use in a hard drive. The flex cable incorporates a stiffener layer operable to provide a mechanical support, an insulating layer provided over the stiffener layer and having at least one via provided therein to expose the stiffener layer, and at least one conductive layer provided over the insulating layer. The at least one conductive layer forms an electrical circuit and at least one heat removing element that extends through the via and establishes a contact with the stiffener layer.

Abstract: A wiring board includes a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on a surface of the first substrate and including interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the fist substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including conductive circuits for being connected to semiconductor elements, a filler filling the opening portion such that the interposer is held in the opening portion of the built-up layer, and mounting pads formed on the first substrate and positioned to mount the semiconductor elements. The mounting pads are positioned to form a matrix on the first substrate.

Abstract: According to one embodiment, semiconductor memory device is capable of operating at a first mode and a second mode which is higher in speed than the first mode. The semiconductor memory device comprising: a semiconductor memory; a controller which controls the semiconductor memory; a connector which is provided with terminals for sending and receiving data to and from an external device; and a substrate on which the semiconductor memory, the controller, and the connector are mounted, the substrate comprising a plurality of wiring layers. The controller and the connector are mounted on an identical surface of the substrate. The substrate comprises a wiring which connects a mounting pad for the terminal for data transfer at the second mode of the connector and a mounting pad for a pin for data transfer at the second mode of the controller to each other on the wiring layer on a mounting surface for the connector and the controller.

Abstract: Disclosed herein a sensor package for a touch panel and a method of manufacturing the same, the sensor package for the touch panel including: a printed circuit board; a sensor formed over the printed circuit board so as to be spaced apart from the printed circuit board; printed circuit board side connecting pads formed on one surface of the printed circuit board; sensor side connecting pads formed on one surface of the sensor and formed to face the printed circuit board side connecting pads; a first insulating layer formed between the printed circuit board side connecting pads on one surface of the printed circuit board; and a second insulating layer formed between the printed circuit board side connecting pad and the sensor side connecting pad and including conductive balls.

Abstract: A wiring board includes an insulating layer, and an upper wiring pattern and a lower wiring pattern arranged with the insulating layer interposed therebetween. A truncated cone-shaped projection is integral with the lower wiring pattern so as to project at the upper wiring pattern side, and a truncated cone-shaped projection is integral with the upper wiring pattern so as to project at the lower wiring pattern side. Bonding end portions of the projections are bonded to each other to form an inter-layer connection conductor. The inter-layer connection conductor conducts the upper wiring pattern and the lower wiring pattern.

Abstract: Surface-active dopants are added to a portion of a circuit package before a reflow process to promote wetting and reduce the formation of solder bump bridges. The circuit package has a solder element that electrically connects the circuit package to a substrate. A reflow process is performed to attach the solder element to a pad on the circuit package. During the reflow process, the surface-active dopants diffuse to the surface of the solder element and form an oxide passivation layer on the surface of the solder element.

Abstract: An electronic assembly includes a first substrate, at least one first conductive pad and multiple second conductive pads. The first substrate comprises a base layer and at least one conductive circuit layer. The at least one conductive circuit layer is disposed on the base layer. The at least one first conductive pad is disposed on the first substrate. The first conductive pad is electrically insulated from the conductive circuit layer. The first conductive pad includes multiple first holes. The second conductive pads are disposed on the first substrate. The second conductive pads are electrically connected to the conductive circuit layer.

Abstract: A 3D stacked package structure includes a first unit, a molding unit, a conductive unit and a second unit. The first unit includes a first substrate and at least one first electronic component, and the first substrate has at least one runner and at least one first conductive pad. The molding unit includes a top portion, a frame, and at least one connection connected between the top portion and the frame. The conductive unit includes at least one conductor passing through the frame and electrically connected to the first conductive pad. Therefore, the first unit can be stacked on the second unit through the frame of the molding unit, and the first unit can be electrically connected to the second unit through the conductor of the conductive unit.

Abstract: A printed circuit board including a first outer layer, a second outer layer and an integrated circuit mounted on the second outer layer. The integrated circuit has a single exposed pad electrically connected to a ground reference, a first supply pin electrically connected to a first power supply and a second supply pin electrically connected to a second power supply, wherein the first power supply is configured to generate a first supply current with frequency components higher than the frequency components of a second supply current generated by the second power supply.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an interposer having a top interposer surface over the substrate; attaching an interposer pad extension to the top interposer surface, the interposer pad extension having an extension contact surface and a lower contact surface, the surface area of the extension contact surface being smaller than the surface area of the lower contact surface; and forming a package encapsulation on the substrate, the interposer, and the interposer pad extension, the package encapsulation having a recess exposing the top interposer surface, the interposer pad extension embedded only in the package encapsulation.

Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

Abstract: Provided is a semiconductor package. The semiconductor package includes an insulation substrate with top and bottom surfaces. The semiconductor package further includes a circuit pattern on the top surface. The circuit pattern includes a first signal conductive pattern and first and second ground conductive patterns. The semiconductor package includes a first insulation film covering the first signal conductive pattern and exposing a first portion of the first ground conductive pattern and a portion of the second ground conductive pattern. The semiconductor package further includes a first conductive member on the first signal conductive pattern and the first and second ground conductive patterns. The first conductive member electrically connects the first and second ground conductive patterns by covering a portion of the first insulation film and coming in contact with the first portion of the first ground conductive pattern and the portion of the second ground conductive pattern.

Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract: A high-frequency module includes first and second switch IC elements and a substrate. The first and second switch IC elements are the same or substantially the same IC chips, and are mounted in the same or substantially the same orientation. The first switch IC element is mounted on the substrate. The second switch IC element is mounted above the first switch IC element. Due to wire bonding, the individual pad electrodes of the first and second switch IC elements are connected to the land electrodes of the substrate, which are to be connected to the individual pad electrodes. Between a pad electrode and a land electrode connected to each other, another land electrode is not provided.

Abstract: A printed circuit board has a first solder land, a second solder land, and a signal line pattern. The first solder land is configured to be soldered with an electronic part. The second solder land is configured to accumulate solder, the second solder land being disposed on a downstream side of the first solder land as viewed in a direction in which the printed circuit is carried. The signal line pattern includes an exposed part that is not covered with a resist, the exposed part being disposed between the solder land and the solder bridge prevention land.

Abstract: A device mounting board includes a metallic substrate, an oxide film formed such that the surfaces of the metallic form are oxidized, an insulating resin layer disposed on the oxide film facing one main surface of the metallic layer, and a wiring layer disposed on the insulating resin layer. The film thickness of a certain partial region of the oxide film disposed below a first semiconductor device is greater than that of the other regions surrounding the partial region of the oxide film. Conversely, the film thickness of the insulating resin layer underneath a second semiconductor device is less than that of the insulating resin layer underneath the first semiconductor device.

Abstract: A display device includes: a display substrate in which a display for displaying an image is formed; an encapsulation substrate, which is assembled on the display substrate and has a first surface facing the display substrate and a second surface opposite to the first surface; and a circuit substrate for transferring an electrical signal to the display, where a plurality of pads, which are electrically connected to the display and connected to the circuit substrate, are formed on the first surface of the encapsulation substrate, and at least one connector is formed on surfaces of the display and the encapsulation substrate which face each other, the connector configured to provide a connection path between the display and the circuit board by being adhesively pressed in a vertical direction.

Abstract: A module incorporating electronic component includes a substrate, a wiring pattern located on at least one surface of the substrate, at least one electronic component electrically bonded to the wiring pattern, and bonded to the substrate, and a sealing resin arranged to cover the surface of the substrate including the bonded electronic component. The wiring pattern includes a plurality of land electrodes, and electrically bonded to the electronic component or a via conductor, and a wiring electrode arranged to connect the land electrodes, and an insulating resin is disposed on the wiring electrode except for a boundary between the land electrode and the wiring electrode, so as to cross at least one boundary between the substrate and the wiring electrode such that an adhesion strength between the insulating resin and the sealing resin is higher than an adhesion strength between the insulating resin and the wiring pattern.

Abstract: Systems and methods for routing cables in an electronic device are provided. In some embodiments, the electronic device may include a touch sensor having a number of traces, a display component, and a mechanical button, each of which may be coupled to a circuit board via a single flexible circuit cable. This may save valuable space within the electronic device.

Abstract: A wired circuit board includes an insulating layer formed with a first opening and a second opening, a conductive layer formed on the insulating layer and including a terminal overlapping the first opening, and a wire having a part thereof overlapping the second opening and continued to the terminal, a metal pedestal portion formed under the insulating layer and disposed around the first opening so as to overlap the second opening and support an electronic element, and a conductive portion filling the second opening to provide electrical conduction between the wire and the metal pedestal portion.

Abstract: A modified 0402 footprint for a PCB, including: at least two padstacks each having a minimum area consistent with the 0402 standard; and each padstack modified on at least two corners such that the padstack's footprint can be placed beneath a ball grid array (‘BGA’), the BGA having approximately a 1 millimeter pitch, and such that the padstack may be placed at least at a minimum distance away from a closest via in the PCB, wherein each padstack has a trace to a via not directly under a padstack in the PCB and each padstack has no via within the padstack.

Abstract: An electronic device is presented for electrical connection between a first pad contact of an integrated circuit component and a target contact positioned substantially in a first plane of a target platform. The electronic device includes a first surface substantially parallel to the first plane and a second surface below the first surface substantially parallel to the first plane. The first surface includes a first contact region configured to connect to the first pad contact when the electronic device is connected between the first pad contact and the target contact. The second surface includes a second contact region configured to connect to the target contact when the electronic device is connected between the first pad contact and the target contact. The electronic device further includes a multitude of electrically passive elements connected between the first and second contact regions.

Abstract: A display device including a substrate, a display unit on the substrate, a sealing substrate coupled to the display unit, a plurality of power pads on the sealing substrate and electrically coupled to the display unit, and a connector including a housing unit, a power connection unit electrically coupled to the plurality of power pads, and a power contact unit for maintaining contact between the plurality of power pads and the power connection unit.

Abstract: A dummy trace portion is provided in a region between at least a suspension board with circuit on one end side and a support frame of a suspension board assembly sheet with circuits. A base insulating layer is formed on a support substrate in the dummy trace portion. A plurality of conductor traces are formed on the base insulating layer, and a cover insulating layer is formed on the base insulating layer to cover each conductor trace. At least one of the base insulating layer and the cover insulating layer in the dummy trace portion has a groove.

Abstract: A first step of the method for assembling a wire element with an electronic chip comprises arranging the wire element in a groove of the chip delineated by a first element and a second element, joined by a link element comprising a plastically deformable material, and a second step then comprises clamping the first and second elements to deform the link element until the wire element is secured in the groove.

Abstract: Three-dimensional power electronics packages are disclosed. In one embodiment, a three-dimensional power electronics package includes a metalized substrate assembly, a first power electronics device, and a second power electronics device. The metalized substrate assembly includes an insulating dielectric substrate having a power via fully-extending through the insulating dielectric substrate, a first conductive layer on a first surface of the insulating dielectric substrate, and a second conductive layer on a second surface of the insulating dielectric substrate. The first conductive layer is electrically coupled to the second conductive layer by the power via. The first power electronics device is electrically coupled to the first conductive layer such that the first power electronics device is positioned in a first plane.

Abstract: Provided is a printed wiring board including a first heat dissipation pattern placed in one surface layer on which a semiconductor package is to be mounted, a second heat dissipation pattern placed in the other surface layer, and an inner layer conductor pattern placed in an inner layer, in which through holes are formed in the printed wiring board; the first heat dissipation pattern has a joint portion which is placed in an opposed region opposed to a heat sink of the semiconductor package and which is joined to the heat sink with solder; at least one of the through holes is placed in the opposed region; and the second heat dissipation pattern is formed in a pattern in which an end portion of a conductor film in the one of the through holes on the other surface layer side is separated.

Abstract: A package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

Abstract: An apparatus includes a substrate and a plurality of conductive traces formed on the substrate. The conductive traces are doped with a concentration of an aluminum material forming a protective layer as a portion of the plurality of conductive traces to inhibit oxidation. A set of first metal contact pads are formed in contact with the plurality of conductive traces. The substrate, the plurality of conductive traces and the set of first metal contact pads define an electronic circuit board configured to operate at a temperature greater than 200 degrees Celsius. A high operating temperature electronic device is configured in electrical communication with the conductive traces defining an assembly configured to operate at a temperature greater than 200 degrees Celsius.

Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

Abstract: A packaging substrate includes a copper foil substrate, a sputtering copper layer, a dielectric layer, a plurality of electrically conductive connection points, and an electrically conductive pattern layer. The sputtering copper layer is formed on the copper foil substrate. The electrically conductive connection points are formed on a surface of the sputtering copper layer, which is away from the copper foil substrate. The dielectric layer is sandwiched between the electrically conductive pattern layer and the sputtering copper layer. A plurality of first blind via are formed in the first dielectric layer. The electrically conductive pattern layer includes a plurality of electrically conductive traces and a plurality of connection pads. Each electrically conductive connection point is electrically connected to the electrically conductive trace by the first blind via.

Abstract: An method of mounting electronic component includes: providing a connecting layer between a wiring and an electronic component, the connecting layer including a conductive layer formed of a solder powder-containing resin composition containing thermosetting resin, solder powder, and a reducing agent and one or two layers of a thermoplastic resin layer formed of thermoplastic resin; and electrically connecting the electronic component to the wiring through the connecting layer.

Abstract: Electronic devices may include a first substrate bearing circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. A second substrate may be electrically connected to at least one of the microscale bond pads. Methods of forming electronic devices may include positioning a first substrate adjacent to a second substrate. The first substrate may bear circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. The second substrate may be electrically connected to at least one of the microscale bond pads.

Abstract: A circuit board with reduced adhesive overflow includes a substrate and a conductive layer. The conductive layer is disposed on the substrate. The conductive layer includes a hole, a first placement area and a second placement area. The hole is used for forming a cavity with the substrate. The first placement area is used for the first electronic element to be fixedly connected onto the circuit board through the first contact surface. The second placement area is used for the second electronic element to be fixedly connected onto the circuit board through the second contact surface. An adjacent place of the first placement area and the second placement area and the hole are overlapped. The cavity is used to accommodate the conductive adhesive for fixedly connecting the first electronic element and the second electronic element.

Abstract: A chip on glass substrate includes a substrate, first, second, and third pads that are arranged on the substrate and that are electrically connected to an IC device, and first to fourth conductive patterns. A first conductive pattern is arranged on the substrate, has one end electrically connected to the first pad, and has another end that is electrically floated. Second and third conductive patterns are arranged on the substrate, each have one end electrically connected to the second pad, and each have another end that is electrically floated. A fourth conductive pattern is arranged on the substrate, has one end electrically connected to the third pad, and has another end that is electrically floated.

Abstract: Disclosed herein are a power module using sintering die attach and a manufacturing method of the same. The power module includes: a substrate having an insulating layer formed on a surface of a metal plate; a circuit layer formed on the substrate and including a wiring pattern and an electrode pattern; a device mounted on the wiring pattern; a sintering die attach layer applying a metal paste between the wiring pattern and the device and sintering the metal paste to bond the wiring pattern to the device; and a lead frame electrically connecting the device to the electrode pattern, whereby making it possible to simplify and facilitate the process, increase electrical efficiency and improve radiation characteristics, and manufacture firm and reliable power module.

Abstract: A wiring substrate includes an insulating layer, an upper wiring pattern, and a lower wiring pattern, the wiring patterns sandwiching the insulating layer. The lower wiring pattern includes an interlayer connecting conductor integral therewith and projecting toward the upper wiring pattern for electrical connection to the upper wiring pattern. The interlayer connecting conductor is joined to the upper wiring pattern so as to penetrate into the upper wiring pattern beyond a joining interface between the insulating layer and the upper wiring pattern. Thus, the wiring substrate adaptable for a large current is provided without causing degradation of reliability in connection, which may occur by cracking, disconnection, interlayer peeling-off, etc.

Abstract: A system has a circuit board, an integrated circuit being mounted on the circuit board by external contacts, and a cover irreversibly connected to the circuit board. The cover covers the external contacts so that external access to the external contacts is prohibited by the cover.

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract: Disclosed herein is a power module package including an external connection terminal; a substrate in which a fastening unit allowing one end of the external connection terminal to be insertedly fastened thereinto is buried at a predetermined depth in a thickness direction; and a semiconductor chip mounted on one surface of the substrate.

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract: A mounting structure of a chip component includes a chip component that is bonded by having a pair of external terminal electrodes provided on both ends of an element body of the thin chip component bonded to a pair of lands respectively through solder, the pair of lands being provided on an attaching substrate in a lateral direction with respect to each other. Where plan view distances from ends of the external terminal electrodes at the ridge lines formed between the surfaces and side faces of the element body of the chip component to the edges of the lands connected to the external terminal electrodes are designated as “d,” and the vertical distances from the bottom surfaces of the external terminal electrodes and the lands are designated as “t,” then d?t/tan 35° and preferably d?t/tan 25° is fulfilled.