Abstract: A mounting structure includes: an electronic component including: a functional element having a predetermined function; a first resin protrusion section having a surface covered by a covering film including a conductive section electrically connected to the functional element; and a second resin protrusion section that is disposed inside an area surrounded by the first resin protrusion section, and has adhesiveness at least on a surface of the second resin protrusion section, and a base member having a connection electrode and adapted to mount the electronic component. In the structure, the second resin protrusion section mounts the electronic component on the base member in a condition in which the conductive section of the covering film has conductive contact with the connection electrode due to elastic deformation of the first resin protrusion section.

Abstract: An electronic component is mounted on a circuit board. The electronic component includes: a lead frame including a fixed portion, a lead portion connected to the fixed portion, and a heat-dissipating portion connected to the fixed portion; a semiconductor chip fixed on the fixed portion by a first binder; and an encapsulation resin for encapsulating the fixed portion, the semiconductor chip, and a base portion of the lead portion. A groove is provided in the fixed portion and the heat-dissipating portion of the lead frame. The groove extends from a portion of the fixed portion where the first binder is present toward the heat-dissipating portion.

Abstract: Base insulating layers are formed on a support substrate having a conductive property. The support substrate is etched, to form support substrate board and a plurality of conductive portions in a suspension board. The holding piece and the conductive portions constitute a shape determination unit. The conductive portions have first to fifth conductive portions. The third and fourth conductive portions are spaced apart from each other, and the fifth conductive portion is formed between the third and fourth conductive portions. The first and second conductive portions are respectively formed integrally with one end and the other end of the fifth conductive portion. It is determined whether the first and second conductive portions in the shape determination unit are connected electrically to each other. And it is determined whether the first and third conductive portions are connected electrically to each other.

Abstract: A dual interface module comprises a substrate layer having at least two first through-holes, two contact pads on a first side of the substrate, at least two connection pads on a second side of the substrate, at least one electronic element on the second side of the substrate, an antenna pad comprising an antenna on the second side of the substrate, at least two first connection elements in the first through-holes, each first element electrically connecting one of the contact pads with one of the connection pads, at least two second connection elements, each second element electrically connecting one of the connection pads with the electronic element, and two third connection elements, each third element electrically connecting the electronic element with the antenna pad. The module can be arranged on a plastic card body or in a cavity in a plastic card body to form a dual interface card.

Abstract: A printed circuit board (PCB) includes two power supply units, a central processing unit (CPU), two inductors and a temperature compensation resistor. One of the inductor is electrically connected between one power supply unit and the CPU, the other inductor is electrically connected between another power supply unit and the CPU. The temperature compensation resistor is electrically connected between the power supply units and ground, and is positioned between the two inductors to adjust output voltage from the CPU.

Abstract: Provided is a printed circuit board (PCB). The PCB includes a board body that includes a first surface and a second surface opposite the first surface, a semiconductor chip mounting region that is disposed on the first surface of the board body, and includes a plurality of semiconductor chip mounting parts on which a semiconductor chip may be mounted, a through region that is disposed at a peripheral portion of the semiconductor chip mounting region, and includes a plurality of through holes passing through the board body, and an external terminal forming region that is disposed on the second surface of the board body, wherein a plurality of external terminal forming parts are disposed at the external terminal forming region in correspondence with the respective semiconductor chip mounting parts.

Abstract: A bonding structure includes a substrate, multiple first pads, multiple second pads, an insulation layer and a patterned conductive layer. The substrate has a bonding region and a predetermined-to-be-cut region. The first pads are disposed on the substrate and within the bonding region. The second pads are disposed on the substrate and within the predetermined-to-be-cut region. The insulation layer is disposed on the substrate and covers the first and second pads. The insulation layer has multiple first and second openings respectively exposing parts of the first and second pads. The patterned conductive layer is disposed on the substrate and covers the insulation layer and the parts of the first and second pads exposed out by the first and second openings, in which the patterned conductive layer is electrically connected to the first and second pads via the first and second openings.

Abstract: An interposer includes a wiring member including a first inorganic substrate, a reinforcement member including a second inorganic substrate, and an adhesive part interposed between the wiring member and the reinforcement member. Each of the first and second inorganic substrates includes first and second surfaces. Multiple inorganic insulating layers formed on the first surface of each of the first and second inorganic substrates have the same layer configuration and are arranged symmetrically in a vertical direction with the adhesive part centered therebetween. An inorganic insulating layer and an organic insulating layer formed on the second surface of each of the first and second inorganic substrates have the same layer configuration and are arranged symmetrically in the vertical direction with the adhesive part. An organic insulating layer formed on the second surface of each of the first and second inorganic substrates is an outermost insulating layer.

Abstract: An electronic device includes: an electronic component including an external connection terminal; and a lead frame (metal member) connected to the external connection terminal. The lead frame is disposed with a pad. The pad overlaps the external connection terminal in plan view, and at least a portion of the pad is located outside the external shape of the electronic component in plan view. The pad and the external connection terminal are connected by means of a conductive bonding member. The pad and the electronic component are bonded together with a resin. The resin extends to a region of the pad located outside the external shape of the electronic component in plan view.

Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

Abstract: The present invention provides a shield case having electrical conductivity and being mountable on a circuit board. The shield case includes a first surface adapted to be placed on the circuit board and a second surface provided continuously with the first surface and extending at an angle or at a right angle with respect to the first surface. A first recess of generally U-shape is provided in a boundary area of the first surface with the second surface and including first and second end portions. A pair of second recesses is provided in a boundary area of the second surface with the first surface and communicating with the first and second end portions of the first recess. The shield case also includes a pad, being defined by the first and second recesses and connectable by soldering to an electrode of the circuit board.

Abstract: A circuit board for connecting a secondary battery including a first insulation layer, a conductive layer positioned on one surface of the first insulation layer, and a pad layer positioned on the conductive layer and divided into at least two areas is disclosed. In the circuit board, the conductive layer has an area wider than that of the pad layer. Accordingly, the conductive layer has an area wider than that of the pad layer, so that it is possible to miniaturize the circuit board and to improve the safety of the circuit board.

Abstract: A method of mounting a semiconductor element, the method includes: attaching a first solder joint material onto a first pad formed on a substrate supplying a second solder joint material onto the first solder joint material, a second melting point of the second solder joint material being lower than a first melting point of the first solder joint material; arranging the semiconductor element so that a second pad formed on the semiconductor element faces the first pad and a joint gap is provided between the semiconductor element and the substrate; and performing reflow at a reflow temperature lower than the first melting point and higher than the second melting point to join the first solder joint material and the second solder joint material.

Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.

Abstract: A system for providing electrical power connection across components mounted to a backplane of an electrical chassis includes a backplane having multiple apertures and front and rear faces. A daughter board faces the front face of the backplane. The daughter board has multiple traces with individual conductive pads. A power connector connected to the rear face of the backplane has multiple conductive members. Multiple fasteners each extend through both the daughter board and into the backplane to electrically couple each of the conductive pads of the daughter board to one of the conductive members of the power connector.

Abstract: Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate.

Abstract: An anisotropic conductive film includes an adhesive layer formed of a polymer resin, conductive particles dispersed in the adhesive layer, a support layer disposed at one side of the adhesive layer and maintaining the adhesive layer in a film shape, and a releasing sheet disposed at one side of the support layer.

Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (nm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

Abstract: The invention concerns a method for producing a microelectronic device comprising a substrate and a stack comprising at least one electrically conductive layer and at least on dielectric layer, wherein it comprises the following steps: formation, from one face of the substrate, of at least one pattern that is in depression with respect to a plane of the face of the substrate, the wall of the pattern comprising a bottom part and a flank part, the flank part being situated between the bottom part and the face of the substrate, the flank part comprising at least one inclined wall as far as the face of the substrate, formation of the stack, the layers of the stack helping to at least partially fill in the pattern, thinning of the stack at least as far as the plane of the face of the substrate so as to completely expose the edge of said at least one electrically conductive layer flush in one plane, formation of at least one electrical connection member (710, 720) on the substrate in contact with the edge of sai

Abstract: An interposer can have conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component can include a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. Conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract: A single-layer component package comprising: a single conductive-pattern layer having a first surface; an insulating-material layer on the first surface of the single conductive-pattern layer; in an installation cavity inside the insulating-material layer, a semiconductor component having flat contact zones; and solid contact pillars containing copper and solderlessly, metallurgically and electrically connecting the flat contact zones to the single conductive-pattern layer.

Abstract: A semiconductor device for mounting on a wiring board includes: a container for containing a semiconductor chip; and a plurality of leads, each of the plurality of leads includes a mount connection portion at one end for the semiconductor device to be connected to the wiring board, wherein the plurality of leads includes first leads and second leads, a signal transmission rate of the first leads is higher than that of the second leads, and the mount connection portion of each of the first leads is smaller than that of each of the second leads.

Abstract: This multi-layer wiring board is provided with an insulating substrate, an inner layer copper sheet, and an outer layer copper foil. The inner layer copper sheet is disposed within the insulating substrate and has been patterned. The outer layer copper foil is disposed in a state of having been patterned at the surface of the insulating substrate, is thinner than the inner layer copper sheet, and has a cross-sectional area of the current path that is smaller than the cross-sectional area of the current path of the inner layer copper sheet. As a result, provided are: a multi-layer wiring board that can flow a large current and a smaller current while suppressing an increase in the projected area of the substrate; and a method for producing the multi-layer wiring board.

Abstract: A footprint of a printed circuit board (PCB) for a leadframe-based package includes a plurality of pads arranged within a central region on a main surface of the PCB; and an array of signal pads disposed within a peripheral region surrounding the central region.

Abstract: A device includes a carrier, a first semiconductor chip arranged over the carrier and a first electrically conductive element arranged over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and to the first semiconductor chip. The first electrically conductive element is configured to forward an electrical signal between the first wire and the second wire.

Abstract: A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.

Abstract: An integrated interconnect tab that provides a mechanically repeatable connection point to electrical components mounted on a printed circuit board. The integrated interconnect tab comprises a conductive pad surrounded by a vertical sidewall structure formed in an overmolded insulating layer. In one embodiment, a large pad accommodates connections to high-power circuit elements such as batteries and high-voltage capacitors. The sidewall structure helps align and guide the position of an interconnecting device such as a wire ribbon connector, facilitating automation of a subsequent attachment process. An automated method of making a PCB assembly having integrated interconnect tabs entails attaching circuit elements and interconnect tabs to a surface of a PCB substrate, encapsulating the attached components, and selectively machining the encapsulating layer to expose weld tabs, to form the vertical sidewall structure surrounding the tabs, and to create mechanical retention features to aid in welding.

Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.

Abstract: According to one embodiment, a ceramic circuit board includes a ceramic substrate, a copper circuit plate and a brazing material protrudent part. The copper circuit plate is bonded to at least one surface of the ceramic substrate through a brazing material layer including Ag, Cu, and Ti. The brazing material protrudent part includes a Ti phase and a TiN phase by 3% by mass or more in total, which is different from the total amount of a Ti phase and a TiN phase in the brazing material layer that is interposed between the ceramic substrate and the copper circuit plate. The number of voids each having an area of 200 ?m2 or less in the brazing material protrudent part is one or less (including zero).

Abstract: The electronic device includes a terminal structure and a printed circuit board including the terminal structure. The terminal structure includes a solder-joint conductor region placed on a wiring conductor, an intermediate layer contacting with the conductor region, and a solder region contacting with the intermediate layer. The intermediate layer includes an intermetallic compound including tin and at least one of copper and nickel as principal components. When the indentation elastic modulus of the conductor region is E1 and the indentation elastic modulus of the intermediate layer is E2, the ratio of E1 to E2 is equal to or more than 0.8 and equal to or less than 1.5.

Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures.

Abstract: A thermal management system for an electrical component includes a printed circuit board (PCB) capable of receiving the electrical component on a first side of the PCB. An elongate member has one end attached to a second side of the PCB, and another end disposed away from the PCB. The elongate member also has an open interior that facilitates fluid communication between the two ends. One of the ends defines an at least partially closed boundary on the PCB. The PCB includes an aperture disposed therethrough proximate the boundary such that fluid communication is facilitated between the first side of the PCB and the second side of the PCB, and along at least a portion of the elongate member.

Abstract: A die backside film including a matrix material; and an amount of filler particles to render the die backside film thermally conductive, wherein a thermal conductivity of the amount of filler particles is greater than a thermal conductivity of silica particles. A method including introducing a die backside film on a backside surface of a die, the die backside film including a matrix material including an elastomer an amount of filler particles to render the die backside film thermally conductive, wherein a thermal conductivity of the amount of filler particles is greater than a thermal conductivity of silica particles; and disposing the die in a package.

Abstract: A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.

Abstract: An electronic device comprises a functional stack (10) and a cover (50) coupled thereto by an insulating adhesive layer (30). The functional stack (10) comprises a first transparent and electrically conductive layer (22), a second electrically conductive layer (24) and a functional structure (26), comprising at least one layer, sandwiched between said first and second conductive layer. The cover (50) includes a substrate (52) and at least a first conductive structure (66, 68) that is arranged in a first plane between the adhesive layer (28) and the substrate (52). First and second transverse electrical conductors (32, 34) transverse to the first plane (61) electrically interconnect the first and the second electrically conductive layer (22, 24) with the first and the second conductive structure (66, 68) in the first plane (61).

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract: A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (IC) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the IC device to the circuit board, and a surface profile modifier on a surface of the IC device and a surface of the mold, and the surface profile modifier enlarging a surface area of the IC device and the mold to dissipate heat.

Abstract: A textile-type electronic component package includes a textile base; a textile-type electronic component and a plurality of conductive patterns having end contact points formed on the top surface of the textile base; a thermoplastic adhesive formed on the bottom surface of the textile base; a plurality of mounting pads formed on the thermoplastic adhesive and facing the conductive patterns, respectively; and a plurality of via-hole-type coupling parts penetrating end contact points of the conductive patterns, the textile base, and the thermoplastic adhesive, and electrically coupling the mounting pads and the conductive patterns, wherein the via-hole-type coupling parts includes a bunch of via-holes filled with a conductive polymer.

Abstract: A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Abstract: A wiring board includes: wiring layers; insulating layers disposed between the wiring layers; and external connection pads respectively including surface plated layers, for connecting to an external circuit. In each of the external connection pads in one face of the wiring board, an outer peripheral edge of the external connection pad is retracted from an outer peripheral edge of the surface plated layer toward a center of the external connection pad.

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract: A lead structure disposed on a substrate is provided. The substrate includes a display area disposed with a device and a peripheral area disposed with a lead structure including first pads, a second pad, first traces and a second trace. The first traces are connected to the device. Each first trace has a first linear portion and a first bonding portion connected together. Each first trace is electrically connected to one of the first pads through the first bonding portion. The second trace has a second linear portion and a second bonding portion connected together. The second trace is electrically connected to the second pad through the second bonding portion. A width of the first linear portion is smaller than a width of the first bonding portion, and a width of the second linear portion is smaller than a width of the second bonding portion.

Abstract: Methods and apparatus for an interposer with a dam used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes.

Abstract: The present invention provides an adhesive layer for an electrical connection. The adhesive layer includes a base resin; an ionic optical-curing agent; an optical curing accelerant; and a conductive particle having a size of several to several tens nanometers, wherein the adhesive layer is cured by a UV light, and the UV light is diffused by the optical curing accelerant.

Abstract: A circuit board mounting apparatus includes a chassis and a circuit board. The chassis includes a side plate defining a slide slot and a latching hole. A latch protrudes forward from the circuit board, and includes a neck and a latching portion extending left from a front end of the neck. A cutout is defined in a front side of the circuit board. A cantilever extends into the cutout. A hook protrudes forward from the cantilever. The latch extends through the slide slot to allow the neck to abut against a portion of the side plate bounding a left end of the slide slot, and to allow the latching portion to engage with a front side of the side plate. The cantilever resists the hook to engage in the latching hole and abut against a portion of the side plate bounding a right end of the latching hole.

Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.

Abstract: A circuit board includes at least one core substrate, at least one insulating layer and at least one dielectric sheet. An opening is defined in the insulating layer corresponding to the core substrate. An area of cross-section of the opening is larger than that of the core substrate. The core substrate is received in the opening. The dielectric sheet is positioned on one side surface of the core substrate and the insulating layer. A cavity is defined in the circuit board. A number of pads of the core substrate are exposed via the cavity. The present disclosure also provides a method for manufacturing the circuit board and package structure.

Abstract: A display device and organic light-emitting display device, the display device including a substrate; a first line on the substrate; a first pad electrically connected to the first line, the first pad being on a same layer as the first line; a second line on another layer different from the layer on which the first line is formed, an insulation layer being interposed between the first line and the second line; a second pad on a same layer as the first pad; and a connection part electrically connecting the second line and the second pad.