Abstract: A multi-layered printed wiring board, capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises, has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, the wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

Abstract: This invention is a circuit board device having a filter element. It has a base board (4), a circuit part (2) mounted on the base board (4), a filter element (5) arranged between the circuit part (2) and the base board (4), and a semiconductor component (3) mounted on the same plate as the circuit part (2) on the base board (4). The semiconductor component (3) is mounted on a thin plate region (17) that is thinner than a thick plate region (16) having its thickness increased by mounting the circuit part (2) on the base board (4). Thus, the thickness of the whole circuit board device is reduced and the filter element (5) is covered with a sufficiently thick dielectric insulating material so as to prevent deterioration in filter characteristic.

Abstract: A flexible multilayer wiring board manufactured by laminating a metal foil via an insulating layer to cover the first layer circuit wiring formed on a conductive substrate, and a resist layer is formed to cover the second layer circuit wiring formed by pattern-etching the metal foil. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, into interlayer via holes each formed applying a laser beam to the resist layer to establish interlayer connection between the first and second layer circuit wirings. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, into hole portions of an insulating layer formed to cover the second layer circuit wiring to form external connection terminals. Then, the conductive substrate is removed entirely or partly to expose the first layer circuit wiring.

Abstract: At least one of a feedback path and a feed path is divided into two paths, and the divided feedback path and the feed path for feeding a signal form a twisted pattern to suppress radiation noise of a high frequency by a twisted pair effect. The other divided feedback path decreases a resistance value of a direct current component and decreases a whole direct current resistance to feed a sufficient current to the path.

Abstract: A surface mount grid array implemented on a PCB (printed circuit board) optimized for trace escape routing for the PCB. The surface mount grid array includes a plurality of connection blocks, with each connection block including an array of pins and an array of vias, wherein the pins and vias are configured to communicatively connect an integrated circuit device to a plurality of traces of the PCB. The connection blocks are disposed in a tiled arrangement, wherein the connection blocks implement a plurality of trace escape channels along connection block boundaries. The trace escape channels are configured for routing traces from inner pins of the surface mount grid array to a periphery of the surface mount grid array.

Abstract: A substrate (300) for a package of high frequency semiconductor devices comprising a planar insulating substrate having a plurality of parallel, planar metal layers (301a, 301b, etc.) embedded in the insulator. The substrate further has at least one pair of parallel, metal-filled vias (302 and 303) traversing the substrate; the vias have a diameter and a distance from each other of at least this diameter. The metal in each via has a sheet-like extension (321a, 321b, etc.) in each of selected planes of said metal layers, resulting in an increased via-to-via capacitance so that the reflection of a high frequency signal is less than 10%.

Abstract: A circuit structural body includes a printed circuit board having a conductive pattern constituting a power circuit including a semiconductor switching element and disposed on one surface of the printed circuit board, and a conductive pattern constituting a control circuit for controlling the semiconductor switching element and disposed on the other surface of the printed circuit board. The printed circuit board has a through-hole for mounting the semiconductor switching element to both of the conductive patterns. The circuit structural body can be manufactured by a method including the step of laminating a reinforcing plate to one surface of the printed circuit board and the step of mounting the semiconductor switching element from the opposite side to the reinforcing plate.

Abstract: A method for transmitting high-frequency current through a substrate is provided. The method comprises receiving the high-frequency current at a via passing through at least one conductive plane disposed within the substrate and coupled to the via with one or more tabs which span a gap between the at least one conductive plane and the via; and directing the high-frequency current along an uninterrupted path substantially on a surface of the via thereby bypassing the at least one conductive plane by conducting at least a portion of the high-frequency current between the one or more tabs.

Abstract: An electrostatic discharge (ESD) detector and a system having an ESD detector have been described herein.

Abstract: A BGA semiconductor device for high-speed operation and high pin counts has a base which is constituted by a core layer formed of wiring boards and surface layers provided on both sides of the core layer, and a semiconductor element mounted on the base. Through holes in a signal region of the core layer are disposed in an optimum through hole pattern in which power through holes and ground through holes are disposed adjacent to signal through holes.

Abstract: In a printed circuit board of the invention, a first signal wiring layer, a first ground layer, a second ground layer and a second signal wiring layer are laminated via an insulating material. A first signal wiring is formed on the first signal wiring layer and a second signal wiring is formed on the second signal wiring layer. The two signal wirings are connected via a first through hole. The conductive first ground layer and the conductive second ground layer are connected via a second through hole. The second through hole is insulated from the first through hole and formed so as to surround the first through hole.

Abstract: The invention relates to a power plane system for suppressing ground bounce noise. The power plane system of the invention comprises a substrate, a power layer and a ground layer. The power layer comprises a plurality of metal units. There is a distance between two adjacent metal units. A plurality of bridges is used for connecting the metal units. The ground layer has a grounding metal plate. According to the invention, when the ground bounce noise occurs, the metal units can broaden the stop-band bandwidth. Therefore, the signals in the stop-band hardly are transmitted so as to suppress the ground bounce noise, and the high frequency ground bounce noise and the electromagnetic radiation can be suppressed efficiently.

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract: An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

Abstract: The present invention provides a solution to the needs described above through a microphone PCB with an integrated filter. The invention provides for an electret microphone assembly. The microphone assembly includes a multilayer printed circuit board. A field effect transistor with a gate is coupled to the electret microphone. The field effect transistor drain is coupled to provide audio frequency output to an audio output node, and the field effect transistor source is coupled to a ground. A first end of a resistor is coupled to the drain of the field effect transistor and the second end is coupled to a filter. The filter attenuates unwanted electromagnetic interference associated with a radio frequency transmitter.

Abstract: A transceiver module including a primary printed circuit board and a secondary printed circuit board in an enclosure is presented. The primary printed circuit board is coupled to the secondary printed circuit board by a connector pin that protrudes out of a critical surface of the enclosure. The printed circuit boards may be positioned substantially parallel to the critical surface of the enclosure. When a transmitter is electrically connected to the primary printed circuit board and a receiver is electrically connected to the secondary printed circuit board, the transmitter and the receiver may be positioned in a plane that is also substantially parallel to the plane of the critical surface.

Abstract: An apparatus comprises a signal layer including a first and second signal trace. The apparatus also comprises a first reference plane including a first slot substantially parallel to the first and second signal traces. Further, the apparatus includes a dielectric layer having at least a portion disposed between the signal layer and the first reference plane.

Abstract: The present invention provides devices and techniques for replacing at least one processor in a multi-processor computer system with an interposer device that maintains at least some of the input/output (“I/O”) connectivity of the replaced processor or processors. Layers of the interposer device may be configured to match the corresponding layers of the motherboard to which the processors and interposer device are attached. According to some implementations of the invention, the power system of the motherboard is altered to allow a voltage regulator that powers a link between a processor and the interposer device to also power a link between the interposer device and an I/O device.

Abstract: A signal transmission structure is disclosed. The signal transmission structure is adapted for a circuit substrate, including at least a signal line, a plating bar and a reference plane. The plating bar is disposed on a side of the reference plane and connected to the signal line. In addition, the plating bar is disposed on the side of the reference plane, and the reference plane has a non-reference area corresponding to the plating bar. The signal transmission structure can reduce the impedance mismatch at the conjunction of the signal line and the plating bar, and the resonant frequency of the plating bar can be improved as to generate a desired transmission quality of the signal.

Abstract: There is described a multi-layer printed circuit board and a method of installing it. The circuit board includes a first signal layer formed on its obverse surface; a ground layer arranged at a position next to the first signal layer; an electronic power source layer arranged at a position next to the ground layer; and a second signal layer formed on its reverse surface. The first and second patterns are formed around peripheral areas of the first and second signal layers, respectively. The first ground pattern and the second ground pattern are electrically coupled to each other by plural through holes, and the multi-layer printed circuit board is installed on an electro-conductive housing in such a manner that a substantially whole area of the second ground pattern electrically contacts a mounting area of the electro-conductive housing, the mounting area being an electro-conductive area continuously coupled to the electro-conductive housing.

Abstract: A circuit assembly (1) and electronic device (30) having a printed circuit board (2), with conductive runners (3) and a ground plane (4). There is electronic circuitry (5) mounted to the circuit board (2) and electrically coupled to the runners (3). The circuit assembly (1) also has a Liquid Crystal Display (6) electrically coupled to the electronic circuitry (5), and a monopole element (7) is mounted on a surface of the Liquid Crystal Display (6) by a dielectric mount (10) that is proximal to an edge (11) of the printed circuit board (2).

Abstract: A circuit board device suppress with a small number of terminal elements unwanted irradiation originating between a power supply layer and a ground layer, even when a configuration of the power supply layer and the ground layer on the circuit board is complex, and a design support device thereof. The circuit board device has a power supply layer and a ground layer disposed in opposition to one another. A dielectric is disposed between the power supply layer and the ground layer. A power supply surface is divided into two power supply surfaces and by a slit having a generally T-shaped configuration to form power supply surface edges. The power supply surface edges retain across a predetermined length L a characteristic impedance present between the power supply layer and the ground layer. A terminal load is connected to a terminal portion of the power supply surface edges.

Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.

Abstract: The present invention provides a circuit board having a differential signal pad pair consisting of a first signal pad and a second signal pad. The first signal pad has (i) a signal via extending therethrough for electrically connecting the first signal pad to a first transmission line of a differential signal path located within the circuit board and (ii) a contact section for receiving a first contact element of a connector. The second signal pad has (i) a signal via extending therethrough for electrically connecting the second signal pad to a second transmission line of the differential signal path and (ii) a contact section for receiving a second contact element of the connector. The distance between the signal via in the first signal pad and the signal via in the second signal pad is greater than the distance between the contact section of the first signal pad and contact section of the second signal pad.

Abstract: Apparatus for housing electrically powered components to protect such components from damage and interference caused by lightning strikes and other externally generated magnetic fields. Methods of manufacturing such enclosures are also disclosed. A cable entry port and door entry are also disclosed.

Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to.

Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.

Abstract: A memory module has a two-plate heat sink attached by rivets. A front plate contacts the flat surfaces of memory chips on a front surface of the module printed-circuit board (PCB) substrate, while another back plate contacts chips on the back surface of the substrate. The plates contact the substrate along the top edge opposite the connector edge, and along the upper half of the substrate's side edges. Holes in the substrate allow for rivets or other fasteners to pass through to firmly attach the plates to the substrate, prevent wobble. Four top-edge slots are cut in the plates near the top edge, between the rivets along the top edge. The top-edge slots allow air to flow underneath the plates, in small gaps between memory chips, and between the plate and the substrate. The added air flow underneath the plates helps cool the heat-sink plates, reduce hot spots and failures.

Abstract: An information handling system, e.g., computer, server or mainframe, which includes a multi-chip electronic package utilizing an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities of the final system product.

Abstract: A multi-layer printed circuit board includes an insulation substrate; a surface conductive pattern disposed on a surface of the insulation substrate; and an inner conductive pattern embedded in the insulation substrate. The surface conductive pattern has a surface roughness on an insulation substrate side, the surface roughness of the surface conductive pattern being larger than that of the inner conductive pattern.

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.

Abstract: A multi-layer printed circuit board includes at least a ground plane for providing a ground level, at least a signal plane having a plurality of trace regions for transmitting signals, at least a power plane region having a plurality of power blocks for individually providing a plurality of voltage levels, and at least a via for electrically connecting the trace regions with the power plane region or the ground plane. Two adjacent power blocks with different voltage levels are separated by an insulating line. The insulating line has a plurality of first insulating sectors, and a plurality of second insulating sectors for connecting two adjacent first insulating sectors when an included angle of the adjacent first insulating sectors is greater than a predetermined value.

Abstract: A multilayer circuit board (50) includes a plurality of substrate cores (34 and 44), an adhesive/bonding layer (55) between at least two among the plurality of substrate cores, and a microvia (35 and 45) in each of at least two of the plurality of substrate cores. The microvia includes a conductive interconnection (39) between a top conductive surface and a bottom conductive surface of each of the plurality of substrate cores and the microvia in a first substrate core is arranged to be inverted relative to a microvia in a second substrate core. The multilayer circuit board can further include a plated through-hole (54) through the plurality of substrate cores and the adhesive/bonding layer such that at least two among the top conductive surfaces (32 or 46) and the bottom conductive surfaces (36 or 42) of the plurality of substrate cores are connected.

Abstract: A printed wiring board having differential pair signal traces has increased spacing between signal-carrying vias and ground or power planes and/or is equipped with selectively placed ground vias to enhance the impedance matching of the signal traces.

Abstract: A multi-layer printed board including signal layers, each signal layer including a signal line, a through-hole, and a ground through-hole. The signal layer includes a land connecting the through-hole and the signal line. An external periphery of the land has a first portion farthest from a center of the land, and a second portion extending a shorter distance from the center of the land than the first portion. A portion of the external periphery of the land opposite to the ground through-hole closest to the center of the land is the second portion. Consequently, impedance matching can be improved even if a signal frequency is high.

Abstract: A microwave coupler is constructed in a multilayer, vertically-connected stripline architecture provided in the form of a microwave integrated circuit that has a homogeneous, multilayer structure. Such a coupler has a vertically-connected stripline structure in which multiple sets of stripline layers are separated by interstitial groundplanes, and wherein more than one set of layers has a segment of coupled stripline. A typical implementation operates at frequencies from approximately 0.5 to 6 GHz, although other frequencies are achievable.

Abstract: An integrated circuit package comprises a set of bond fingers for connecting wire bonds from the chip, the bond fingers being placed overlapping on a transverse axis from the chip and extending inwardly and outwardly from vias positioned at different positions along the transverse axis, so that wire bonds connected to adjacent fingers have the same length.

Abstract: There is disclosed a semiconductor device comprising at least one first pad being formed above a substrate and given a first potential, at least one first conductive layer being formed between the first pad and the substrate so as to be electrically connected to the first pad, at least one second pad being formed above the substrate so as to sandwich the at least one first conductive layer between the second pad and the substrate, and given a second potential different from the first potential, at least one second conductive layer being formed between the first and second pads and the substrate so as to be electrically connected to the second pad, and a plurality of insulating layers being stacked on the substrate and at least one of the insulating layers being as an inter-electrode insulator of a capacitance element.

Abstract: A printed circuit board structure for a scope unit of an electronic endoscope system, which is provided with a first printed circuit board formed with a first circuit section, and a second printed circuit board formed with a second circuit section. The first printed circuit board is piled on the second printed circuit board. The second printed circuit board having an area covered with the first printed circuit board and at least one area which is not covered with the first circuit board. The at least one area is used for electrically connecting the second circuit section with an electrical unit other than the second circuit section.

Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract: A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: A technique has been developed whereby crosstalk induced in a first electrical connection by current flow at an adjacent second electrical connection is at least partially cancelled by an opposing crosstalk signal induced at an inductive coupling between electrical traces extending from or toward the first and second electrical connections, respectively. Crosstalk cancellation is provided by orienting the electrical traces such that current flow through the second electrical connection and respective electrical trace induces an opposing crosstalk signal at the inductive coupling. In some configurations, an inductive coupling between electrical traces includes essentially parallel portions of the traces and an aperture in a voltage plane. In some configurations, cancellation of crosstalk induced by multiple adjacent electrical connection is provided. Crosstalk inducing electrical connections include pins, solder bumps, leads, wires, edge connectors, etc.

Abstract: A flexible printed circuit improves data transfer rates by disposing ground wires in a ground plane proximate to signal wires disposed in a signal channel plane. One or more ground wires is associated with each signal wire pair or each signal wire for imaging of the return currents of the signal pairs. An overlapping alignment minimizes loop area between a ground wire and its associated signal wire. An offset alignment provides a reduced loop area and reduced breakage risk since movement of the flexible circuit does result in compression of the signal wire and its associated ground wire. A combination of overlapping and offset alignment balances signal transfer effectiveness with breakage risk by offsetting ground and signal wires is stress sensitive regions and overlapping ground and signal wires in stress tolerant regions.

Abstract: Systems for power delivery, signal transfer, package design, thermal management, and electromagnetic interference (“EMI”) control are provided to support an integrated circuit (“IC”). The power delivery system includes a power supply, a voltage regulator module and a decoupling capacitance in the form of discrete and/or integral capacitors. The voltage regulator module and decoupling capacitance are located in a connector that may be formed as a cover, socket or a frame for the IC. The power delivery system delivers power to the IC along top, bottom or sides of the IC. The signal transfer system couples signals from the IC to one or more circuits on a circuit board. The package design system for the IC permits signals and/or power to be coupled to selected sides of the IC at connections outside, flush with, recessed or inside the IC package.

Abstract: A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.

Abstract: The present embodiments and associated methods provide for an integrated EMI shield for effective shielding not only from emissions perpendicular to the integrated circuit (IC) chip carrier but also parallel (edgewise) to the carrier. In one embodiment, a method includes forming at least a portion of an internal ground layer along at least a portion of a chip carrier edge, applying an electrically conductive layer to at least a portion of the chip carrier edge, the conductive layer being applied over the exposed portion of the ground layer and in electrical contact with said ground layer, and forming at least one cavity within the top surface of the chip carrier, where the at least one cavity configured to hold one or more integrated circuit chips therein.

Abstract: A data processing system including a control chip, a central processing unit and a printed circuit board is provided. In the data processing system, the printed circuit board not only supports the control chip and the central processing unit, but also serves as an interface for transferring signals between the control chip and the central processing unit. Critical signals can be transmitted from the central processing unit to the control chip via the printed circuit with a better return path.