Abstract: An interconnect system between an integrated circuit device and a printed circuit board may include a filter between the integrated circuit device and the power subsystem of the printed circuit board. The filter may be a low-pass filter that reduces current in a higher frequency range without negatively modifying current in a lower frequency range and may reduce radiated emissions produced during operation of the integrated circuit. The filter may be implemented by arranging core-power voltage conductors and ground conductors at a first or second level interconnect into one or more voltage groupings and one or more adjacent ground groupings such that series inductance is increased. In some embodiments, the first level interconnect may include conductive bumps or pads between an integrated circuit and a substrate. In some embodiments, the second level interconnect may include solder balls, pins, pads, or other conductors of a package, socket, or interposer.

Abstract: An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OS1 is formed in the upper wiring layer of the semiconductor device 1. The stub length L1 is set to a length of ¼ of the wavelength of the known frequency containing peak components of noises. The noise receiving part AT1 is disposed adjacent to the open stub OS1. The open stub OS1 is connected to the power source wiring 4 by an interlayer wiring 6. The noise receiving part AT1 is biased to a ground potential. The basic wave component and odd-number harmonic waves of noises that are generated from the PLL circuit 11 and propagate (the arrow Y1 of FIG. 2) in the power source wiring 4 are reflected (arrow Y2 of FIG. 2) by the open stub OS1 so as to return to the PLL circuit 11, and do not reach the filter circuit 12.

Abstract: Disclosed is a PCB having axially parallel via holes, in which an outer ground via hole, acting as a ground, is formed around a via hole for intercircuit connection in the PCB, thereby minimizing the effect of noise caused by the via hole.

Abstract: A power supply circuit produces a supply voltage to be supplied to a microprocessor which is an integrated circuit. A transmission line type noise filter includes a signal input terminal, a signal output terminal and two ground terminals corresponding respectively to the signal input terminal and the signal output terminal. The transmission line type noise filter eliminates a high-frequency component of DC voltage applied to the signal input terminal and outputs it from the signal output terminal. A first power supply line pattern, formed on a printed-circuit board, connects an output terminal of the power supply circuit with the signal input terminal of the transmission line type noise filter. A second power supply line pattern connects the signal output terminal of the transmission line type noise filter with a power supply terminal of the microprocessor. A ground land pattern is connected with an external ground potential through via holes and makes a connection between the two ground terminals.

Abstract: Techniques are provided for placing and routing vias that conduct signals through a connector between two electrical units. Vias that conduct a first set of signals are placed next to vias that provide return paths for the first set of signals to reduce cross-talk or impedance. Vias that conduct input or output signals can be placed next to vias that provide return paths for the input or output signals to reduce cross-talk. The vias that provide the return paths can conduct, for example, ground signals, power supply signals, or both. Vias that conduct power supply signals can be placed next to vias that provide return paths for the power supply signals to reduce impedance. The vias that provide the return paths for the power supply signals can conduct, for example, ground signals. The via configurations reduce cost and increase yield, and the via configurations are modular.

Abstract: A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.

Abstract: A DC power plane structure applied in multi-layer circuit board is provided. The DC power plane structure includes a first circuit area for receiving a DC power, a noise filter with one end electrically connected to a DC power output end of the first circuit area, and a second circuit area which is electrically isolated from the first circuit area. The second circuit area has a band gap structure, and the DC power input end of the band gap structure is electrically connected to the other end of the noise filter for inhibiting high-frequency noise generated between layers of the multi-layer circuit board.

Abstract: A high frequency multi-layer printed circuit board, according to the present invention, comprises a through connection having an impedance adapting structure surrounding the through connection and enabling an adjustment of the characteristic impedance of the through connection to a desired value. Thus, high frequency signals may be led through the printed circuit board with reduced signal deformation. The high frequency multi-layer printed circuit board is applicable for high frequency signals up to the GHz-range.

Abstract: A composite structural member with an integrated electrical circuit is provided. The structural member includes a plurality of layers of structural reinforcement material, and two or more electrical devices are disposed at least partially between the layers with an intermediate layer of the structural reinforcement material disposed between the electrical devices. At least one electrical bus is disposed in the structural member, and each electrical device is connected to the bus by a conductive electrode. Thus, the electrodes can extend through the intermediate layer of the structural reinforcement material to connect each of the electrical devices to one or more of the buses.

Abstract: A method and system for improving power distribution and/or current measurement on a printed circuit board is disclosed. According to the invention, a first power plane adapted for current measurement includes a first segment to which a current source is connected and a second segment to which other devices may be connected, forming the current load. A third segment is used to measure the current between the first segment and the second segment through two vias that link two points of the third segment to, preferably, two pads of the external layer. In a preferred embodiment, vias are connected to the first segment so that current flow in the third segment is linear, to improve and simplify current determination. The resistivity between the pair of vias may be computed or estimated using calibrated currents.

Abstract: An electronic control apparatus includes an exclusive power source line for a charge pump circuit which is discriminated from a common power source line. The exclusive power source line is connected to the common power source wiring via a via-hole va having an impedance larger than that of the exclusive source line. Similarly, the electronic control apparatus includes an exclusive ground line for the charge pump circuit which is discriminated from a common ground line. The exclusive ground line is connected to the common ground via an additional via-hole vb. Furthermore, a noise-suppressing capacitor C is connected between the exclusive power source and around lines.

Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

Abstract: A circuit substrate and a method of manufacturing a slot-shaped plated through slot thereon are provided. The circuit substrate has a linear slot. A slot-shaped plated through hole with a multiple transmission paths is formed in the linear slot so that a multiple of signals can be transmitted through the linear slot at one time. The circuit substrate and the method of manufacturing the slot-shaped plated through hole thereon can increase the level of integration of the circuit, decrease the average routing length of the circuit, boost the production efficiency and lower the production cost.

Abstract: A printed circuit board with vias that reduce or eliminate radio frequency interference and method of forming the same. The printed circuit board includes non-conductive layers, conductive-layers interspersed between the non-conductive layers, vias extending through the non-conductive layers and the conductive layers, radio frequency absorbing material within each of the vias, where the radio frequency absorbing material is at a conductive layer within the printed circuit board at which a conductive trace is not connected to a via, an insulating layer over each radio frequency absorbing material, and a cylindrical conductive material within via and over each insulating layer.

Abstract: Some embodiments of the invention effectively shield signal traces on a substrate without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention provide improved power delivery without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention are described in the claims.

Abstract: In some embodiments, apparatuses and methods for improving ball-grid-array solder joint reliability in printed circuit boards. Such apparatuses may comprise, in an exemplary embodiment, a stiffened printed circuit board defining one or more cavities therein and including one or more stiffening members positioned, respectively, in the one or more cavities. The cavities and embedded stiffening members may be located proximate a ball-grid-array device footprint so as to resist deflection caused by the application of forces to the board by test probe pins during testing. Such methods may include, in an exemplary embodiment, creating one or more cavities in a middle sub-layer of a core layer of a stiffened printed circuit board and inserting one or more stiffening members, respectively, therein. Top and bottom sub-layers may then be secured to top and bottom surfaces of the middle sub-layer to complete the core layer. Other embodiments are also described and claimed.

Abstract: A plurality of wiring patterns in a stripe form are formed to be parallel to one another on one surface of a base insulating layer. The wiring patterns each have a layered structure including a conductive layer and a wiring layer. A thin metal film is formed on the other surface of the base insulating layer, and a plurality of ground patterns in a stripe form are formed to be parallel to one another on the thin metal film. The wiring patterns and the ground patterns are provided in a staggered manner so that they are not opposed to one another with the base insulating layer interposed therebetween. In other words, the ground patterns are provided to be opposed to regions between the wiring patterns.

Abstract: A circuit board includes a first group of layers located close to a top side of the circuit board, and a second group of layers located close to an underside of the circuit board. Signals which are fed to input and output contact terminals on the top side of the circuit board are passed along at least one of the layers of the group. Signals which are fed to input and output contact terminals on the underside of the circuit board are passed along at least one of the layers of the second group. The contact-making holes for connecting the input and output contact terminals to the layers of the first and second groups are preferably formed as blind contact-making holes.

Abstract: A method of creating a layout geometry for a multilayer printed circuit board is described. The method involves identifying a signal trace connected to a connector pin via. A antipad is selected for use in conjunction with the connector pin via, where the antipad is of a size selected to prevent interference with said signal trace.

Abstract: An information handling system has a printed circuit board with a split power plane having a plurality of sections that may be used for distributing different voltages on a single conductive foil layer of the printed circuit board to components on the printed circuit board. Capacitive coupling of the split power plane sections may be enhanced with a high dielectric fill between the portions.

Abstract: A multi-layer printed circuit board includes an insulation substrate; a surface conductive pattern disposed on a surface of the insulation substrate; and an inner conductive pattern embedded in the insulation substrate. The surface conductive pattern has a surface roughness on an insulation substrate side, the surface roughness of the surface conductive pattern being larger than that of the inner conductive pattern.

Abstract: A high frequency multilayer integrated circuit is provided with: a multilayer board including n earth conductor layers (n: integer of two or more than two) and (n-1) dielectric layers each arranged between adjacent earth conductor layers; a first high frequency circuit disposed in one of the most outside earth conductor layers of the multilayer board; a first power-supply/control circuit disposed in this most outside earth conductor layer; a second high frequency circuit disposed in at least one of the dielectric layers and connected to the first high frequency circuit in the multilayer board; a second power-supply/control circuit disposed in another one of the most outside earth conductor layers of the multilayer board; and a third power-supply/control circuit disposed in at least one of the dielectric layers at a portion at which the second high frequency circuit does not exist, the third power-supply/control circuit being connected to the first and second power-supply/control circuits.

Abstract: A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.

Abstract: A method and system for reducing the release of high frequency electromagnetic energy into the environment is disclosed, wherein local regions of distributed capacitance are embedded within a printed circuit board (PCB) and adjacent the PCB conductive traces act as low pass filters and thus increase the rise and/or fall times occurring on such traces. The present invention increases very short rise and/or fall times (e.g., 200 picoseconds or less) without degrading or detrimentally affecting other signal characteristics. The present invention does not substantially affect the voltage amplitude and does not affect the bit period when lengthening the rise and/or fall time. Also, the present invention does not induce any timing jitter that may cause synchronization problems within the system.

Abstract: An R-C network formed on a substrate. The capacitor includes a metal member with anodized and unanodized layers. The unanodized layer functions as one of the capacitor's electrodes. The anodized layer functions as the capacitor's dielectric layer. The resistor is formed from material on the same side of the substrate as the capacitor. In some versions of the invention, the resistor is formed on top of a substrate dielectric layer. In these versions of the invention, a conductor both functions as one of the capacitor's electrodes and connects the resistor to the capacitor. In alternative versions of the invention, the resistor is formed from a film that disposed on the undersurface a metal foil. The foil functions as the resistor to capacitor conductor. Sections of the foil that are removed expose and define the resistor. Solder balls or other connectors on the substrate surface connect the network to another component.

Abstract: An electrical circuit includes a multilayer printed circuit board and a housing which shields against electromagnetic interference. A portion of at least one outer layer of the printed circuit board are in the form of contact areas which are connected to a respective conductor area on a further layer of the printed circuit board. The conductor area occupies an area region that is offset with respect to the contact area and forms a bushing capacitor with a ground area of the outer layer.

Abstract: A low noise multilayer printed circuit board includes at least one ground layer and at least one power layer. The at least one ground layer is divided into a first area and a second area. The first area and the second area are connected by a first metal neckline. The at least one power layer is divided into a third area and a fourth area. The third area and the fourth area are connected by a second metal neckline. The first area corresponds to the third area. The second area corresponds to the fourth area. The location where the first and second areas are connected by the first metal neckline is different from that where the third and fourth areas are connected by the second metal neckline.

Abstract: In a transmission circuit board, ground terminal portions (10) are disposed at every other two rows in both end columns. Each of signal circuit layers (20) includes at least a pair of adjacent signal connecting portions electrically connected to a pair of the wiring portions (21, 22) arranged in parallel in a row direction and the column direction different from those on an adjacent signal circuit layer. Each of the ground layers is electrically connected to at least one of the ground terminal portions (10) in the both end columns.

Abstract: A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements to be electrically coupled to a second electrical contact of an integrated circuit die.

Abstract: A network outlet fixture providing wall-mounted LAN jacks. The fixture may include an in-wall power supply and be configured for mounting within a conventional multi-gang wall box. The power supply may be directly connected to an adjacent wall outlet, which serves as a power source, in the same or an adjacent wall box. The fixture may include both network switching and fiber-to-copper media converter functionality. The fixture may be configured to disconnect the power source upon removal of a face plate of the fixture. Further, the fixture may be configured to allow mounting of the jack-supporting structure in any one of several different positions relative to a remainder of the outlet fixture. This allows for presentation of the LAN jacks in a certain preferred orientation while permitting the remainder of the outlet fixture to be mounted in several different orientations relative to a wall.

Abstract: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.

Abstract: An exemplary circuit board includes a power plane with a first metal plate, a ground plane with a second metal plate, a channel etched in one of the metal plates to define an isolated area therein, and a coupling circuit. A gap is formed between the isolated area and other area of the one of the metal plates. The coupling circuit is electronically connected between the first and the second metal plates in the isolated area for reducing a resonance frequency caused by the channel. The circuit board can reduce electromagnetic interference generated therein.

Abstract: Various embodiments of an apparatus, circuit board, and method are disclosed for cable termination. In one embodiment, a surface pad is disposed on a surface of the circuit board. A ground conductor is in the circuit board, the ground conductor being parallel to and collateral to the at least one surface pad. Also, at least one antipad is positioned between the at least one surface pad and the ground conductor, wherein a nonconductive volume extends from the surface pad to the ground conductor through the at least one antipad.

Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

Abstract: A circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer.

Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.

Abstract: The present invention provides a multilayered power supply line suitable for use in a semiconductor integrated circuit and a layout method thereof. In the multilayered power supply line (10) for the semiconductor integrated circuit, a top metal (12) and a second metal (14) are electrically connected to each other by through holes (18). Further, a capacitor metal (16) is electrically connected to the top metal (12) by through holes (20) to thereby make the top metal (12), the second metal (14) and the capacitor metal (16) identical in potential to one another, whereby the multilayered power supply line functions as a power supply line based on normal wiring metals without functioning as a capacitor. It is thus possible to supply power with reduced impedance.

Abstract: A PCB is provided that is suitable for use in applications where EMI control is of interest. The PCB includes circuitry that communicates with an edge connector having edge traces located on its surface. Additionally, embedded traces are disposed within the dielectric material of the PCB, and each embedded trace electrically connects an edge trace with a corresponding median trace located on a surface of the PCB. An embedded ground layer substantially disposed within the dielectric material defines an area within the dielectric material through which the embedded traces pass. Finally, one or more vias are provided that extend through the dielectric material of the PCB and are filled with a conductive material. The vias are electrically connected to the embedded ground layer and configured to electrically communicate with an associated module. In this way, a structure is implemented that facilitates control of electromagnetic radiation emitted by the PCB circuitry.

Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.

Abstract: A test board for testing a packaged integrated circuit has a set of contacts matching counterpart contacts on a socket. The contacts are each connected to a first voltage plane containing power, a second voltage plane carrying ground, and a set of terminals that will be connected to a tester system. The number of terminals necessary to operate the circuit is identified, both power terminal and signal-carrying terminals to the affected part of the circuit, and two of the three connections to the contacts are severed; e.g. the terminal carrying signals is disconnected from the power and ground. The disconnect from the voltage planes may be performed by an automated milling machine in a short time, providing much faster turnaround than a method that forms a custom-made board.

Abstract: A method for adjusting the equivalent series resistance (ESR) of a multi-layer component includes providing at least first and second layers separated by an insulating layer, providing a resistive layer between the inslulating layer and one of the first or second electrode layers, and adjusting the ESR of the component by varying the effective resistance of the resistive layer. The effective resistance may be varied by adjusting the composition or thickness of the resistive layer. Alternatively, the effective resistance may be varied by forming a plurality of through-holes perforating one of the electrode layers and by then adjusting the respective diameters of selected of the through-holes to vary the extent of coverage on the resistive layer. An additionally disclosed feature of the present subject matter is to incorporate dielectric layers of varied thicknesses to broaden the resonancy curve associated with a particular mutli-layer component configuration.

Abstract: A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

Abstract: A multi-layer circuit board includes a first layer having at least first and second conductive traces of different widths and the same impedance. One of a first power plane and first ground plane has a void region such that the first conductive trace is spaced apart from the first power plane by a first thickness, and the second conductive trace is spaced apart from the first ground plane by a second, different thickness.

Abstract: A technique for reducing the number of layers in a multilayer circuit board having a plurality of electrically conductive signal layers for routing electrical signals to and from a surface of the multilayer circuit board is disclosed. The technique is realized by a method comprising: forming a plurality of electrically conductive vias in the multilayer circuit board extending from the surface of the multilayer circuit board to at least one of the plurality of electrically conductive signal layers; arranging the surface such that a first set of two power/ground pins corresponds to a first via and a second set of two power/ground pins corresponds to a second via positioned adjacent the first via, thereby creating a channel; and routing a first plurality of electrical signals through the channel on the first of the plurality of electrically conductive signal layers.

Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.

Abstract: A circuit board has, in a first signal layer, a signal conductor having a relatively small width and a contact pad having a relatively large width. The relatively large width of the contact pad combined with the relatively narrow signal conductor creates an impedance mismatch between the contact pad and the signal conductor. The circuit board has, in a second signal layer, a ground plane separated from the first signal layer by a nonconductive layer. The circuit board defines an opening in the second signal layer underneath the contact pad. The presence of the ground plane underneath the contact pad typically affects the impedance of the contact pad. The opening in the second signal layer removes a portion the ground plane relative to the contact pad and, therefore, reduces the impedance mismatch between the contact pad and the signal conductor.

Abstract: A multi-layer printed wire board (PWB) structure optimized for improved drop reliability, reliable electrical connections under thermal load, and minimal thickness is provided, along with a mobile terminal, including the PWB. The PWB includes alternating conductive layers and insulative layers. The outermost three layers form an interconnect structure constructed of two conductive layers surrounding an insulative-coated conductive layer. The thicknesses of the various layers are optimized to have an increased resistance to mechanical shock resulting from, for instance, a drop onto a hard surface. In addition, the optimized PWB structure has a minimized thickness and an improved resistance to connection failures resulting from cyclical thermal loads.

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract: A circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated therefrom by a common interim dielectric layer. An electrical assembly including the circuitized substrate as part thereof and a method of making the circuitized substrate are also included. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.