Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configurin

Abstract: A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

Abstract: A shift register unit and a driving method thereof, a scan driving circuit and a display device, wherein the shift register unit comprises an input terminal (INPUT), an output terminal (OUTPUT), a reset terminal (RESET), and a first noise leak terminal (LEAK1), and further comprises an output pull-down module (14), and also an input module (11), an output module (12), a reset module (13) and a first noise leak module (15) that are connected to a first node (PU), the input module (11) being configured to pull up a voltage at the first node (PU) under control of a signal received at the input terminal (INPUT), the first noise leak module (15) being configured to release a noise voltage at the first node (PU) to the first noise leak terminal (LEAK1) under control of a third clock signal (CLK1), and to disconnect an electrical connection between the first noise leak terminal (CLK1) and the first node (PU) during a time period in which the voltage at the first node (PU) is pulled up, by which a stable output of th

Abstract: The plurality of stages of circuit blocks of a driver circuit in a display device include a first transistor and a second transistor. The first transistor is connected at its gate with a first node and controls conductivity between a scanning signal line and a first clock signal line applied with a first clock signal. The first node is at an active potential when at least any one signal of signals output from one stage in each of a forward direction and a reverse direction is at the active potential. The second transistor is connected at its gate with the first node and controls conductivity between the first clock signal line and an input signal line of another stage of circuit block.

Abstract: A GOA circuit includes GOA circuit units. Each of the GOA circuit units at each stage includes an input control module, an output control module, and a pull-down module. The pull-down module includes a first transistor, a second transistor, a third transistor, and a resistor. The GOA circuit unit uses fewer transistors and fewer capacitors. Therefore, the GOA circuit unit proposed by the present invention is beneficial for being used in displays with a narrow bezel. In addition, the GOA circuit unit omits a capacitor so power generated after the capacitor is charged is reduced. It provides a beneficiary effect of reducing power of the whole GOA circuit.

Abstract: A shift register circuit includes a driving unit outputting a first scan signal according to a first clock signal; a pull up unit outputting a driving voltage according to one of a second scan signal and a third scan signal; a pull down unit pulling down voltage of an output end according to a second clock signal; a pull down control unit controlling the voltage of the output end and a driving node according to the first clock signal; a reset unit pulling down the voltage level of the driving node according to a touch-enable signal; and an electric storage unit adjusting the voltage of the driving node according to a touch-stop signal. When the touch-enable signal is enabled, the clock signals and the touch-stop signal are disabled, and when the touch-stop signal is enabled, the clock signals and the touch-enable signal are disabled.

Abstract: Provided is an active matrix substrate that includes a gate line group, a source line group, a pixel electrode arranged in a display area, and a gate line driving circuit (11) formed in the display area. The gate line driving circuit (11) includes an accumulation line that accumulates a voltage for controlling the voltage level of the gate line; an output unit (U1) that controls the voltage level of the gate line according to the voltage of the accumulation line; an accumulated voltage supply unit (U2) that varies the voltage of the accumulation line according to a signal input from another gate line; and accumulated voltage adjustment units (U3) that change the voltage of the accumulation line to a predetermined level according to the control signal.

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Abstract: A gate driver includes a plurality of gate driver units. Each of the gate driver units includes a GOA driving circuit and at least one buffer GOA driving circuits at multiple levels. The GOA driving circuit outputs output signals during a display stage, wherein the output signals are transmitted to gate lines and the buffer GOA driving circuits at multiple levels. The output signals are transmitted between the levels when the buffer GOA driving circuits at the multiple levels are during a touch stage, and the output signals are transmitted to the GOA driving circuit of the driving unit at the next level. In addition, a touch panel includes the above gate driver.

Abstract: An OLED display device includes an array of pixel units. Each pixel unit includes a pixel driving circuit and an OLED. The pixel units in each column is connected to a data line. The pixel units in each row is connected to a first scan line for selecting and activating pixel units to receive a data voltage provided by the data line. The pixel units in each row is connected to a second scan line for selecting and resetting pixel units. An emission control line connected to the pixel units in each odd-numbered row is connected to a first clock signal end. An emission control line connected to the pixel units in each even-numbered row is connected to a second clock signal end. Two emission control signals outputted by the first and second clock signal ends have the same period and have a stable phase difference between 90° and 180°.

Abstract: An embodiment of the disclosed technology provides a driving device for a thin film transistor liquid crystal display (TFT-LCD) and a method for manufacturing the same. The driving device comprises at least one first TFT and at least one second TFT formed a base substrate, wherein load of the first TFT is larger than load of the second TFT, the first TFT is of a top-gate configuration, and the second TFT is of a bottom-gate configuration.

Abstract: There are disclosed a shift register unit (100) and a driving method thereof, a gate driving apparatus and a display apparatus. The shift register unit (100) comprises a scanning direction selection unit (101), a control unit (102), a bootstrap unit (103), a first pull-down maintenance unit (104) and a second pull-down maintenance unit (105), which are used to reduce electric stress of a part of elements in the shift register unit (100), so as to raise stability of operation and prolong service life. Additionally, it is capable of realizing a narrow frame design of a liquid crystal display. The gate driving apparatus can adopt the GOA technique to enhance integrity of the TFT-LCD panel.

Abstract: The present invention provides a scanning driving circuit for executing a driving operation to cascaded scanning lines, the scanning driving circuit includes a pull-down control module, a pull-down module, a reset module, a down link module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source; wherein a cascading manner of the clock signal is determined according to a scanning order of the scanning driving circuit, for the reset module to pull up the corresponding scanning signal of the scanning line. The structure of the scanning driving circuit of the present invention is simple and highly dependable.

Abstract: A display panel includes shift registers coupled in serial. At least one of the shift registers includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.

Abstract: Provided is a shift register circuit including a single conductive transistor which performs overlap scanning without increasing the number of clock signals and reduces power consumption by avoiding an ineffective through current, a gate driver, and a display apparatus. The shift register circuit includes: a shift register unit having a first output transistor which connects an output terminal and a first power supply; and a first gate control circuit of which an output terminal is connected to a gate terminal of the first output transistor, wherein the first gate control circuit includes a timing generation unit and a buffer unit, the buffer unit is a bootstrap circuit, and an output of the timing generation unit to which an input signal is inputted is used as an input of the buffer unit and an output of the buffer unit is used as an output of the first gate control circuit.

Abstract: A gate driving circuit comprises GOA units of multiple stages. Each GOA unit includes a pull-up module and an output module. The pull-up module outputs a second clock signal to the output module when an input signal is at a high level; and the output module is turned on when the second clock signal is at a high level, and outputs a third clock signal as a first gate driving signal and outputs a fourth clock signal as a second gate driving signal when being turned on; the third clock signal and the fourth clock signal have opposite phases but the same cycle, and the cycle of the second clock signal is twice that of the third clock signal. It also discloses a liquid crystal display and a gate driving method, two rows of pixels are driven by one GOA unit, thus the space for disposing TFTs is saved, the sealing area of the LCD is reduced.

Abstract: A sensing driving circuit and a display device including the same are disclosed. In one aspect, the sensing driving circuit includes a plurality of stages configured to respectively output a plurality of sensing signals and including a (K)th stage and a (K+1)th stage. The (K)th stage includes a shift register configured to provide a (K)th carry signal to the (K+1)th stage; and a masking buffer configured to output a (K)th sensing signal. The masking buffer includes a first input circuit configured to provide i) an input signal to a first node based on a node driving signal and ii) a first power voltage to a second node based on the input signal and the node driving signal. The masking buffer also includes a node masking circuit configured to supply the first power voltage to the first node based on a masking signal.

Abstract: A shift register unit includes a first shift register module and a second shift register module. The first shift register module includes a first input module configured to input a start signal to a first control node, a second input module configured to input a first level to a second control node, a first output control module configured to input a second level to the first control node, a second output control module configured to input a first clock signal to the second control node, a first output module configured to input the first clock signal to a first output end, and a second output module configured to input the first level to the first output end. The second shift register module includes a second output end, third and fourth input modules, third and fourth output control modules, and third and fourth output modules.

Abstract: A shift register unit having a pulse width modulation module is provided. The pulse width modulation module includes a first input submodule, a first pull-down submodule, a second input submodule, a second pull-down submodule, a third input submodule, and a third pull-down submodule.

Abstract: The invention provides a GOA circuit for LTPS-TFT, using a resistor (R1) and a tenth TFT (T10) to replace the second capacitor in known technology, and change the diode-style connection of the ninth TFT (T9) in known technology to connect one end of the resistor (R1) to the constant high voltage (VGH) and the other to the gate of the ninth TFT (T9) so that during the output end (G(n)) staying at low, the voltage of the second node (P(n)) follows the (M+1)-th clock signal (CK(M+1)) to switch between high and low, that is, following a fixed frequency to pull down the voltage of the second node (P(n)), prevents the second node from staying at high for long duration and prevents the sixth TFT (T6) and the seventh TFT (T7) from prolonged operation to cause threshold voltage shift and improve GOA circuit stability.

Abstract: A shift register unit includes: a pull-up node control unit; a pull-down control node control unit connected with a first level output terminal, and configured to control an electrical potential at a pull-down control node to be a second level when an electrical potential at a pull-up node is a first level, and to control a pull-down control node to be connected with a first level output terminal when the electrical potential at the pull-up node is a third level; a pull-down node control unit; a gate driving signal output unit; and a carry signal output unit configured to control a carry signal output terminal to output a carry signal under the control of the pull-up node and the pull-down node. The carry signal output terminal provides an input signal to a shift register unit in an adjacent next stage.

Abstract: A scan driving circuit is provided for driving scan line in cascade, including a pull-down controlling module, a pull-down module, a reset-controlling module, a resetting module, a downward-transferring module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source. By disposing the resetting module, the scan driving circuit of the present invention raises the reliability of the scan driving circuit and simplifies the entire structure of the scan driving circuit.

Abstract: The present invention provides a GOA circuit and a liquid crystal display device. The GOA circuit adds the stage transfer unit (900) and the stage transfer pull-down unit (800) and modifying the global control auxiliary unit (1000) to use the stage transfer end (ST(N)) of the stage transfer unit (900) to output the signal which is different from the scan driving signal to be the stage transfer signal and to use the global control auxiliary unit (1000) to stable the voltage level of the stage transfer end (ST(N)) in the period that the output ends (G(N)) of all the GOA units output the scan driving signal at the same time, the signal outputted by the stage transfer end (ST(N)) is opposite to the voltage level of the scan driving signal.

Abstract: Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.

Abstract: A shift register, a gate driving circuit and a display apparatus are provided. The shift register comprises a pull-up node control unit, a pull-down node control unit, a pull-up output unit, a noise reduction unit, and a touch scanning control unit. Herein, the pull-up node control unit is connected to a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal, and a pull-up node (PU); the pull-down node control unit is connected to a high level terminal (VGH), a low level terminal (VGL) and the pull-up node (PU) and a pull-down node (PD); the pull-up output unit is connected to a clock signal input terminal (CLK), the pull-up node (PU), a signal output terminal (Output); the noise reduction unit is connected to the pull-up node (PD) and the low level terminal (VGL); the touch scanning control unit is connected to a control signal input terminal (SW), the pull-up node (PU), the signal output terminal (Output), and the low level terminal (VGL).

Abstract: A shift register unit, a method for driving the same and a gate scanning circuit are provided. The shift register unit comprises an input module for receiving a signal to be shifted, an output module, a reset module and a reset control module, an output terminal of the input module, a control terminal of the output module and an output terminal of the reset module are connected to a first node, an output terminal of the reset control module is connected with a control terminal of the reset module for turning on the reset module under control of control signal received by control terminal of the reset control module to reset the first node, the output module outputs a shifted signal with multiple pulses before the first node is reset. According to the present invention, a gate driving signal with multiple pulses can be outputted by one shift register unit.

Abstract: Disclosed is a display device that may include a display panel, a data driver configured to supply a data signal to the display panel, and a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter, wherein the shift register is arranged in an output terminal of an N-th stage circuit unit formed in a first non-display area and an output terminal of an N-th compensation circuit unit formed in a second non-display area opposite the first non-display area are paired to be connected to an N-th scan line, wherein the N-th compensation circuit unit outputs a compensation signal to the N-th scan line in response to a node voltage of a neighboring stage circuit unit.

Abstract: There are provided a shift register, an array substrate and a display apparatus. The shift register comprises: a triggering module, output module, input terminal, first output terminal and a second output terminal, wherein: the trigger module is configured to, according to an input signal from the input terminal, output a triggering signal that has a phase the same as the input signal and delays half a clock cycle more than the input signal under the action of a clock signal; the output module is configured to output an output signal that has a phase opposite to the input signal and delays half a clock cycle more than the input signal to the first output terminal under the triggering of the triggering signal and under the action of the clock signal; and an operating voltage of a signal outputted from the first output terminal is supplied by a direct current power supply.

Abstract: Provided are a scanning driving circuit and a liquid crystal display device. The scanning driving circuit comprises multiple cascaded scanning driving units (1). Each scanning driving unit (1) comprises an input module (100) for outputting a low-level signal and a plurality of driving circuits (200). Each driving circuit (200) corresponding drives one scanning line. Each driving circuit (200) comprises: a control module (210), for outputting a control signal according to the received low-level signal; an output module (220), and a pull-down module (230), for being connected or cut off according to the received control signal; scanning lines (G(N?1), G(N), G(N+1)), for outputting a high-level or low-level scanning driving signal to pixel units.

Abstract: There are provided a shift register, a gate driving circuit and a relevant display device, comprising a first node controlling module (1), a second node controlling module (2), a third node controlling module (3), a first outputting module (4) and a second outputting module (5). The first node controlling module (1) adjust a potential of a first node (A), the second node controlling module (2) adjust a potential of a second node (B), the third node controlling module (3) adjust a potential of a third node (C), the first outputting module (4) adjust a potential of a driving signal output terminal (Output), and the second outputting module (5) adjusts the potential of the driving signal output terminal (Output).

Abstract: The invention provides a scan driving circuit and a liquid crystal display device. The scan driving circuit includes: an input module for calculating a preceding-stage control signal, first and second clock signals to obtain a first control signal; a resetting module for resetting a control signal node according to a reset signal; a latching module for calculating the first control signal, the first and second clock signals to obtain a second control signal; a logic processing module for performing a logic calculation on the second control signal and a third clock signal to obtain a logic control signal; an output module for calculating the logic control signal to obtain a scan driving signal; and a scan line for receiving and transmitting the scan driving signal to a pixel unit, to reset the control signal node and the scan driving signal and thereby avoid the failure of scan driving circuit.

Abstract: A gate drive circuit is disclosed. The gate drive circuit includes shift register units connected with gate lines. The gate drive circuit also includes clock signal lines to provide clock signals. A trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p?1)-th shift register unit. An end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2M-1)-th shift register unit, low level signal terminals are connected with a first low level signal line, and reset signal terminals are connected with a reset signal line. In addition, forward scan signal terminals are connected with a first scan signal line, and backward scan signal terminals are connected with a second scan signal line.

Abstract: The present disclosure discloses a shift register unit, a gate drive circuit, and a display device. The shift register unit includes first to twelfth switch elements, a first capacitor, and a second capacitor. The first switch element switches on in response to an input signal, the second switch element switches on in response to a first clock signal, the third, the ninth and the twelfth switch elements switch on in response to a signal of the second node, the fourth switch element switches on in response to a signal of the first node, and the fifth, the seventh and the eleventh switch elements switch on in response to a second clock signal.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: A GOA circuit includes GOA circuit units. The GOA circuit units at every two stages share a pull-down circuit. The pull-down circuit includes a first transistor, a second transistor and a third transistor. The present invention uses fewer transistors for the GOA circuit and lower the frequency of the first and second clock signals. The decrease in the frequency of the first and second clock signals helps a decrease in the frequency of charge and discharge to the parasitic capacitance and further a reduction in overall power consumption of the GOA circuit.

Abstract: The present invention provides a GOA circuit based on oxide semiconductor thin film transistor. By adding the fifty-fifth, fifty-sixth, fifty-seventh thin film transistors (T55, T56, T57) respectively corresponding to the fourth, fifth, second nodes (S(N), K(N), P(N)) in the pull-down holding module (600). The fifty-fifth, fifty-sixth, fifty-seventh thin film transistors (T55, T56, T57) are controlled with the stage transfer signal of the GOA unit circuit of the former N?1th stage or the scan driving signal of the GOA unit circuit of the former N?1th stage to pull down the voltage levels of the fourth, fifth, second nodes (S(N), K(N), P(N)) under circumstance that the first node (Q(N)) is not completely boosted to rapidly deactivate the pull-down holding module (600) for ensuring the normal boost of the voltage level of the first node (Q(N)). The first node (Q(N)) is guaranteed to be high voltage level in the functioning period, and thus, the normal output of the GOA circuit is ensured.

Abstract: A scan driving circuit for oxide semiconductor thin film transistors includes a pull-down holding circuit part including a first pull-down holding module and a second pull-down holding module to help extend the lifetime of the circuit. The first pull-down holding module includes a first main inverter and a first auxiliary inverter introducing a constant low voltage level. The second pull-down holding module includes a second main inverter and a second auxiliary inverter introducing a constant low voltage level. The constant low voltage level is set lower than a second negative voltage level, which is in turn lower than a first negative voltage level. An influence of electrical property of the oxide semiconductor thin film transistors on the scan driving circuit, particularly poor functioning resulting from an electric leakage issue, can be prevented.

Abstract: Disclosed is a scan driving circuit for oxide semiconductor thin film transistors, in which a pull-down holding circuit part includes a main inverter and an auxiliary inverter. By introducing a constant low voltage level (DCL) and setting the constant low voltage level (DCL) less than the second negative voltage level (VSS2), which is in turn less than the first negative voltage level (VSS1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (Q(N)) and the output end (G(N)) at low voltage level.

Abstract: The present invention relates to display technology field, provides a shift register unit and a method for driving the same, a shift register, and a display apparatus for solving a problem that the shift register unit of prior art cannot output a stable signal. The shift register unit of the present invention comprises an input module, a pull-up module, an output control module and an output pull-down module; the input module is connected with a signal input terminal, a first clock signal input terminal and a low level signal terminal; the output control module is connected with a second clock signal input terminal and a high level signal terminal; the pull-up module is connected with the high level signal terminal; the output pull-down module is connected with the first clock signal input terminal, the second clock signal input terminal, the high level signal terminal and the low level signal terminal.

Abstract: A shift register, a gate driving circuit, a display panel, a method for driving the display panel and a display device relate to a field of display technology. By aid of adding an output control unit, a second pull-up unit, a second pull-down unit and a selection control signal terminal on the basis of the shift register in the prior art, it can be controlled whether a scan signal should be outputted at a selection driving output terminal. In the gate driving circuit, through controlling the selection control signals applied on the selection control signal terminals, the scan signals can be outputted to a part of gate lines selectively. In the display panel provided in the embodiments of the present disclosure, besides the gate driving circuit, switch devices each of which is connected between third nodes of two shift registers, switch devices each of which is connected between fourth nodes of two shift registers and a mode switching circuit connected to the driving control circuit are incorporated.

Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.

Abstract: The application relates to a shift register unit and a driving method thereof, a shift register circuit and a display apparatus. The shift register unit may include a gate starting terminal, a first clock terminal, a second clock terminal, a reset terminal, a low level terminal, a gate output terminal, a storage capacitor, a charging module, an output control module and a reset module. In the shift register according to the present application, since the reset operation is under control of the second transistor and the fifth transistor both, an improper reset operation will not occur, even if the signal at the reset terminal is unstable.

Abstract: The present invention provides a shift register, a driving method, a gate driving apparatus and a display apparatus. Said shift register comprises a pull-up unit, a reset unit, a pull-down unit and a signal output; the pull-up unit is connected to said signal output and pulls up an output signal; the reset unit is connected to a control end of said pull-up unit and said signal output respectively and resets the potential of the control end of said pull-up unit after said output signal is at high level; the pull-down unit is connected to a control end of said pull-up unit and said signal output respectively and pulls down the potential of the control end of said pull-up unit and said output signal after said reset unit has reset the potential of the control end of said pull-up unit, so that said pull-up unit switches off.

Abstract: A shift register includes a first voltage stabilizing unit, a second voltage stabilizing unit, a main pull-down unit and a main pull-up unit. The first voltage stabilizing unit is used to pull a first driving control signal to a low voltage terminal when a first stabilizing control signal is high. The second voltage stabilizing unit is used to pull the first driving control signal to the low voltage terminal when a second stabilizing control signal is high. The main pull-down unit includes a first sub-pull-down unit controlled by a second gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a first display mode, and a second sub-pull-down unit controlled by a third gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a second display mode. The main pull-up unit is used for pulling up a first gate-terminal signal.

Abstract: A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal.

Abstract: A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.

Abstract: A display is disclosed. The display comprises a panel, a data driver and a scan driver. The panel comprises pixels, data lines and scan lines. The data lines transmit data signals to the pixels, and the scan lines transmit scan signals to the pixels. The data driver provides the data signals, and the scan driver provides the scan signals. The scan driver comprises a shift register circuit. The shift register circuit comprises an i+1th stage carry shift register, an ith stage carry shift register and a jth stage buffer shift register. The ith stage carry shift register generates an i+1th start signal to start the i+1th stage carry shift register, so that the i+1th stage carry shift register generates an i+2th start signal. The i+1th start signal starts the jth stage buffer shift register to generate a jth output signal.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

Abstract: A scan line driver is disclosed. In one aspect, the scan line driver includes a driving signal generation circuit, an output line driving circuit, and a carry transfer circuit. The driving signal generation circuit is configured to generate first and second driving signals based on a plurality of clock signals and a carry signal from a previous scan line driver. The output line driving circuit is configured to generate a scan line enable signal based on the first and second driving signals. The carry transfer circuit is configured to generate a carry signal based on the first and second driving signals.