Abstract: An imprinting method for forming a pattern of a cured product by irradiating a curable composition for imprinting disposed on a substrate with light while the curable composition is in contact with a mold having surface asperities and removing the mold from a cured product of the curable composition. The method includes bringing the mold into contact with the curable composition in a condensable gas atmosphere, wherein the curable composition for imprinting has a viscosity in the range of 1 cP to 40 cP in air at 23° C., and the condensable gas is introduced between the mold and the curable composition such that the curable composition for imprinting has a condensable gas solubility (gas/(curable composition+gas)) (g/g) in the range of 0.1 to 0.4.

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.

Abstract: An exposure apparatus that exposes a substrate by exposure light via liquid between an optical member and the substrate, the exposure apparatus includes: an apparatus frame, an optical system including the optical member, a liquid immersion member that is configured to form an immersion liquid space and that includes a first member disposed at at least a portion of surrounding of the optical member and a second member disposed at at least a portion of surrounding of the optical member, a driving apparatus configured to relatively move the second member with respect to the first member, and a vibration isolator by which the first member is supported to the apparatus frame.

Abstract: A method includes providing an elastomeric stamp including a stamping surface with a first pattern element having a fill factor of 20 to 99 percent and including a continuous region and at least one discontinuous region, the discontinuous region including at least one of: (1) one or more elongated concavities, and (2) one or more interior voids. A second pattern element of the stamping surface has a fill factor of 0.25 to 10 percent, and includes traces with a width from 0.1 micrometers to 50 micrometers. The stamping surface is inked with an ink composition including a functionalizing molecule with a functional group selected to bind to a surface of the ink-receptive material. The inked stamping surface is contacted with an ink-receptive material selected from a sheet or a web for a contact time sufficient to bind the functional group with the surface of the ink-receptive material to form a self-assembled monolayer (SAM) of the functionalizing material.

Abstract: In order to form a fine mask pattern with high accuracy, in a mask blank in which a light-semitransmissive film, a light shielding film, and a hard mask film are laminated in the stated order on a transparent substrate, the light-semitransmissive film containing silicon and additionally nitrogen, the hard mask film containing silicon or tantalum, and additionally oxygen, the light shielding film having the laminate structure of a lower layer, an intermediate layer, and an upper layer and containing chromium, conditions on the light shielding film are adjusted so that etching rates using a mixture gas of chlorine and oxygen are the lowest for the upper layer and the next lowest for the lower layer.

Abstract: Methods and systems for dynamic design attributes for wafer inspection are provided. One method includes, at run time of a wafer inspection recipe, prompting a user of a wafer inspection tool on which the wafer inspection recipe is performed for information for a design based binning (DBB) process. The information includes one or more formulae for calculating design attributes from a design for a wafer. The design attributes are used to bin the defects in the DBB process. The method also includes performing inspection of a wafer according to an updated wafer inspection recipe. Performing the inspection includes binning defects detected on the wafer according to the DBB process in the updated wafer inspection recipe.

Abstract: A micro electrochemical cell, a micro electrochemical gas sensor, and a method for fabrication of the micro electrochemical cell are described that include a photopatternable glass substrate, two or more embedded electrodes integrated with through-glass vias, and a gas-permeable membrane lid. In an implementation, a micro electrochemical cell includes a photopatternable glass substrate; at least one recess formed in the photopatternable glass substrate; a plurality of through-glass vias formed in the photopatternable glass substrate, at least one electrolyte disposed in the at least one recess; a wicking layer disposed over the at least one electrolyte; and a lid assembly.

Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.

Abstract: Embodiments of the invention provide an array substrate and a method of manufacturing the same. The method comprises: forming a gate electrode pattern, a gate insulation layer, an active layer pattern and an etching stopping layer on a substrate; forming a photoresist layer on the etching stopping layer; performing a single patterning process on the photoresist layer, such that photoresist in the first region is partially etched off, photoresist in the second region is completely etched off, and photoresist in the third region is completely remained; and performing a single etching process, such that residual photoresist in the first region and a portion of the etching stopping layer in the first region are etched off, and at the same time, a portion of the etching stopping layer and a portion of the gate insulation layer in the second region are etched off.

Abstract: A method of forming a structure containing a phase-separated structure, the method including applying a block copolymer solution to a substrate to form a layer containing a block copolymer and having a film thickness of less than 100 nm; and phase-separating the layer containing the block copolymer, a solvent of the block copolymer solution comprising a poor solvent exhibiting a poor solubility for a homopolymer A of one of the blocks of the block copolymer.

Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a sil

Abstract: An exposure apparatus can mitigate the impact of fluctuations in the refractive index of ambient gas, and improve, for example, stage positioning accuracy. An exposure apparatus radiates an exposure illumination light to a wafer on a wafer stage through a projection optical system, and forms a prescribed pattern on the wafer, and comprises: a scale, which is provided to the wafer stage; a plurality of X heads, which detect information related to the position of the scale; a measurement frame that integrally supports the plurality of X heads and has a coefficient of linear thermal expansion that is smaller than that of the main body of the wafer stage (portions excepting a plate wherein the scale is formed); and a control apparatus that derives information related to the displacement of the wafer stage based on the detection results of the plurality of X heads.

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. The random diffusion of acid generated by a photoacid generator during a lithography process contributes to line edge/width roughness. Methods disclosed herein apply an electric field, a magnetic field, and/or a standing wave during photolithography processes. The field and/or standing wave application controls the diffusion of the acids generated by the photoacid generator along the line and spacing direction, preventing the line edge/width roughness that results from random diffusion. Apparatuses for carrying out the aforementioned methods are also disclosed herein.

Abstract: An illumination system includes a light source used to generate a light and an opaque plate. The opaque plate is disposed between the light source and a photomask and includes an annular aperture and an aperture dipole. The annular aperture has an inner side and an outer side. The aperture dipole includes at least one first aperture and at least one second aperture. The first aperture and the second aperture connected to the annular aperture respectively and protruding out from the outer side of the annular aperture are disposed symmetrically with respect to a center of the annular aperture.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device may be raised or lowered relative to other areas of the semiconductor device. Therefore, focusing the light on one area causes another to become unfocused. By carefully designing a photomask to cause phase shifts of the light transmitted therethrough, focus across all areas of the semiconductor device can be achieved during photolithography, which results in sharp and accurate patterns formed on the semiconductor device.

Abstract: The invention relates to a method for processing a substrate with a focussed particle beam which incidents on the substrate, the method comprising the steps of: (a) generating at least one reference mark on the substrate using the focused particle beam and at least one processing gas, (b) determining a reference position of the at least one reference mark, (c) processing the substrate using the reference position of the reference mark, and (d) removing the at least one reference mark from the substrate.

Abstract: To improve the manufacturing yield of a semiconductor device, there is to provide a method of manufacturing a semiconductor device using a multilayer resist, in which before performing water repelling processing for immersion exposure on a wafer, an anti-reflection film, an underlayer film, and an intermediate film applied to a wafer edge portion are eliminated through rinse processing.

Abstract: A write wiring trace is formed over insulating layer. A coating layer, being directly in contact with at least a first portion of a surface of the write wiring trace, is formed over the insulating layer to cover the write wiring trace. A connection terminal is formed over the insulating layer to be electrically connected to the write wiring trace and exposed from the coating layer.

Abstract: A new monolithic resonator metasurface design achieves ultra-high Q-factors while using only one resonator per unit cell. The metasurface relies on breaking the symmetry of otherwise highly symmetric resonators to induce intra-resonator mixing of bright and dark modes (rather than inter-resonator couplings), and is scalable from the near-infrared to radio frequencies and can be easily implemented in dielectric materials. The resulting high-quality-factor Fano metasurface can be used in many sensing, spectral filtering, and modulation applications.

Abstract: New photoacid generator compounds (“PAGs”) are provided that comprise a cholate moiety and photoresist compositions that comprise such PAG compounds.

Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

Abstract: A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.

Abstract: The spatial light modulator is provided with: a substrate; a fixed electrode disposed on a surface of the substrate; a connecting section, which has one end of the connecting section connected to the surface of the substrate; a movable section, which is connected to another end of the connecting section; a supporting post section, which extends in the thickness direction of the substrate with one end of the supporting post section connected to the movable section; a reflecting member, which is connected to another end of the supporting post section; a movable electrode, which is disposed on a surface of the reflecting member, the surface of the reflecting member facing the fixed electrode; and a conductive layer, which is disposed on the supporting post section with a film thickness larger than that of the movable electrode, and which electrically connects between the movable section and the movable electrode.

Abstract: The present invention provides methods of fabricating microelectronics structures and the resulting structures formed thereby using a dual-layer, light-sensitive, wet-developable bottom anti-reflective coating stack to reduce reflectance from the substrate during exposure. The invention provides dye-filled and dye-attached compositions for use in the anti-reflective coatings. The anti-reflective coatings are thermally crosslinkable and photochemically decrosslinkable. The bottom anti-reflective coating stack has gradient optical properties and develops at the same time as the photoresist. The method and structure are particularly suited to high-NA lithography processes.

Abstract: A negative pattern is formed by applying a resist composition onto a substrate, exposing the resist film, and developing the exposed resist film in an organic solvent developer. The process further involves coating the negative pattern with a shrink agent solution of a polymer comprising recurring units capable of forming lactone under the action of acid in a C7-C16 ester or C8-C16 ketone solvent, baking the coating, and removing the excessive shrink agent via organic solvent development for thereby shrinking the size of spaces in the pattern.

Abstract: A resist composition including a base component that exhibits changed solubility in an alkali developing solution under the action of acid, an acid-generator component that generates acid upon exposure, and a nitrogen-containing organic compound, the acid generator component including an acid generator represented by general formula (b0), the nitrogen-containing organic compound including a compound represented by general formula (d1) or general formula (d2) in which each of R1 and R2 represents an aryl group or an alkyl group, Rf represents a fluorinated alkyl group, X?represents a counter anion, each of R3 and R4 represents an aliphatic hydrocarbon group, R5 represents a hydrocarbon group having 5 or more carbon atoms, and each of R6 and R7 independently represents a hydrogen atom, an aliphatic hydrocarbon group, or —C(?O)—O—R5.

Abstract: A negative pattern is formed by applying a resist composition onto a substrate, exposing the resist film, and developing the exposed resist film in an organic solvent developer. The process further involves coating the negative pattern with a shrink agent solution of a polymer comprising recurring units having an acid labile group-substituted hydroxyl and/or carboxyl group in a C7-C16 ester or C8-C16 ketone solvent, baking the coating, and removing the excessive shrink agent via organic solvent development for thereby shrinking the size of spaces in the pattern.

Abstract: The invention concerns a manufacturing method for nanolithography masks from a PS-b-PMMA block copolymer film deposited on a surface to be etched, said copolymer film comprising PMMA nanodomains orientated perpendicularly to the surface to be etched, said method being characterized in that it comprises the following steps: partially irradiating said copolymer film to form a first irradiated area and a second non-irradiated area in said copolymer film, then treating said copolymer film in a developer solvent to selectively remove at least said PMMA nanodomains of said first irradiated area of said copolymer film.

Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Abstract: Various embodiments provide photomask patterns and methods for forming the same. In an exemplary method, a to-be-etched pattern can be provided. The to-be-etched pattern can be divided into a first mask pattern and an initial second mask pattern. The first mask pattern can include one or more first patterns and the initial second mask pattern can include one or more second patterns. A second print scattering pattern can be formed and added to the initial second mask pattern. A position of the second print scattering pattern can be separated from a position of the one or more first patterns of the first mask pattern.

Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.

Abstract: A flip chip package and a manufacturing method thereof are disclosed. The flip chip package in accordance with an embodiment of the present invention includes: a substrate; a plurality of pads formed on the substrate; a solder resist covering the substrate in such a way that the pads are exposed; a chip mounted on the substrate in such a way that the chip is electrically connected with the pads; a plurality of bumps formed, respectively, on the pads in such a way that the bumps are interposed between the pads and the chip; an under-fill flowing between the substrate and the chip and being filled in between the substrate and the chip; and an opening placed in between the plurality of bumps in such a way that a flowing space of the under-fill is provided in between the plurality of bumps.

Abstract: The present invention is a new formulation and process for treating TiN semiconductor devices having a high aspect ratio structure formed thereon. The new composition is designed to be used in the chip making process between cleaning a wet etched memory device and its final rinse/drying process. It is intended to include the treatment in order to prevent collapse of the high aspect ratio TiN structure found on the semiconductor device.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an anti-reflection layer on a lower layer, forming photoresist patterns on the anti-reflection layer, forming protection patterns to cover the photoresist patterns, respectively, etching the anti-reflection layer using the photoresist patterns covered with the protection patterns as an etch mask to form anti-reflection patterns, forming spacers to cover sidewalls of the anti-reflection patterns, and removing the anti-reflection patterns.

Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract: The present invention provides a radiation-sensitive resin composition that contains a polymer having a structural unit that includes an acid-labile group; and an acid generator, wherein the acid generator includes a compound including a sulfonate anion having SO3?, wherein a hydrogen atom or an electron-donating group bonds to an ? carbon atom with respect to SO3?, and an electron-withdrawing group bonds to a ? carbon atom with respect to SO3?; and a radiation-degradable onium cation. The compound preferably has a group represented by the following formula (1-1) or (1-2). In the following formulae (1-1) and (1-2), R1 and R2 each independently represent a hydrogen atom or a monovalent electron-donating group. R3 represent a monovalent electron-withdrawing group. R4 represents a hydrogen atom or a monovalent hydrocarbon group.

Abstract: A method of forming nanotubes may include applying a photoresist to a metal substrate, selectively exposing a first portion of the photoresist to electromagnetic radiation while not exposing a second portion to the electromagnetic radiation, removing the second portion of the photoresist from the metal substrate exposing a first portion of the metal substrate, exposing the first portion of the metal substrate to an etchant removing the first portion of the photoresist exposing a second portion of the metal substrate, and growing carbon nanotubes on the second portion of the metal substrate.

Abstract: An etching method containing the step of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal by bringing an etching liquid into contact with the substrate and thereby removing the first layer, wherein the first layer has a surface oxygen content from 0.1 to 10% by mole, and wherein the etching liquid comprises an ammonia compound and an oxidizing agent, and has a pH of from 7 to 14.

Abstract: An orthogonal process for photolithographic patterning organic structures is disclosed. The disclosed process utilizes fluorinated solvents or supercritical CO2 as the solvent so that the performance of the organic conductors and semiconductors would not be adversely affected by other aggressive solvent. One disclosed method may also utilize a fluorinated photoresist together with the HFE solvent, but other fluorinated solvents can be used. In one embodiment, the fluorinated photoresist is a resorcinarene, but various fluorinated polymer photoresists and fluorinated molecular glass photoresists can be used as well. For example, a copolymer perfluorodecyl methacrylate (FDMA) and 2-nitrobenzyl methacrylate (NBMA) is a suitable orthogonal fluorinated photoresist for use with fluorinated solvents and supercritical carbon dioxide in a photolithography process.

Abstract: According to one embodiment, there is provided a manufacturing method of an electronic device including a lower electrode, a source electrode and a drain electrode made of a nanoparticulate conductive material on a substrate, an organic semiconductor layer between the source and drain electrodes, and a gate electrode on the organic semiconductor layer via a gate insulating layer. The manufacturing method includes forming a nonphotosensitive resin layer as the gate insulating layer on the organic semiconductor layer and on the lower electrode, forming a photosensitive resin layer as the gate insulating layer on the nonphotosensitive resin layer, and forming a through hole in the photosensitive resin layer on the lower electrode.

Abstract: A method for processing exposure data (40) for exposing a pattern on a target (30) using a plurality of charged particle beams (24), the exposure data comprising pattern data (42) representing one or more features (60) to be written on the target (30) and exposure dose data (52) describing exposure dose of the charged particle beams.

Abstract: Provided are photoresist overcoat compositions, substrates coated with the overcoat compositions and methods of forming electronic devices by a negative tone development process. The compositions, coated substrates and methods find particular applicability in the manufacture of semiconductor devices.

Abstract: A method of forming patterns includes (a) coating a substrate with a resist composition for negative development to form a resist film, wherein the resist composition contains a resin capable of increasing the polarity by the action of the acid and becomes more soluble in a positive developer and less soluble in a negative developer upon irradiation with an actinic ray or radiation, (b) forming a protective film on the resist film with a protective film composition after forming the resist film and before exposing the resist film, (c) exposing the resist film via an immersion medium, and (d) performing development with a negative developer.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract: A plurality of suspension boards and an inspection substrate are integrally supported by a support frame. In each suspension board, a line is formed on a conductive first support substrate via a first insulating layer. The first support substrate and the line are electrically connected by a first via in the first insulating layer. In the inspection substrate, a conductor layer is formed on a conductive second support substrate with a second insulating layer sandwiched therebetween. The second support substrate and the conductor layer are electrically connected by a second via in the second insulating layer. The first via and the second via have the same configuration.

Abstract: A method of forming a resist pattern, and a film including a metal-containing compound formed on the resist pattern while developing the resist pattern. The method uses an organic solvent developer liquid, in which a metal compound capable of generating a hydroxyl group upon hydrolysis is dissolved in an organic solvent that does not have a functional group that reacts with the metal compound.

Abstract: Methods, algorithms, processes, circuits, and/or structures for laser patterning suitable for customized RFID designs are disclosed. In one embodiment, a method of laser patterning of an identification device can include the steps of: (i) depositing a patternable resist formulation on a substrate having configurable elements and/or materials thereon; (ii) irradiating the resist formulation with a laser tool sufficiently to change the solubility characteristics of the resist in a developer; and (iii) developing exposed areas of the resist using the developer. Embodiments of the present invention can advantageously provide a relatively low cost and high throughput approach for customized RFID devices.

Abstract: Techniques herein provide methods for self-aligned etching that use existing features for patterning or registering a pattern, without damaging existing features. Existing substrate structures are used to create a surface that enables directed self-assembly (DSA) of block copolymers (BCP) without a separate lithographic patterning layer. Methods herein include recessing at least one existing material or structure on a substrate, and adding a film that remains on the recessed material only. This film can be selected to have a preferential surface energy that enables controlled self-assembly of block copolymers. The substrate can then be etched using both existing structures and one polymer material as an etching mask. One example advantage is that self-assembled polymer material can be located to protect exposed corners of existing features, which reduces a burden of selective etch chemistry, increases precision of subsequent etching, and reduces sputter yield.