Abstract: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.

Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

Abstract: A method of manufacturing a flash memory device may include forming a trench, defining at least a common source region, on a semiconductor substrate, forming a gate poly over the semiconductor substrate, performing an ion implantation process employing a first photoresist pattern and the gate poly as a mask, wherein the ion implantation process forms a source/drain junction on the semiconductor substrate, forming a recess common source region in the trench by using a second photoresist pattern, and performing an ion implantation process on the recess common source region.

Abstract: The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques.

Abstract: A method of manufacturing a semiconductor device includes implanting an impurity into a crystalline semiconductor film that is formed over a base and includes a first part in contact with the base, a second part and a third part, so that at least the second part and the third part are doped with the impurity while the first part is prevented from being doped with the impurity, and forming a source and a drain in the second part and the third part, respectively. The implanting includes depositing a material of the crystalline semiconductor film over the base. The forming includes heating at least the second part and the third part.

Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.

Abstract: A semiconductor device provided with a filled tetrahedral semiconductor is formed by introducing impurity atoms S for substituting the component atoms of sites of lattice points and impurity atoms I to be inserted into interstitial sites of a host semiconductor where component atoms are bonded to form a tetrahedral bonding structure. Such a semiconductor device is made to show a high mobility level and a high current drive force as a semiconductor substance where impurity atoms S are made to have a valance electron agreeing with that of the component atoms of the host semiconductor as a result of charge transfer between impurity atoms S and impurity atoms I and impurity atoms I are bonded in a state of showing an electronic arrangement of a closed shell structure is used as channel material.

Abstract: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.

Abstract: Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of the resulting boron-containing film. The boron-containing films have a stress between about ?10 GPa and 10 GPa and may be used as boron source layers or as strain-inducing layers.

Abstract: A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60?), one (60) forming the reference current (RC) side (601) and the other (60?) forming the mirror current side (602) of the CCM (74). The gates (65, 65?) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66?, 66?) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601).

Abstract: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.

Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening.

Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Abstract: A double diffused region (65), (75), (85) is formed in a semiconductor substrate or in an epitaxial layer (20) formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a conductive layer on the first insulating film; exposing the first insulating film by removing a portion of the conductive layer; forming a second insulating film on the exposed surface of the first insulating film in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and then unloading the semiconductor substrate from the first processing chamber to the outside; and annealing the second insulating film in a second processing chamber.

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

Abstract: The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

Abstract: Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.

Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a sacrificial layer on a substrate; forming a patterned resist layer on the sacrificial layer; performing an ion implantation to the substrate; applying a first wet etch solution to remove the patterned photoresist layer; and applying a second wet etch solution to remove the sacrificial layer.

Abstract: A silicide forming method for a semiconductor device. A silicide forming method may include forming a gate electrode by depositing a gate oxide film and/or polysilicon over a silicon substrate and patterning. A silicide forming method may include forming a nitride film spacer over sidewalls of a gate electrode and simultaneously performing source/drain implant and amophization implant over a silicon substrate. A silicide forming method may include depositing an insulating film after performing source/drain and amophization implants. A silicide forming method may include partially and/or entirely exposing a source/drain and/or gate electrode disposed under an insulating film by etching an insulating film. A silicide forming method may include applying a metal film over a silicon substrate and forming silicide over regions etched by performing heat treatment over a source/drain and/or gate electrode.

Abstract: In one aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first conductivity type and having a main surface that has a first plane orientation, a second semiconductor layer of the first conductivity type and having a main surface that has a second plane orientation different from the first plane orientation, the second semiconductor layer being directly provided on the first semiconductor layer, a third semiconductor layer having a main surface that has the first plane orientation, and being formed on the first semiconductor layer and on a side face of the second semiconductor layer, a gate electrode formed on the second semiconductor layer via a gate insulating film, first impurity diffusion regions of a second conductivity type, and being formed in the second semiconductor layer so that the gate electrode is located on a region sandwiched in a gate length direction between the first impurity diffusion regions, the first impurity diffusion regions extending t

Abstract: Method of producing a transistor, comprising in particular the steps of: producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor, etching the gate layer according to the first etching mask, first ion implantation in a part of the substrate not covered by the gate layer, trimming the first etching mask over a length equal to a gate length of the transistor, producing a second etching mask on the gate layer, removing the first etching mask etching the gate layer according to the second etching mask, second ion implantation in another part of the substrate.

Abstract: A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.

Abstract: Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.

Abstract: A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations and depositing amorphous silicon within the recess to from amorphous silicon source/drain extensions. Dopants may be implanted into the amorphous silicon source/drain extensions and the semiconductor wafer may then be annealed.

Abstract: A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in the silicon semiconductor substrate in which the silicon epitaxial layer is formed. The semiconductor transistor device includes a silicon epitaxial layer formed to have a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate. Thus, since a salicide layer is used without increase of leakage current, the transistor device having low power and high performance can be manufactured.

Abstract: A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

Abstract: A method for manufacturing the CMOS image sensor comprising forming an epitaxial layer provided with a plurality of photo diodes on a semiconductor substrate, coating a first photo resist on the epitaxial layer and performing a patterning process on the first photo resist using a predetermined reference value in order to form a first photo resist pattern, coating a second photo resist on the epitaxial layer and first photo resist pattern and performing a patterning process for the second photo resist in order to form the second photo resist pattern on the first photo resist pattern; and forming a well area of a pixel area by performing a dopant implantation process using a mask pattern including the first photo resist pattern and the second photo resist pattern.

Abstract: A transistor includes a gate structure of HfMoN. The work function of the gate structure can be modulated by doping the HfMoN with dopants including nitride, silicon or germanium. The gate structure of HfMoN of the present invention is applicable to PMOS, NMOS or CMOS transistors.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.

Abstract: One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, comprising: implanting a first dopant into a first partial completion of the device, the first dopant comprising a first noise reducing species; and implanting a second dopant into a second partial completion of the device, the second dopant and the first dopant being opposite conductivity types.

Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.

Abstract: A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon.

Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.

Abstract: A method for forming a uniform doped region in a substrate having a non-uniform material layer thereon is provided. The non-uniform material layer is removed form the substrate. Thereafter, a treatment process is performed to form an offset material layer on a predetermined doped region of the substrate. Next, an ion implantation process is performed to form the uniform doped region in the predetermined doped region below the offset material layer.

Abstract: A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT.

Abstract: A method of manufacturing a semiconductor device includes forming, over a substrate, a gate insulating film containing a high-k insulating film which is composed of a material having a dielectric constant larger than that of silicon dioxide film; forming a gate electrode containing a metal over the gate insulating film; forming extension regions by implanting an dopant into the substrate using the gate electrode as a mask; and annealing the substrate, having the dopant implanted therein, by flash lamp annealing or laser annealing; wherein the annealing further includes: a first step irradiating a substrate with a light pulse having a predetermined peak intensity; and a second step irradiating a substrate with light pulses having peak intensities lower than that of the light pulse used in the first step.

Abstract: A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.

Abstract: MOS transistors and methods for fabricating MOS transistors are provided. One exemplary method comprises providing a substrate having a silicon-comprising surface region. A first metal silicide layer is formed overlying the silicon-comprising surface region. Ion implantation is used to implant rare earth metal ions at an interface between the first metal silicide layer and the silicon-comprising surface region. The substrate is heated to form a second rare earth metal silicide layer disposed below the first metal silicide layer.

Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.

Abstract: Low contact resistance semiconductor devices and methods for fabricating such semiconductor devices are provided. In accordance with one exemplary embodiment, a method comprises depositing an insulating material overlying a metal silicide region and etching a contact opening within the insulating material and exposing the metal silicide region. The contact opening is at least partially bottom-filled with substantially pure cobalt. A conductor is deposited in the contact opening if, after the step of at least partially bottom-filling, the contact opening is not filled with the substantially pure cobalt.

Abstract: A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.