Abstract: An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

Abstract: A method of manufacturing a semiconductor device is further described, comprising the steps of providing a supply of dopant atoms or molecules into an ionization chamber, combining the dopant atoms or molecules into clusters containing a plurality of dopant atoms, ionizing the dopant clusters into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ion by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate. In general, dopant clusters contain n dopant atoms where n can be 2, 3, 4 or any integer number. This method provides the advantages of increasing the dopant dose rate to n times the implantation current with an equivalent per dopant atom energy of 1/n times the cluster implantation energy.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusion portion of the silicon film, forming a dummy film over the silicon film, etching the dummy film so that the dummy film is partially remained on sidewalls of the protrusion portion, etching the silicon film using the remaining dummy film to form a gate electrode, and performing ion implantation into the semiconductor substrate to form source/drain regions.

Abstract: A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewalls made of an insulator to cover side surfaces of the gate electrode; ion-implanting into the semiconductor layer on both sides of the gate electrode to form drain/source regions; partially etching the sidewalls to expose upper parts of the side surfaces of the gate electrode; depositing a metal film to cover the tops of the drain/source regions and of the gate electrode and the exposed upper parts of the side surfaces of the gate electrode; and performing heat treatment on the SOI substrate to form silicide layers respectively in the surfaces of the gate electrode and of the drain/source regions.

Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.

Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.

Abstract: An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels.

Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.

Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 ? of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

Abstract: Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate.

Abstract: An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm?3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface.

Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

Abstract: In sophisticated transistor elements, an additional silicon-containing semiconductor material may be provided after forming the drain and source extension regions, thereby reducing the probability of forming metal silicide regions, such as nickel silicide regions, which may extend into the channel region, thereby causing a significant increase in series resistance. Consequently, an increased degree of flexibility in adjusting the overall transistor characteristics may be achieved, for instance, by selecting a reduced spacer width and the like.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium.

Abstract: One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, including introducing a first dopant into a first partial completion of the device, the first dopant including a first noise reducing species; and introducing a second dopant into a second partial completion of the device, the second dopant and the first dopant being opposite conductivity types.

Abstract: A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed on a gate dielectric layer in or on both the PMOS regions and the NMOS regions. An n-type doping is used to create n-type wet etch sensitized regions on opposing sides of the gate stack in both the PMOS and said NMOS regions. Wet etching removes the n-type wet etch sensitized regions in (i) at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses or (ii) in at least a portion of said NMOS regions to form a plurality of NMOS source/drain recesses, or (i) and (ii). At least one of a compressive strain inducing epitaxial layer is formed in the plurality of PMOS source/drain recesses and a tensile strain inducing epitaxial layer is formed in the plurality of NMOS source/drain recesses.

Abstract: A method of fabricating a semiconductor device is provided. In one embodiment, a gate structure is formed on a substrate, the gate structure having a gate dielectric layer and a first polysilicon layer formed above the gate dielectric layer. A passivation layer is formed above the first polysilicon layer. A second polysilicon layer is formed above the passivation layer. The second polysilicon layer and the passivation layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed.

Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: The present disclosure provides a FinFET device and method of fabricating a FinFET device. The method includes providing a substrate, forming a fin structure on the substrate, forming a gate structure including a gate dielectric and gate electrode, the gate structure overlying a portion of the fin structure, forming a protection layer over another portion of the fin structure, and thereafter performing an implantation process to form source and drain regions.

Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of at the one or more diffusion regions being less than about 40% greater than the first width.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

Abstract: A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.

Abstract: A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration.

Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).

Abstract: A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.

Abstract: A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method may begin with providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A in-situ doped semiconductor material is formed on the first semiconductor layer adjacent to the gate structure. The dopant from the in-situ doped semiconductor material is then diffused into the first semiconductor layer to form extension regions. The method is also applicable to finFET structures.

Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si/Ge TFETs resulting in ultra-high on-chip transistor densities.

Abstract: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.

Abstract: A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types sui

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract: In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract: A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusion portion of the silicon film, forming a dummy film over the silicon film, etching the dummy film so that the dummy film is partially remained on sidewalls of the protrusion portion, etching the silicon film using the remaining dummy film to form a gate electrode, and performing ion implantation into the semiconductor substrate to form source/drain regions.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The method includes forming a gate layer on a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; forming a second oxide layer on the first oxide layer; exposing the first oxide layer by removing the second oxide layer other than on side surfaces of the gate layer by etching using a photoresist as a mask; and forming junctions in source/drain regions by implanting a high concentration of N-type ions and/or a high concentration of P-type ions using the second oxide layer as a sidewall mask.

Abstract: A semiconductor device includes a gate formed over a substrate, a junction region formed in the substrate at both sides of the gate, and a depletion region expansion prevention layer surrounding sidewalls of the junction region in the substrate.

Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abstract: A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.

Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Abstract: A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.

Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.

Abstract: A method for manufacturing a semiconductor device comprises preparing a base; forming a silicon oxide film including hydrogen or deuterium on the base; diffusing nitrogen into the silicon oxide film to form a gate insulating film; forming a gate electrode on the gate insulating film; ion doping the base to form source and drain regions along side a channel region; and forming a source electrode connected to the source region and a drain electrode connected to the drain region, the gate insulating film having a region where B/A is in the range of 1.6 to 10, where A is a concentration of nitrogen, and B is a concentration of hydrogen or deuterium, and the region is Y/10 of the thickness of the gate insulating film from the interface between the gate insulating film and the base, where Y is an average thickness of the gate insulating film.

Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material.

Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.