Abstract: A MOS semiconductor device including MOSFETs each of which has a gate portion formed on a semiconductor substrate and source/drain regions includes sidewall insulating films formed on the side portions of the gate portions in the gate length direction, alloy layers formed on the source/drain regions, taper adjusting insulating films that are formed on the side portions of the sidewall insulating films and in which a taper angle made between a cross section thereof in the gate length direction and the substrate surface is set smaller than a taper angle made between the sidewall insulating film and the substrate surface, a stress-causing insulating film that applies strains to channels and is formed to cover the gate portions, sidewall insulating films and taper adjusting insulating films, and an interlayer insulating film formed on the stress-causing insulating film.

Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes: Lower device bulk layer. Upper source and upper drain region both located atop lower device bulk layer. Both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer. Both upper drain and upper body region are shaped to form a drain-body interface. The drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region. Gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Abstract: Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor adjacent the gate stack and having at least a portion in the semiconductor substrate, wherein the stressor comprises an element for adjusting a lattice constant of the stressor. The stressor includes a lower portion and a higher portion on the lower portion, wherein the element in the lower portion has a first atomic percentage, and the element in the higher portion has a second atomic percentage substantially greater than the first atomic percentage.

Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.

Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

Abstract: A method of manufacturing a semiconductor device, which has a gate electrode and a pair of diffusion layers formed in a semiconductor substrate on sides of the gate electrode, includes forming an insulating film and a gate electrode on a semiconductor substrate, obtaining a thickness of an affected layer formed in a surface of the semiconductor substrate, forming a pair of diffusion layers by injecting an impurity element into the semiconductor substrate in areas flanking the gate electrodes based on a predetermined injection parameter, performing activating heat treatment based on a predetermined heat treatment parameter, and a parameter deriving step provided between the obtaining step and the diffusion layer forming step, the parameter deriving step deriving the injection parameter or heat treatment parameter in response to the obtained thickness of the affected layer such that the diffusion layers are set to a predetermined sheet resistance.

Abstract: A self-aligned field-effect transistor (FET) is provided. The self-aligned FET includes a substrate, a dielectric layer, conductive electrodes, and a carbon nanotube. A patterned back-gated conductive electrode is disposed in the substrate. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer and function as a source/drain. The patterned source/drain conductive electrodes contain a metal silicide such as cobalt silicide serve as a catalyst for carbon nanotube synthesis. The carbon nanotube is disposed on the dielectric layer to be electrically connected with the source/drain conductive electrodes.

Abstract: A method for manufacturing a semiconductor device, includes the steps of forming a dummy gate insulating film and a dummy gate electrode, forming source and drain regions, forming a first insulating film, forming a second insulating film, removing the second insulating film, simultaneously removing the first insulating film and the second insulating film that remains, while planarizing the first insulating film and the second insulating film that remains, forming a gate electrode trench by removing the dummy gate electrode and the dummy gate insulating film, forming a gate insulating film, and forming a gate electrode, wherein a field effect transistor is formed by the method.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.

Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber and furnishing a hydrocarbon process gas into the chamber, preferably propylene (C3H6) or toluene (C7H8) or acetylene (C2H2) or a mixture of acetylene and methane (C2H4). The process further includes inductively coupling RF plasma source power into the chamber while and applying RF plasma bias power to the wafer. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired stress (compressive or tensile). We have discovered that at a wafer temperature less than or equal to 475 degrees C.

Abstract: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.

Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Abstract: A method of manufacturing double diffused drains in a semiconductor device. An embodiment comprises forming a gate dielectric layer on a substrate, and masking and patterning the gate dielectric layer. Once the gate dielectric layer has been patterned, a second dielectric layer, having a different depth than the gate dielectric layer, is deposited into the pattern. Once the dielectric layers have been placed into a step form, DDDs are formed by implanting ions through the two dielectric layers, whose different filtering properties form the DDDS. In another embodiment the implantations through the two dielectric layers are performed using different energies to form the different dose regions. In yet another embodiment the implantations are performed using different species (light and heavy), instead of different energies, to form the different dose regions.

Abstract: A semiconductor integrated circuit is provided in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Second conductivity type source and drain regions are formed in the semiconductor film. The source region has an ultra-shallow high-density second conductivity type source extension region at a boundary with a channel region, a low-density second conductivity type source extension region under the ultra-shallow high-density second conductivity type source extension region, and a high-density second conductivity type source extension region under the low-density second conductivity type source extension region.

Abstract: A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

Abstract: A patterned anti-reflective coating may be used as a selective implant-blocking layer during fabrication of an integrated circuit transistor. In particular, the anti-reflective coating may be used as a gate sidewall spacer to block at least some dopants from an integrated circuit substrate beneath the gate sidewall spacer. Moreover, a single mask may be used when fabricating source and drain extension regions and source and drain regions of an integrated circuit transistor.

Abstract: An MOS field effect transistor which improves the mobility of electrons and holes of an nMOS and a pMOS by applying larger tensile stress to a stressed Si channel in a lateral direction than that applied to a conventional structure without increasing a Ge composition of a buffer SiGe layer, and thus achieves a faster operation speed and lower power consumption, and a method of manufacturing the MOS field effect transistor. The method of manufacturing an MOS field effect transistor includes the steps of: forming a gate electrode on a top surface of a substrate comprising a compound layer having a lattice constant different from a lattice constant of silicon, and a silicon layer via an insulating film; forming a sidewall on a side wall of the gate electrode; exposing a side wall of the compound layer; and forming a silicon film on the side wall of the compound layer in a lattice matched manner.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.

Abstract: A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose temperature increase/decrease rate is higher than that of the spike RTA, and applying the ultra-rapid rising/falling temperature annealing (second annealing) alone in a pMOS, when activating a shallow source/drain extension region.

Abstract: The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.

Abstract: An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.

Abstract: A method for producing a transistor structure with a lightly doped drain (LDD) includes structuring a gate electrode on a gate dielectric. The method also includes etching the semiconductor body or substrate to form sloping sidewails on regions adjacent to the gate electrode, and anisotropically back-etching the spacer layer to form spacers. The gate electrode is used as a mask to implant dopant to form a source region, a drain region, and regions of lower dopant concentration. Implanting dopant is performed at a first angle relative to the upper surface of the semiconductor body or substrate to form the source and drain regions, and at a second angle relative to the upper surface of the semiconductor body or substrate, and through the spacers, to form the regions of lower dopant concentration. The first angle is greater than the second angle.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device. In embodiments, the method may include forming a gate electrode on the semiconductor substrate, forming a pattern having a groove at the edge of the gate electrode and performing an etching process using the pattern as a mask, so that a groove extending from the edge of the gate electrode to LDD is formed, forming an ion diffusion barrier on the substrate having the gate electrode and the groove obtained through the previous step, implanting low-density ions onto the diffusion barrier, forming a spacer at edge of the gate electrode, and implanting high-density ions onto the substrate using the spacer and the gate electrode. A problem that may be caused by ion-implantation or diffusion process may be solved so that the hot carrier effects are improved, thereby improving the reliability of the semiconductor device.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2?; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath the LDMOS gate region, the channel interconnecting the LDMOS source and drain regions and having a laterally graded doping concentration. In order to obtain a lower parasitic capacitance coupling from the gate semiconductor region, the gate semiconductor layer region is provided with a laterally graded net doping concentration (P+N+; N+N?). A method for fabrication of the inventive LDMOS transistor device is further disclosed.

Abstract: A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

Abstract: A method for forming a strained semiconductor device is described. A substrate including a first semiconductor material and having a first conductivity type is provided. A semiconductor layer of a second conductivity type is formed contacting with the substrate, wherein the semiconductor layer includes the first semiconductor material and a second semiconductor material and has a dopant of the second conductivity type. In-situ annealing is then conducted to diffuse the dopant.

Abstract: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

Abstract: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

Abstract: A non-volatile memory device includes a buffer oxide film on a substrate; a polysilicon layer on the buffer oxide film; a silicon oxy-nitride (SiON) layer on the polysilicon layer, a first insulator layer on the SiON layer, a nitride film on the first insulator, a second insulator layer on the nitride film, an electrode on the second insulator, and a source/drain in the polysilicon layer.

Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

Abstract: A semiconductor device and/or a method of manufacturing the same that may include: Forming a gate insulating film over a semiconductor substrate in a gate region. Forming a first gate pattern over the gate insulating film. Forming a second gate pattern over the first gate pattern, such that the second gate pattern is wider than the first gate pattern. Forming sidewall spacers at both sides of the first gate pattern and the second gate pattern, such that spaces are formed between the sidewall spacers and the first gate pattern below the second gate pattern.

Abstract: A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, by ion bombardment for example, so as to inhibit subsequent diffusion of the dopant ions during thermal annealing. Low thermal budgets are favoured for the activation and polysilicon regrowth to ensure an abrupt doping profile for the source/drain regions. As a consequence an upper portion (10b) of the gate electrode remains amorphous. The upper portion of the gate electrode is removed so as to allow a low resistance contact to be made with the polysilicon lower portion (10a).

Abstract: A semiconductor device 100 includes a first gate 210, which is formed using a gate last process. The first gate 210 includes a gate insulating film formed in a bottom surface in a first concave portion formed in the insulating film; a gate electrode formed over the gate insulating film in the first concave portion; and a protective insulating film 140 formed on the gate electrode in the first concave portion. In addition, the semiconductor device 100 includes a contact 134, which is coupled to the N-type impurity-diffused region 116a in the both sides of the first gate 210 and is buried in the second concave portion having a diameter that is large than the first concave portion.

Abstract: In the non-volatile semiconductor memory in which an N-type source diffusion layer and an N-type drain diffusion layer are formed on a P-type well formed on a substrate: the source diffusion layer has a protrusion portion and a depressed portion on a cross section taken along a plane that includes (a) a straight line extending along a direction of extension of the source diffusion layer and (b) a normal line of the semiconductor substrate, and the source diffusion layer is formed of a series of (a) an upper-wall layer constituting the protrusion portion, (b) a lower-wall layer constituting the depressed portion, and (c) a side-wall layer between the upper-wall layer and the lower-wall layer; a silicide is formed to cover the upper-wall layer, the lower-wall layer, and the side-wall layer, and an insulating layer is formed to cover the silicide; and a distance d between (a) an interface between the insulating layer and the silicide formed on the upper-wall layer and (b) an interface between the insulating laye

Abstract: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

Abstract: Provided is a lateral semiconductor device with a trench structure for improving driving capability. A trench portion is formed in a well to give concave and convex portions in a gate width direction. A gate electrode is formed inside and above the trench portion with an insulating film therebetween. A source region is formed on one side of the gate electrode in a gate length direction, and a drain region is formed on the other side, both formed by impurity diffusion from polycrystalline silicon containing an impurity and filling the inside of the trench portion, deep enough to reach vicinity of the bottom of the gate electrode (vicinity of bottom of trench portion).

Abstract: Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.

Abstract: An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.

Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes: forming a photoresist film on a semiconductor substrate including a silicide forming region and non-silicide forming region; forming a photoresist pattern as a non-salicide pattern by patterning the photoresist film, so as to cover the non-silicide forming region and open the silicide forming region, with an overhang structure that a bottom is removed more compared to a top; forming a metal film on a top of the photoresist pattern and overall the semiconductor substrate in the silicide forming region; stripping the photoresist pattern and the metal film on the photoresist pattern; and forming a silicide metal film by annealing the metal film remaining on the semiconductor substrate. Therefore, the present invention simplifies a salicide process of a semiconductor device, making it possible to improve yields.

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: A semiconductor device including a substrate, a first well, a second well, a gate, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the substrate. The gate is formed on the substrate and overlaps the first and the second wells. The first doped region includes the second conductive type. The first doped region is formed in the first well and self-aligned with the gate. The second doped region includes the second conductive type. The second doped region is formed in the second well and self-aligned with the gate. The gate, the first and the second doped regions constitute a transistor.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.